1233 lines
28 KiB
C
1233 lines
28 KiB
C
/* maverick.c -- Cirrus/DSP co-processor interface.
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Copyright (C) 2003-2018 Free Software Foundation, Inc.
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Contributed by Aldy Hernandez (aldyh@redhat.com).
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <assert.h>
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#include "armdefs.h"
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#include "ansidecl.h"
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#include "armemu.h"
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/*#define CIRRUS_DEBUG 1 */
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#if CIRRUS_DEBUG
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# define printfdbg printf
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#else
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# define printfdbg printf_nothing
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#endif
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#define POS64(i) ( (~(i)) >> 63 )
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#define NEG64(i) ( (i) >> 63 )
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/* Define Co-Processor instruction handlers here. */
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/* Here's ARMulator's DSP definition. A few things to note:
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1) it has 16 64-bit registers and 4 72-bit accumulators
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2) you can only access its registers with MCR and MRC. */
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/* We can't define these in here because this file might not be linked
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unless the target is arm9e-*. They are defined in wrapper.c.
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Eventually the simulator should be made to handle any coprocessor
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at run time. */
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struct maverick_regs
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{
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union
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{
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int i;
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float f;
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} upper;
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union
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{
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int i;
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float f;
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} lower;
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};
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union maverick_acc_regs
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{
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long double ld; /* Acc registers are 72-bits. */
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};
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struct maverick_regs DSPregs[16];
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union maverick_acc_regs DSPacc[4];
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ARMword DSPsc;
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#define DEST_REG (BITS (12, 15))
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#define SRC1_REG (BITS (16, 19))
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#define SRC2_REG (BITS (0, 3))
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static int lsw_int_index, msw_int_index;
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static int lsw_float_index, msw_float_index;
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static double mv_getRegDouble (int);
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static long long mv_getReg64int (int);
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static void mv_setRegDouble (int, double val);
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static void mv_setReg64int (int, long long val);
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static union
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{
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double d;
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long long ll;
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int ints[2];
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} reg_conv;
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static void
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printf_nothing (void * foo, ...)
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{
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}
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static void
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cirrus_not_implemented (char * insn)
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{
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fprintf (stderr, "Cirrus instruction '%s' not implemented.\n", insn);
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fprintf (stderr, "aborting!\n");
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exit (1);
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}
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unsigned
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DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED,
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unsigned type ATTRIBUTE_UNUSED,
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ARMword instr,
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ARMword * value)
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{
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switch (BITS (5, 7))
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{
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case 0: /* cfmvrdl */
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/* Move lower half of a DF stored in a DSP reg into an Arm reg. */
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printfdbg ("cfmvrdl\n");
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printfdbg ("\tlower half=0x%x\n", DSPregs[SRC1_REG].lower.i);
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printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG));
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*value = (ARMword) DSPregs[SRC1_REG].lower.i;
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break;
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case 1: /* cfmvrdh */
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/* Move upper half of a DF stored in a DSP reg into an Arm reg. */
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printfdbg ("cfmvrdh\n");
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printfdbg ("\tupper half=0x%x\n", DSPregs[SRC1_REG].upper.i);
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printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG));
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*value = (ARMword) DSPregs[SRC1_REG].upper.i;
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break;
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case 2: /* cfmvrs */
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/* Move SF from upper half of a DSP register to an Arm register. */
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*value = (ARMword) DSPregs[SRC1_REG].upper.i;
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printfdbg ("cfmvrs = mvf%d <-- %f\n",
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SRC1_REG,
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DSPregs[SRC1_REG].upper.f);
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break;
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#ifdef doesnt_work
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case 4: /* cfcmps */
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{
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float a, b;
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int n, z, c, v;
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a = DSPregs[SRC1_REG].upper.f;
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b = DSPregs[SRC2_REG].upper.f;
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printfdbg ("cfcmps\n");
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printfdbg ("\tcomparing %f and %f\n", a, b);
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z = a == b; /* zero */
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n = a != b; /* negative */
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v = a > b; /* overflow */
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c = 0; /* carry */
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*value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
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break;
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}
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case 5: /* cfcmpd */
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{
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double a, b;
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int n, z, c, v;
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a = mv_getRegDouble (SRC1_REG);
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b = mv_getRegDouble (SRC2_REG);
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printfdbg ("cfcmpd\n");
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printfdbg ("\tcomparing %g and %g\n", a, b);
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z = a == b; /* zero */
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n = a != b; /* negative */
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v = a > b; /* overflow */
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c = 0; /* carry */
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*value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
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break;
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}
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#else
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case 4: /* cfcmps */
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{
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float a, b;
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int n, z, c, v;
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a = DSPregs[SRC1_REG].upper.f;
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b = DSPregs[SRC2_REG].upper.f;
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printfdbg ("cfcmps\n");
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printfdbg ("\tcomparing %f and %f\n", a, b);
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z = a == b; /* zero */
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n = a < b; /* negative */
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c = a > b; /* carry */
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v = 0; /* fixme */
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printfdbg ("\tz = %d, n = %d\n", z, n);
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*value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
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break;
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}
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case 5: /* cfcmpd */
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{
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double a, b;
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int n, z, c, v;
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a = mv_getRegDouble (SRC1_REG);
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b = mv_getRegDouble (SRC2_REG);
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printfdbg ("cfcmpd\n");
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printfdbg ("\tcomparing %g and %g\n", a, b);
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z = a == b; /* zero */
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n = a < b; /* negative */
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c = a > b; /* carry */
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v = 0; /* fixme */
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*value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
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break;
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}
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#endif
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default:
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fprintf (stderr, "unknown opcode in DSPMRC4 0x%x\n", instr);
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cirrus_not_implemented ("unknown");
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break;
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}
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return ARMul_DONE;
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}
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unsigned
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DSPMRC5 (ARMul_State * state ATTRIBUTE_UNUSED,
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unsigned type ATTRIBUTE_UNUSED,
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ARMword instr,
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ARMword * value)
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{
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switch (BITS (5, 7))
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{
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case 0: /* cfmvr64l */
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/* Move lower half of 64bit int from Cirrus to Arm. */
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*value = (ARMword) DSPregs[SRC1_REG].lower.i;
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printfdbg ("cfmvr64l ARM_REG = mvfx%d <-- %d\n",
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DEST_REG,
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(int) *value);
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break;
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case 1: /* cfmvr64h */
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/* Move upper half of 64bit int from Cirrus to Arm. */
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*value = (ARMword) DSPregs[SRC1_REG].upper.i;
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printfdbg ("cfmvr64h <-- %d\n", (int) *value);
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break;
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case 4: /* cfcmp32 */
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{
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int res;
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int n, z, c, v;
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unsigned int a, b;
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printfdbg ("cfcmp32 mvfx%d - mvfx%d\n",
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SRC1_REG,
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SRC2_REG);
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/* FIXME: see comment for cfcmps. */
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a = DSPregs[SRC1_REG].lower.i;
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b = DSPregs[SRC2_REG].lower.i;
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res = DSPregs[SRC1_REG].lower.i - DSPregs[SRC2_REG].lower.i;
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/* zero */
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z = res == 0;
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/* negative */
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n = res < 0;
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/* overflow */
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v = SubOverflow (DSPregs[SRC1_REG].lower.i, DSPregs[SRC2_REG].lower.i,
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res);
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/* carry */
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c = (NEG (a) && POS (b))
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|| (NEG (a) && POS (res))
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|| (POS (b) && POS (res));
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*value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
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break;
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}
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case 5: /* cfcmp64 */
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{
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long long res;
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int n, z, c, v;
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unsigned long long a, b;
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printfdbg ("cfcmp64 mvdx%d - mvdx%d\n",
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SRC1_REG,
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SRC2_REG);
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/* fixme: see comment for cfcmps. */
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a = mv_getReg64int (SRC1_REG);
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b = mv_getReg64int (SRC2_REG);
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res = mv_getReg64int (SRC1_REG) - mv_getReg64int (SRC2_REG);
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/* zero */
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z = res == 0;
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/* negative */
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n = res < 0;
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/* overflow */
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v = ((NEG64 (a) && POS64 (b) && POS64 (res))
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|| (POS64 (a) && NEG64 (b) && NEG64 (res)));
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/* carry */
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c = (NEG64 (a) && POS64 (b))
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|| (NEG64 (a) && POS64 (res))
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|| (POS64 (b) && POS64 (res));
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*value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
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break;
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}
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default:
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fprintf (stderr, "unknown opcode in DSPMRC5 0x%x\n", instr);
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cirrus_not_implemented ("unknown");
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break;
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}
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return ARMul_DONE;
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}
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unsigned
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DSPMRC6 (ARMul_State * state ATTRIBUTE_UNUSED,
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unsigned type ATTRIBUTE_UNUSED,
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ARMword instr,
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ARMword * value)
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{
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switch (BITS (5, 7))
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{
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case 0: /* cfmval32 */
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cirrus_not_implemented ("cfmval32");
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break;
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case 1: /* cfmvam32 */
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cirrus_not_implemented ("cfmvam32");
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break;
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case 2: /* cfmvah32 */
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cirrus_not_implemented ("cfmvah32");
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break;
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case 3: /* cfmva32 */
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cirrus_not_implemented ("cfmva32");
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break;
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case 4: /* cfmva64 */
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cirrus_not_implemented ("cfmva64");
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break;
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case 5: /* cfmvsc32 */
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cirrus_not_implemented ("cfmvsc32");
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break;
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default:
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fprintf (stderr, "unknown opcode in DSPMRC6 0x%x\n", instr);
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cirrus_not_implemented ("unknown");
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break;
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}
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return ARMul_DONE;
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}
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unsigned
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DSPMCR4 (ARMul_State * state,
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unsigned type ATTRIBUTE_UNUSED,
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ARMword instr,
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ARMword value)
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{
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switch (BITS (5, 7))
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{
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case 0: /* cfmvdlr */
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/* Move the lower half of a DF value from an Arm register into
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the lower half of a Cirrus register. */
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printfdbg ("cfmvdlr <-- 0x%x\n", (int) value);
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DSPregs[SRC1_REG].lower.i = (int) value;
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break;
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case 1: /* cfmvdhr */
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/* Move the upper half of a DF value from an Arm register into
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the upper half of a Cirrus register. */
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printfdbg ("cfmvdhr <-- 0x%x\n", (int) value);
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DSPregs[SRC1_REG].upper.i = (int) value;
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break;
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case 2: /* cfmvsr */
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/* Move SF from Arm register into upper half of Cirrus register. */
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printfdbg ("cfmvsr <-- 0x%x\n", (int) value);
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DSPregs[SRC1_REG].upper.i = (int) value;
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break;
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default:
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fprintf (stderr, "unknown opcode in DSPMCR4 0x%x\n", instr);
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cirrus_not_implemented ("unknown");
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break;
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}
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return ARMul_DONE;
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}
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unsigned
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DSPMCR5 (ARMul_State * state,
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unsigned type ATTRIBUTE_UNUSED,
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ARMword instr,
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ARMword value)
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{
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union
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{
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int s;
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unsigned int us;
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} val;
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switch (BITS (5, 7))
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{
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case 0: /* cfmv64lr */
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/* Move lower half of a 64bit int from an ARM register into the
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lower half of a DSP register and sign extend it. */
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printfdbg ("cfmv64lr mvdx%d <-- 0x%x\n", SRC1_REG, (int) value);
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DSPregs[SRC1_REG].lower.i = (int) value;
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break;
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case 1: /* cfmv64hr */
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/* Move upper half of a 64bit int from an ARM register into the
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upper half of a DSP register. */
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printfdbg ("cfmv64hr ARM_REG = mvfx%d <-- 0x%x\n",
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SRC1_REG,
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(int) value);
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DSPregs[SRC1_REG].upper.i = (int) value;
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break;
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case 2: /* cfrshl32 */
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printfdbg ("cfrshl32\n");
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val.us = value;
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if (val.s > 0)
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DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i << value;
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else
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DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -value;
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break;
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case 3: /* cfrshl64 */
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printfdbg ("cfrshl64\n");
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val.us = value;
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if (val.s > 0)
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mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) << value);
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else
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mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) >> -value);
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break;
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default:
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fprintf (stderr, "unknown opcode in DSPMCR5 0x%x\n", instr);
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cirrus_not_implemented ("unknown");
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break;
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}
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return ARMul_DONE;
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}
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unsigned
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DSPMCR6 (ARMul_State * state,
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unsigned type ATTRIBUTE_UNUSED,
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ARMword instr,
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ARMword value)
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{
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switch (BITS (5, 7))
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{
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case 0: /* cfmv32al */
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cirrus_not_implemented ("cfmv32al");
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break;
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case 1: /* cfmv32am */
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cirrus_not_implemented ("cfmv32am");
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break;
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case 2: /* cfmv32ah */
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cirrus_not_implemented ("cfmv32ah");
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break;
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case 3: /* cfmv32a */
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cirrus_not_implemented ("cfmv32a");
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break;
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case 4: /* cfmv64a */
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cirrus_not_implemented ("cfmv64a");
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break;
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case 5: /* cfmv32sc */
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cirrus_not_implemented ("cfmv32sc");
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break;
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default:
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fprintf (stderr, "unknown opcode in DSPMCR6 0x%x\n", instr);
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cirrus_not_implemented ("unknown");
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break;
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}
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return ARMul_DONE;
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}
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unsigned
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DSPLDC4 (ARMul_State * state ATTRIBUTE_UNUSED,
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unsigned type,
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ARMword instr,
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ARMword data)
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{
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static unsigned words;
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if (type != ARMul_DATA)
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{
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words = 0;
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return ARMul_DONE;
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}
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if (BIT (22))
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{ /* it's a long access, get two words */
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/* cfldrd */
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printfdbg ("cfldrd: %x (words = %d) (bigend = %d) DESTREG = %d\n",
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data, words, state->bigendSig, DEST_REG);
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if (words == 0)
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{
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if (state->bigendSig)
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DSPregs[DEST_REG].upper.i = (int) data;
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else
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DSPregs[DEST_REG].lower.i = (int) data;
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}
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else
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{
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if (state->bigendSig)
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DSPregs[DEST_REG].lower.i = (int) data;
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else
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DSPregs[DEST_REG].upper.i = (int) data;
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}
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++ words;
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if (words == 2)
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{
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printfdbg ("\tmvd%d <-- mem = %g\n", DEST_REG,
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mv_getRegDouble (DEST_REG));
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return ARMul_DONE;
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}
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else
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return ARMul_INC;
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}
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else
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{
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/* Get just one word. */
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|
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/* cfldrs */
|
|
printfdbg ("cfldrs\n");
|
|
|
|
DSPregs[DEST_REG].upper.i = (int) data;
|
|
|
|
printfdbg ("\tmvf%d <-- mem = %f\n", DEST_REG,
|
|
DSPregs[DEST_REG].upper.f);
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
}
|
|
|
|
unsigned
|
|
DSPLDC5 (ARMul_State * state ATTRIBUTE_UNUSED,
|
|
unsigned type,
|
|
ARMword instr,
|
|
ARMword data)
|
|
{
|
|
static unsigned words;
|
|
|
|
if (type != ARMul_DATA)
|
|
{
|
|
words = 0;
|
|
return ARMul_DONE;
|
|
}
|
|
|
|
if (BIT (22))
|
|
{
|
|
/* It's a long access, get two words. */
|
|
|
|
/* cfldr64 */
|
|
printfdbg ("cfldr64: %d\n", data);
|
|
|
|
if (words == 0)
|
|
{
|
|
if (state->bigendSig)
|
|
DSPregs[DEST_REG].upper.i = (int) data;
|
|
else
|
|
DSPregs[DEST_REG].lower.i = (int) data;
|
|
}
|
|
else
|
|
{
|
|
if (state->bigendSig)
|
|
DSPregs[DEST_REG].lower.i = (int) data;
|
|
else
|
|
DSPregs[DEST_REG].upper.i = (int) data;
|
|
}
|
|
|
|
++ words;
|
|
|
|
if (words == 2)
|
|
{
|
|
printfdbg ("\tmvdx%d <-- mem = %lld\n", DEST_REG,
|
|
mv_getReg64int (DEST_REG));
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
else
|
|
return ARMul_INC;
|
|
}
|
|
else
|
|
{
|
|
/* Get just one word. */
|
|
|
|
/* cfldr32 */
|
|
printfdbg ("cfldr32 mvfx%d <-- %d\n", DEST_REG, (int) data);
|
|
|
|
/* 32bit ints should be sign extended to 64bits when loaded. */
|
|
mv_setReg64int (DEST_REG, (long long) data);
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
}
|
|
|
|
unsigned
|
|
DSPSTC4 (ARMul_State * state ATTRIBUTE_UNUSED,
|
|
unsigned type,
|
|
ARMword instr,
|
|
ARMword * data)
|
|
{
|
|
static unsigned words;
|
|
|
|
if (type != ARMul_DATA)
|
|
{
|
|
words = 0;
|
|
return ARMul_DONE;
|
|
}
|
|
|
|
if (BIT (22))
|
|
{
|
|
/* It's a long access, get two words. */
|
|
/* cfstrd */
|
|
printfdbg ("cfstrd\n");
|
|
|
|
if (words == 0)
|
|
{
|
|
if (state->bigendSig)
|
|
*data = (ARMword) DSPregs[DEST_REG].upper.i;
|
|
else
|
|
*data = (ARMword) DSPregs[DEST_REG].lower.i;
|
|
}
|
|
else
|
|
{
|
|
if (state->bigendSig)
|
|
*data = (ARMword) DSPregs[DEST_REG].lower.i;
|
|
else
|
|
*data = (ARMword) DSPregs[DEST_REG].upper.i;
|
|
}
|
|
|
|
++ words;
|
|
|
|
if (words == 2)
|
|
{
|
|
printfdbg ("\tmem = mvd%d = %g\n", DEST_REG,
|
|
mv_getRegDouble (DEST_REG));
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
else
|
|
return ARMul_INC;
|
|
}
|
|
else
|
|
{
|
|
/* Get just one word. */
|
|
/* cfstrs */
|
|
printfdbg ("cfstrs mvf%d <-- %f\n", DEST_REG,
|
|
DSPregs[DEST_REG].upper.f);
|
|
|
|
*data = (ARMword) DSPregs[DEST_REG].upper.i;
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
}
|
|
|
|
unsigned
|
|
DSPSTC5 (ARMul_State * state ATTRIBUTE_UNUSED,
|
|
unsigned type,
|
|
ARMword instr,
|
|
ARMword * data)
|
|
{
|
|
static unsigned words;
|
|
|
|
if (type != ARMul_DATA)
|
|
{
|
|
words = 0;
|
|
return ARMul_DONE;
|
|
}
|
|
|
|
if (BIT (22))
|
|
{
|
|
/* It's a long access, store two words. */
|
|
/* cfstr64 */
|
|
printfdbg ("cfstr64\n");
|
|
|
|
if (words == 0)
|
|
{
|
|
if (state->bigendSig)
|
|
*data = (ARMword) DSPregs[DEST_REG].upper.i;
|
|
else
|
|
*data = (ARMword) DSPregs[DEST_REG].lower.i;
|
|
}
|
|
else
|
|
{
|
|
if (state->bigendSig)
|
|
*data = (ARMword) DSPregs[DEST_REG].lower.i;
|
|
else
|
|
*data = (ARMword) DSPregs[DEST_REG].upper.i;
|
|
}
|
|
|
|
++ words;
|
|
|
|
if (words == 2)
|
|
{
|
|
printfdbg ("\tmem = mvd%d = %lld\n", DEST_REG,
|
|
mv_getReg64int (DEST_REG));
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
else
|
|
return ARMul_INC;
|
|
}
|
|
else
|
|
{
|
|
/* Store just one word. */
|
|
/* cfstr32 */
|
|
*data = (ARMword) DSPregs[DEST_REG].lower.i;
|
|
|
|
printfdbg ("cfstr32 MEM = %d\n", (int) *data);
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
}
|
|
|
|
unsigned
|
|
DSPCDP4 (ARMul_State * state,
|
|
unsigned type,
|
|
ARMword instr)
|
|
{
|
|
int opcode2;
|
|
|
|
opcode2 = BITS (5,7);
|
|
|
|
switch (BITS (20,21))
|
|
{
|
|
case 0:
|
|
switch (opcode2)
|
|
{
|
|
case 0: /* cfcpys */
|
|
printfdbg ("cfcpys mvf%d = mvf%d = %f\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
DSPregs[SRC1_REG].upper.f);
|
|
DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f;
|
|
break;
|
|
|
|
case 1: /* cfcpyd */
|
|
printfdbg ("cfcpyd mvd%d = mvd%d = %g\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
mv_getRegDouble (SRC1_REG));
|
|
mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG));
|
|
break;
|
|
|
|
case 2: /* cfcvtds */
|
|
printfdbg ("cfcvtds mvf%d = (float) mvd%d = %f\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
(float) mv_getRegDouble (SRC1_REG));
|
|
DSPregs[DEST_REG].upper.f = (float) mv_getRegDouble (SRC1_REG);
|
|
break;
|
|
|
|
case 3: /* cfcvtsd */
|
|
printfdbg ("cfcvtsd mvd%d = mvf%d = %g\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
(double) DSPregs[SRC1_REG].upper.f);
|
|
mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].upper.f);
|
|
break;
|
|
|
|
case 4: /* cfcvt32s */
|
|
printfdbg ("cfcvt32s mvf%d = mvfx%d = %f\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
(float) DSPregs[SRC1_REG].lower.i);
|
|
DSPregs[DEST_REG].upper.f = (float) DSPregs[SRC1_REG].lower.i;
|
|
break;
|
|
|
|
case 5: /* cfcvt32d */
|
|
printfdbg ("cfcvt32d mvd%d = mvfx%d = %g\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
(double) DSPregs[SRC1_REG].lower.i);
|
|
mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].lower.i);
|
|
break;
|
|
|
|
case 6: /* cfcvt64s */
|
|
printfdbg ("cfcvt64s mvf%d = mvdx%d = %f\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
(float) mv_getReg64int (SRC1_REG));
|
|
DSPregs[DEST_REG].upper.f = (float) mv_getReg64int (SRC1_REG);
|
|
break;
|
|
|
|
case 7: /* cfcvt64d */
|
|
printfdbg ("cfcvt64d mvd%d = mvdx%d = %g\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
(double) mv_getReg64int (SRC1_REG));
|
|
mv_setRegDouble (DEST_REG, (double) mv_getReg64int (SRC1_REG));
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 1:
|
|
switch (opcode2)
|
|
{
|
|
case 0: /* cfmuls */
|
|
printfdbg ("cfmuls mvf%d = mvf%d = %f\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
DSPregs[SRC1_REG].upper.f * DSPregs[SRC2_REG].upper.f);
|
|
|
|
DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f
|
|
* DSPregs[SRC2_REG].upper.f;
|
|
break;
|
|
|
|
case 1: /* cfmuld */
|
|
printfdbg ("cfmuld mvd%d = mvd%d = %g\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
mv_getRegDouble (SRC1_REG) * mv_getRegDouble (SRC2_REG));
|
|
|
|
mv_setRegDouble (DEST_REG,
|
|
mv_getRegDouble (SRC1_REG)
|
|
* mv_getRegDouble (SRC2_REG));
|
|
break;
|
|
|
|
default:
|
|
fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr);
|
|
cirrus_not_implemented ("unknown");
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 3:
|
|
switch (opcode2)
|
|
{
|
|
case 0: /* cfabss */
|
|
DSPregs[DEST_REG].upper.f = (DSPregs[SRC1_REG].upper.f < 0.0F ?
|
|
-DSPregs[SRC1_REG].upper.f
|
|
: DSPregs[SRC1_REG].upper.f);
|
|
printfdbg ("cfabss mvf%d = |mvf%d| = %f\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
DSPregs[DEST_REG].upper.f);
|
|
break;
|
|
|
|
case 1: /* cfabsd */
|
|
mv_setRegDouble (DEST_REG,
|
|
(mv_getRegDouble (SRC1_REG) < 0.0 ?
|
|
-mv_getRegDouble (SRC1_REG)
|
|
: mv_getRegDouble (SRC1_REG)));
|
|
printfdbg ("cfabsd mvd%d = |mvd%d| = %g\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
mv_getRegDouble (DEST_REG));
|
|
break;
|
|
|
|
case 2: /* cfnegs */
|
|
DSPregs[DEST_REG].upper.f = -DSPregs[SRC1_REG].upper.f;
|
|
printfdbg ("cfnegs mvf%d = -mvf%d = %f\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
DSPregs[DEST_REG].upper.f);
|
|
break;
|
|
|
|
case 3: /* cfnegd */
|
|
mv_setRegDouble (DEST_REG,
|
|
-mv_getRegDouble (SRC1_REG));
|
|
printfdbg ("cfnegd mvd%d = -mvd%d = %g\n",
|
|
DEST_REG, DEST_REG,
|
|
mv_getRegDouble (DEST_REG));
|
|
break;
|
|
|
|
case 4: /* cfadds */
|
|
DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f
|
|
+ DSPregs[SRC2_REG].upper.f;
|
|
printfdbg ("cfadds mvf%d = mvf%d + mvf%d = %f\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
DSPregs[DEST_REG].upper.f);
|
|
break;
|
|
|
|
case 5: /* cfaddd */
|
|
mv_setRegDouble (DEST_REG,
|
|
mv_getRegDouble (SRC1_REG)
|
|
+ mv_getRegDouble (SRC2_REG));
|
|
printfdbg ("cfaddd: mvd%d = mvd%d + mvd%d = %g\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
mv_getRegDouble (DEST_REG));
|
|
break;
|
|
|
|
case 6: /* cfsubs */
|
|
DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f
|
|
- DSPregs[SRC2_REG].upper.f;
|
|
printfdbg ("cfsubs: mvf%d = mvf%d - mvf%d = %f\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
DSPregs[DEST_REG].upper.f);
|
|
break;
|
|
|
|
case 7: /* cfsubd */
|
|
mv_setRegDouble (DEST_REG,
|
|
mv_getRegDouble (SRC1_REG)
|
|
- mv_getRegDouble (SRC2_REG));
|
|
printfdbg ("cfsubd: mvd%d = mvd%d - mvd%d = %g\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
mv_getRegDouble (DEST_REG));
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr);
|
|
cirrus_not_implemented ("unknown");
|
|
break;
|
|
}
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
|
|
unsigned
|
|
DSPCDP5 (ARMul_State * state,
|
|
unsigned type,
|
|
ARMword instr)
|
|
{
|
|
int opcode2;
|
|
char shift;
|
|
|
|
opcode2 = BITS (5,7);
|
|
|
|
/* Shift constants are 7bit signed numbers in bits 0..3|5..7. */
|
|
shift = BITS (0, 3) | (BITS (5, 7)) << 4;
|
|
if (shift & 0x40)
|
|
shift |= 0xc0;
|
|
|
|
switch (BITS (20,21))
|
|
{
|
|
case 0:
|
|
/* cfsh32 */
|
|
printfdbg ("cfsh32 %s amount=%d\n", shift < 0 ? "right" : "left",
|
|
shift);
|
|
if (shift < 0)
|
|
/* Negative shift is a right shift. */
|
|
DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -shift;
|
|
else
|
|
/* Positive shift is a left shift. */
|
|
DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i << shift;
|
|
break;
|
|
|
|
case 1:
|
|
switch (opcode2)
|
|
{
|
|
case 0: /* cfmul32 */
|
|
DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
|
|
* DSPregs[SRC2_REG].lower.i;
|
|
printfdbg ("cfmul32 mvfx%d = mvfx%d * mvfx%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 1: /* cfmul64 */
|
|
mv_setReg64int (DEST_REG,
|
|
mv_getReg64int (SRC1_REG)
|
|
* mv_getReg64int (SRC2_REG));
|
|
printfdbg ("cfmul64 mvdx%d = mvdx%d * mvdx%d = %lld\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
mv_getReg64int (DEST_REG));
|
|
break;
|
|
|
|
case 2: /* cfmac32 */
|
|
DSPregs[DEST_REG].lower.i
|
|
+= DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i;
|
|
printfdbg ("cfmac32 mvfx%d += mvfx%d * mvfx%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 3: /* cfmsc32 */
|
|
DSPregs[DEST_REG].lower.i
|
|
-= DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i;
|
|
printfdbg ("cfmsc32 mvfx%d -= mvfx%d * mvfx%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 4: /* cfcvts32 */
|
|
/* fixme: this should round */
|
|
DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f;
|
|
printfdbg ("cfcvts32 mvfx%d = mvf%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 5: /* cfcvtd32 */
|
|
/* fixme: this should round */
|
|
DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG);
|
|
printfdbg ("cfcvtd32 mvdx%d = mvd%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 6: /* cftruncs32 */
|
|
DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f;
|
|
printfdbg ("cftruncs32 mvfx%d = mvf%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 7: /* cftruncd32 */
|
|
DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG);
|
|
printfdbg ("cftruncd32 mvfx%d = mvd%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 2:
|
|
/* cfsh64 */
|
|
printfdbg ("cfsh64\n");
|
|
|
|
if (shift < 0)
|
|
/* Negative shift is a right shift. */
|
|
mv_setReg64int (DEST_REG,
|
|
mv_getReg64int (SRC1_REG) >> -shift);
|
|
else
|
|
/* Positive shift is a left shift. */
|
|
mv_setReg64int (DEST_REG,
|
|
mv_getReg64int (SRC1_REG) << shift);
|
|
printfdbg ("\t%llx\n", mv_getReg64int(DEST_REG));
|
|
break;
|
|
|
|
case 3:
|
|
switch (opcode2)
|
|
{
|
|
case 0: /* cfabs32 */
|
|
DSPregs[DEST_REG].lower.i = (DSPregs[SRC1_REG].lower.i < 0
|
|
? -DSPregs[SRC1_REG].lower.i : DSPregs[SRC1_REG].lower.i);
|
|
printfdbg ("cfabs32 mvfx%d = |mvfx%d| = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 1: /* cfabs64 */
|
|
mv_setReg64int (DEST_REG,
|
|
(mv_getReg64int (SRC1_REG) < 0
|
|
? -mv_getReg64int (SRC1_REG)
|
|
: mv_getReg64int (SRC1_REG)));
|
|
printfdbg ("cfabs64 mvdx%d = |mvdx%d| = %lld\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
mv_getReg64int (DEST_REG));
|
|
break;
|
|
|
|
case 2: /* cfneg32 */
|
|
DSPregs[DEST_REG].lower.i = -DSPregs[SRC1_REG].lower.i;
|
|
printfdbg ("cfneg32 mvfx%d = -mvfx%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 3: /* cfneg64 */
|
|
mv_setReg64int (DEST_REG, -mv_getReg64int (SRC1_REG));
|
|
printfdbg ("cfneg64 mvdx%d = -mvdx%d = %lld\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
mv_getReg64int (DEST_REG));
|
|
break;
|
|
|
|
case 4: /* cfadd32 */
|
|
DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
|
|
+ DSPregs[SRC2_REG].lower.i;
|
|
printfdbg ("cfadd32 mvfx%d = mvfx%d + mvfx%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 5: /* cfadd64 */
|
|
mv_setReg64int (DEST_REG,
|
|
mv_getReg64int (SRC1_REG)
|
|
+ mv_getReg64int (SRC2_REG));
|
|
printfdbg ("cfadd64 mvdx%d = mvdx%d + mvdx%d = %lld\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
mv_getReg64int (DEST_REG));
|
|
break;
|
|
|
|
case 6: /* cfsub32 */
|
|
DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
|
|
- DSPregs[SRC2_REG].lower.i;
|
|
printfdbg ("cfsub32 mvfx%d = mvfx%d - mvfx%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
DSPregs[DEST_REG].lower.i);
|
|
break;
|
|
|
|
case 7: /* cfsub64 */
|
|
mv_setReg64int (DEST_REG,
|
|
mv_getReg64int (SRC1_REG)
|
|
- mv_getReg64int (SRC2_REG));
|
|
printfdbg ("cfsub64 mvdx%d = mvdx%d - mvdx%d = %d\n",
|
|
DEST_REG,
|
|
SRC1_REG,
|
|
SRC2_REG,
|
|
mv_getReg64int (DEST_REG));
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
fprintf (stderr, "unknown opcode in DSPCDP5 0x%x\n", instr);
|
|
cirrus_not_implemented ("unknown");
|
|
break;
|
|
}
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
|
|
unsigned
|
|
DSPCDP6 (ARMul_State * state,
|
|
unsigned type,
|
|
ARMword instr)
|
|
{
|
|
switch (BITS (20,21))
|
|
{
|
|
case 0:
|
|
/* cfmadd32 */
|
|
cirrus_not_implemented ("cfmadd32");
|
|
break;
|
|
|
|
case 1:
|
|
/* cfmsub32 */
|
|
cirrus_not_implemented ("cfmsub32");
|
|
break;
|
|
|
|
case 2:
|
|
/* cfmadda32 */
|
|
cirrus_not_implemented ("cfmadda32");
|
|
break;
|
|
|
|
case 3:
|
|
/* cfmsuba32 */
|
|
cirrus_not_implemented ("cfmsuba32");
|
|
break;
|
|
|
|
default:
|
|
fprintf (stderr, "unknown opcode in DSPCDP6 0x%x\n", instr);
|
|
}
|
|
|
|
return ARMul_DONE;
|
|
}
|
|
|
|
/* Conversion functions.
|
|
|
|
32-bit integers are stored in the LOWER half of a 64-bit physical
|
|
register.
|
|
|
|
Single precision floats are stored in the UPPER half of a 64-bit
|
|
physical register. */
|
|
|
|
static double
|
|
mv_getRegDouble (int regnum)
|
|
{
|
|
reg_conv.ints[lsw_float_index] = DSPregs[regnum].upper.i;
|
|
reg_conv.ints[msw_float_index] = DSPregs[regnum].lower.i;
|
|
return reg_conv.d;
|
|
}
|
|
|
|
static void
|
|
mv_setRegDouble (int regnum, double val)
|
|
{
|
|
reg_conv.d = val;
|
|
DSPregs[regnum].upper.i = reg_conv.ints[lsw_float_index];
|
|
DSPregs[regnum].lower.i = reg_conv.ints[msw_float_index];
|
|
}
|
|
|
|
static long long
|
|
mv_getReg64int (int regnum)
|
|
{
|
|
reg_conv.ints[lsw_int_index] = DSPregs[regnum].lower.i;
|
|
reg_conv.ints[msw_int_index] = DSPregs[regnum].upper.i;
|
|
return reg_conv.ll;
|
|
}
|
|
|
|
static void
|
|
mv_setReg64int (int regnum, long long val)
|
|
{
|
|
reg_conv.ll = val;
|
|
DSPregs[regnum].lower.i = reg_conv.ints[lsw_int_index];
|
|
DSPregs[regnum].upper.i = reg_conv.ints[msw_int_index];
|
|
}
|