b6f8c7c452
On x86, some instructions have alternate shorter encodings:
1. When the upper 32 bits of destination registers of
andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64
known to be zero, we can encode them without the REX_W bit:
andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32
This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates. This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions. When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:
VOP %reg, %reg, %dest_reg
can be encoded with
VOP128 %reg, %reg, %dest_reg
This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate. This optimization is
enabled with -Os.
This patch does:
1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.
gas/
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
opcodes/
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
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2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/22871
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* i386-gen.c (opcode_modifiers): Add Optimize.
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* i386-opc.h (Optimize): New enum.
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(i386_opcode_modifier): Add optimize.
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* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
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"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
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"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
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"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
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vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
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vpxord and vpxorq.
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* i386-tbl.h: Regenerated.
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2018-02-26 Alan Modra <amodra@gmail.com>
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* crx-dis.c (getregliststring): Allocate a large enough buffer
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to silence false positive gcc8 warning.
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2018-02-22 Shea Levy <shea@shealevy.com>
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* disassemble.c (ARCH_riscv): Define if ARCH_all.
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2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Add {rex},
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* i386-tbl.h: Regenerated.
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2018-02-20 Maciej W. Rozycki <macro@mips.com>
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* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
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(mips16_opcodes): Replace `M' with `m' for "restore".
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2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (thumb_opcodes): Fix BXNS mask.
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2018-02-13 Maciej W. Rozycki <macro@mips.com>
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* wasm32-dis.c (print_insn_wasm32): Rename `index' local
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variable to `function_index'.
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2018-02-13 Nick Clifton <nickc@redhat.com>
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PR 22823
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* metag-dis.c (print_fmmov): Double buffer size to avoid warning
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about truncation of printing.
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2018-02-12 Henry Wong <henry@stuffedcow.net>
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* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
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2018-02-05 Nick Clifton <nickc@redhat.com>
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* po/pt_BR.po: Updated Brazilian Portuguese translation.
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2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-dis.c (enum): Add pconfig.
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* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
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(cpu_flags): Add CpuPCONFIG.
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* i386-opc.h (enum): Add CpuPCONFIG.
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(i386_cpu_flags): Add cpupconfig.
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* i386-opc.tbl: Add PCONFIG instruction.
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* i386-init.h: Regenerate.
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* i386-tbl.h: Likewise.
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2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-dis.c (enum): Add PREFIX_0F09.
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* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
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(cpu_flags): Add CpuWBNOINVD.
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* i386-opc.h (enum): Add CpuWBNOINVD.
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(i386_cpu_flags): Add cpuwbnoinvd.
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* i386-opc.tbl: Add WBNOINVD instruction.
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* i386-init.h: Regenerate.
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* i386-tbl.h: Likewise.
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2018-01-17 Jim Wilson <jimw@sifive.com>
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* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
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2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
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Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
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CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
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(cpu_flags): Add CpuIBT, CpuSHSTK.
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* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
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(i386_cpu_flags): Add cpuibt, cpushstk.
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* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
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* i386-init.h: Regenerate.
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* i386-tbl.h: Likewise.
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2018-01-16 Nick Clifton <nickc@redhat.com>
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* po/pt_BR.po: Updated Brazilian Portugese translation.
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* po/de.po: Updated German translation.
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2018-01-15 Jim Wilson <jimw@sifive.com>
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* riscv-opc.c (match_c_nop): New.
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(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
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2018-01-15 Nick Clifton <nickc@redhat.com>
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* po/uk.po: Updated Ukranian translation.
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2018-01-13 Nick Clifton <nickc@redhat.com>
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* po/opcodes.pot: Regenerated.
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2018-01-13 Nick Clifton <nickc@redhat.com>
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* configure: Regenerate.
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2018-01-13 Nick Clifton <nickc@redhat.com>
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2.30 branch created.
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2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
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* i386-tbl.h: Regenerate.
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2018-01-10 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
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* i386-tbl.h: Re-generate.
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2018-01-10 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
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vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
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vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
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vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
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vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
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Disp8MemShift of AVX512VL forms.
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* i386-tbl.h: Re-generate.
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2018-01-09 Jim Wilson <jimw@sifive.com>
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* riscv-dis.c (maybe_print_address): If base_reg is zero,
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then the hi_addr value is zero.
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2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
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* arm-dis.c (arm_opcodes): Add csdb.
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(thumb32_opcodes): Add csdb.
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2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/22681
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* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
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Remove AVX512 vmovd with 64-bit operands.
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* i386-tbl.h: Regenerated.
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2018-01-05 Jim Wilson <jimw@sifive.com>
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* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
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jalr.
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2018-01-03 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2018-01-02 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
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and OPERAND_TYPE_REGZMM entries.
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For older changes see ChangeLog-2017
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Copyright (C) 2018 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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