325 lines
8.4 KiB
C
325 lines
8.4 KiB
C
/* TIc80 Simulator.
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Copyright (C) 1997 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* TI C80 control registers */
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typedef enum {
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EPC_CR,
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EIP_CR,
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CONFIG_CR,
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INTPEN_CR,
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IE_CR,
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FPST_CR,
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PPERROR_CR,
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PKTREQ_CR,
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TCOUNT_CR,
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TSCALE_CR,
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FLTOP_CR,
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FLTADR_CR,
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FLTTAG_CR,
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FLTDLT_CR,
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FLTDTH_CR,
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FLT005_CR,
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FLT006_CR,
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FLT007_CR,
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FLT008_CR,
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FLT009_CR,
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FLT010_CR,
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FLT011_CR,
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FLT012_CR,
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FLT013_CR,
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FLT014_CR,
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FLT015_CR,
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SYSSTK_CR,
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SYSTMP_CR,
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MPC_CR,
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MIP_CR,
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ECOMCNTL_CR,
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ANASTAT_CR,
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BRK1_CR,
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BRK2_CR,
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ITAG0_CR,
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ITAG1_CR,
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ITAG2_CR,
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ITAG3_CR,
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ITAG4_CR,
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ITAG5_CR,
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ITAG6_CR,
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ITAG7_CR,
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ITAG8_CR,
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ITAG9_CR,
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ITAG10_CR,
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ITAG11_CR,
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ITAG12_CR,
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ITAG13_CR,
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ITAG14_CR,
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ITAG15_CR,
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ILRU_CR,
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DTAG0_CR,
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DTAG1_CR,
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DTAG2_CR,
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DTAG3_CR,
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DTAG4_CR,
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DTAG5_CR,
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DTAG6_CR,
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DTAG7_CR,
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DTAG8_CR,
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DTAG9_CR,
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DTAG10_CR,
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DTAG11_CR,
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DTAG12_CR,
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DTAG13_CR,
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DTAG14_CR,
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DTAG15_CR,
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DLRU_CR,
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IN0P_CR,
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IN1P_CR,
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OUTP_CR,
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SCRATCH_CR,
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nr_tic80_control_regs,
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} tic80_control_regs;
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/* extern int tic80_cr2index (tic80_control_regs reg); */
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/* Map an instruction CR index onto the corresponding internal cr enum
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or SCRATCH_CR if the index is invalid */
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extern tic80_control_regs tic80_index2cr (int index);
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/* TIc80 interrupt register bits */
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enum {
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IE_CR_PE = BIT32(31),
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IE_CR_X4 = BIT32(30),
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IE_CR_X3 = BIT32(29),
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IE_CR_BP = BIT32(28),
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IE_CR_PB = BIT32(27),
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IE_CR_PC = BIT32(26),
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IE_CR_MI = BIT32(25),
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/**/
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IE_CR_P3 = BIT32(19),
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IE_CR_P2 = BIT32(18),
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IE_CR_P1 = BIT32(17),
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IE_CR_P0 = BIT32(16),
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IE_CR_IO = BIT32(15),
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IE_CR_MF = BIT32(14),
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/**/
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IE_CR_X2 = BIT32(12),
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IE_CR_X1 = BIT32(11),
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IE_CR_TI = BIT32(10),
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IE_CR_F1 = BIT32(9),
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IE_CR_F0 = BIT32(8),
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IE_CR_FX = BIT32(7),
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IE_CR_FU = BIT32(6),
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IE_CR_FO = BIT32(5),
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/**/
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IE_CR_FZ = BIT32(3),
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IE_CR_FI = BIT32(2),
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/**/
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IE_CR_IE = BIT32(0),
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};
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struct _sim_cpu {
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unsigned32 reg[32];
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unsigned64 acc[4];
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unsigned32 cr[nr_tic80_control_regs];
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int is_user_mode; /* hidden mode latch */
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sim_cia cia;
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sim_cpu_base base;
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};
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#define CPU_CIA(CPU) ((CPU)->cia)
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#define GPR(N) ((CPU)->reg[N])
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#define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL))
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#define ACC(N) ((CPU)->acc[N])
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#define CR(N) ((CPU)->cr[tic80_index2cr ((N))])
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#if defined(WITH_TRACE)
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extern char *tic80_trace_alu3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
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extern char *tic80_trace_alu2 PARAMS ((int, unsigned32, unsigned32));
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extern char *tic80_trace_shift PARAMS ((int, unsigned32, unsigned32, int, int, int, int, int));
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extern void tic80_trace_fpu3 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu, sim_fpu, sim_fpu));
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extern void tic80_trace_fpu2 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu, sim_fpu));
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extern void tic80_trace_fpu1 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu));
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extern void tic80_trace_fpu2i PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, unsigned32, sim_fpu, sim_fpu));
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extern char *tic80_trace_nop PARAMS ((int));
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extern char *tic80_trace_sink1 PARAMS ((int, unsigned32));
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extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32));
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extern char *tic80_trace_sink3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
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extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32));
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extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32));
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extern void tic80_trace_ldst PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, int, int, int, unsigned32, unsigned32, unsigned32));
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#define TRACE_ALU3(indx, result, input1, input2) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "alu", \
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tic80_trace_alu3 (indx, result, input1, input2)); \
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} \
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} while (0)
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#define TRACE_ALU2(indx, result, input) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "alu", \
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tic80_trace_alu2 (indx, result, input)); \
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} \
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} while (0)
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#define TRACE_SHIFT(indx, result, input, i, n, merge, endmask, rotate) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "shift", \
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tic80_trace_shift (indx, result, input, i, n, \
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merge, endmask, rotate)); \
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} \
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} while (0)
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#define TRACE_FPU3(result, input1, input2) \
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do { \
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if (TRACE_FPU_P (CPU)) { \
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tic80_trace_fpu3 (SD, CPU, cia, MY_INDEX, \
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result, input1, input2); \
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} \
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} while (0)
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#define TRACE_FPU2(result, input) \
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do { \
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if (TRACE_FPU_P (CPU)) { \
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tic80_trace_fpu2 (SD, CPU, cia, MY_INDEX, \
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result, input); \
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} \
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} while (0)
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#define TRACE_FPU1(result) \
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do { \
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if (TRACE_FPU_P (CPU)) { \
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tic80_trace_fpu1 (SD, CPU, cia, MY_INDEX, \
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result); \
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} \
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} while (0)
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#define TRACE_FPU2I(result, input1, input2) \
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do { \
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if (TRACE_FPU_P (CPU)) { \
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tic80_trace_fpu2i (SD, CPU, cia, MY_INDEX, \
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result, input1, input2); \
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} \
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} while (0)
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#define TRACE_NOP(indx) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "nop", \
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tic80_trace_nop (indx)); \
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} \
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} while (0)
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#define TRACE_SINK1(indx, input) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "nop", \
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tic80_trace_sink1 (indx, input)); \
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} \
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} while (0)
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#define TRACE_SINK2(indx, input1, input2) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "nop", \
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tic80_trace_sink2 (indx, input1, input2)); \
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} \
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} while (0)
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#define TRACE_SINK3(indx, input1, input2, input3) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "nop", \
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tic80_trace_sink3 (indx, input1, input2, input3)); \
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} \
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} while (0)
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#define TRACE_COND_BR(indx, jump_p, cond, target) \
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do { \
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if (TRACE_BRANCH_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "branch", \
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tic80_trace_cond_br (indx, jump_p, cond, target)); \
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} \
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} while (0)
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#define TRACE_UCOND_BR(indx, target) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
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itable[indx].line_nr, "branch", \
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tic80_trace_ucond_br (indx, target)); \
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} \
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} while (0)
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#define TRACE_LD(result, m, s, addr1, addr2) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \
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0, m, s, result, addr1, addr2); \
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} \
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} while (0)
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#define TRACE_ST(value, m, s, addr1, addr2) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \
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1, m, s, value, addr1, addr2); \
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} \
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} while (0)
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#else
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#define TRACE_ALU3(indx, result, input1, input2)
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#define TRACE_ALU2(indx, result, input)
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#define TRACE_FPU3(result, input1, input2)
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#define TRACE_FPU2(result, input)
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#define TRACE_FPU1(result)
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#define TRACE_FPU2I(result, input1, input2)
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#define TRACE_NOP(indx)
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#define TRACE_SINK1(indx, input)
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#define TRACE_SINK2(indx, input1, input2)
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#define TRACE_SINK3(indx, input1, input2, input3)
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#define TRACE_COND_BR(indx, jump_p, cond, target)
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#define TRACE_UCOND_BR(indx, target)
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#define TRACE_LD(m, s, result, addr1, addr2)
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#define TRACE_ST(m, s, value, addr1, addr2)
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#endif
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