238 lines
6.6 KiB
C
238 lines
6.6 KiB
C
/* FRV simulator memory option handling.
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Copyright (C) 1999, 2000, 2007, 2008, 2009, 2010
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Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#define WANT_CPU frvbf
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#define WANT_CPU_FRVBF
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#include "sim-main.h"
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#include "sim-assert.h"
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#include "sim-options.h"
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#ifdef HAVE_STRING_H
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#include <string.h>
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#else
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#ifdef HAVE_STRINGS_H
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#include <strings.h>
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#endif
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#endif
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#ifdef HAVE_STDLIB_H
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#include <stdlib.h>
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#endif
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/* FRV specific command line options. */
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enum {
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OPTION_FRV_DATA_CACHE = OPTION_START,
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OPTION_FRV_INSN_CACHE,
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OPTION_FRV_PROFILE_CACHE,
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OPTION_FRV_PROFILE_PARALLEL,
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OPTION_FRV_TIMER,
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OPTION_FRV_MEMORY_LATENCY
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};
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static DECLARE_OPTION_HANDLER (frv_option_handler);
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const OPTION frv_options[] =
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{
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{ {"profile", optional_argument, NULL, 'p'},
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'p', "on|off", "Perform profiling",
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frv_option_handler },
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{ {"data-cache", optional_argument, NULL, OPTION_FRV_DATA_CACHE },
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'\0', "WAYS[,SETS[,LINESIZE]]", "Enable data cache",
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frv_option_handler },
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{ {"insn-cache", optional_argument, NULL, OPTION_FRV_INSN_CACHE },
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'\0', "WAYS[,SETS[,LINESIZE]]", "Enable instruction cache",
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frv_option_handler },
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{ {"profile-cache", optional_argument, NULL, OPTION_FRV_PROFILE_CACHE },
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'\0', "on|off", "Profile caches",
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frv_option_handler },
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{ {"profile-parallel", optional_argument, NULL, OPTION_FRV_PROFILE_PARALLEL },
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'\0', "on|off", "Profile parallelism",
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frv_option_handler },
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{ {"timer", required_argument, NULL, OPTION_FRV_TIMER },
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'\0', "CYCLES,INTERRUPT", "Set Interrupt Timer",
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frv_option_handler },
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{ {"memory-latency", required_argument, NULL, OPTION_FRV_MEMORY_LATENCY },
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'\0', "CYCLES", "Set Latency of memory",
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frv_option_handler },
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{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
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};
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static char *
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parse_size (char *chp, address_word *nr_bytes)
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{
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/* <nr_bytes> */
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*nr_bytes = strtoul (chp, &chp, 0);
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return chp;
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}
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static address_word
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check_pow2 (address_word value, char *argname, char *optname, SIM_DESC sd)
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{
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if ((value & (value - 1)) != 0)
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{
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sim_io_eprintf (sd, "%s argument to %s must be a power of 2\n",
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argname, optname);
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return 0; /* will enable default value. */
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}
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return value;
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}
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static void
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parse_cache_option (SIM_DESC sd, char *arg, char *cache_name, int is_data_cache)
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{
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int i;
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address_word ways = 0, sets = 0, linesize = 0;
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if (arg != NULL)
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{
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char *chp = arg;
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/* parse the arguments */
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chp = parse_size (chp, &ways);
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ways = check_pow2 (ways, "WAYS", cache_name, sd);
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if (*chp == ',')
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{
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chp = parse_size (chp + 1, &sets);
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sets = check_pow2 (sets, "SETS", cache_name, sd);
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if (*chp == ',')
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{
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chp = parse_size (chp + 1, &linesize);
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linesize = check_pow2 (linesize, "LINESIZE", cache_name, sd);
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}
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}
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}
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, i);
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FRV_CACHE *cache = is_data_cache ? CPU_DATA_CACHE (current_cpu)
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: CPU_INSN_CACHE (current_cpu);
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cache->ways = ways;
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cache->sets = sets;
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cache->line_size = linesize;
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frv_cache_init (current_cpu, cache);
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}
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}
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static SIM_RC
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frv_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
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char *arg, int is_command)
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{
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switch (opt)
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{
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case 'p' :
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if (! WITH_PROFILE)
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sim_io_eprintf (sd, "Profiling not compiled in, `-p' ignored\n");
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else
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{
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unsigned mask = PROFILE_USEFUL_MASK;
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if (WITH_PROFILE_CACHE_P)
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mask |= (1 << PROFILE_CACHE_IDX);
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if (WITH_PROFILE_PARALLEL_P)
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mask |= (1 << PROFILE_PARALLEL_IDX);
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return set_profile_option_mask (sd, "profile", mask, arg);
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}
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break;
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case OPTION_FRV_DATA_CACHE:
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parse_cache_option (sd, arg, "data_cache", 1/*is_data_cache*/);
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return SIM_RC_OK;
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case OPTION_FRV_INSN_CACHE:
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parse_cache_option (sd, arg, "insn_cache", 0/*is_data_cache*/);
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return SIM_RC_OK;
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case OPTION_FRV_PROFILE_CACHE:
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if (WITH_PROFILE_CACHE_P)
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return sim_profile_set_option (sd, "-cache", PROFILE_CACHE_IDX, arg);
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else
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sim_io_eprintf (sd, "Cache profiling not compiled in, `--profile-cache' ignored\n");
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break;
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case OPTION_FRV_PROFILE_PARALLEL:
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if (WITH_PROFILE_PARALLEL_P)
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{
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unsigned mask
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= (1 << PROFILE_MODEL_IDX) | (1 << PROFILE_PARALLEL_IDX);
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return set_profile_option_mask (sd, "-parallel", mask, arg);
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}
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else
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sim_io_eprintf (sd, "Parallel profiling not compiled in, `--profile-parallel' ignored\n");
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break;
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case OPTION_FRV_TIMER:
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{
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char *chp = arg;
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address_word cycles, interrupt;
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chp = parse_size (chp, &cycles);
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if (chp == arg)
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{
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sim_io_eprintf (sd, "Cycle count required for --timer\n");
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return SIM_RC_FAIL;
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}
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if (*chp != ',')
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{
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sim_io_eprintf (sd, "Interrupt number required for --timer\n");
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return SIM_RC_FAIL;
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}
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chp = parse_size (chp + 1, &interrupt);
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if (interrupt < 1 || interrupt > 15)
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{
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sim_io_eprintf (sd, "Interrupt number for --timer must be greater than 0 and less that 16\n");
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return SIM_RC_FAIL;
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}
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frv_interrupt_state.timer.enabled = 1;
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frv_interrupt_state.timer.value = cycles;
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frv_interrupt_state.timer.current = 0;
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frv_interrupt_state.timer.interrupt =
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FRV_INTERRUPT_LEVEL_1 + interrupt - 1;
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}
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return SIM_RC_OK;
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case OPTION_FRV_MEMORY_LATENCY:
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{
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int i;
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char *chp = arg;
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address_word cycles;
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chp = parse_size (chp, &cycles);
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if (chp == arg)
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{
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sim_io_eprintf (sd, "Cycle count required for --memory-latency\n");
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return SIM_RC_FAIL;
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}
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, i);
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FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu);
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FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu);
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insn_cache->memory_latency = cycles;
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data_cache->memory_latency = cycles;
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}
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}
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return SIM_RC_OK;
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default:
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sim_io_eprintf (sd, "Unknown FRV option %d\n", opt);
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return SIM_RC_FAIL;
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}
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return SIM_RC_FAIL;
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}
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