389 lines
13 KiB
C
389 lines
13 KiB
C
/* GNU/Linux on ARM target support.
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Copyright 1999, 2000, 2001, 2002, 2003, 2005 Free Software
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Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include "defs.h"
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#include "target.h"
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#include "value.h"
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#include "gdbtypes.h"
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#include "floatformat.h"
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#include "gdbcore.h"
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#include "frame.h"
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#include "regcache.h"
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#include "doublest.h"
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#include "solib-svr4.h"
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#include "osabi.h"
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#include "arm-tdep.h"
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#include "glibc-tdep.h"
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/* Under ARM GNU/Linux the traditional way of performing a breakpoint
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is to execute a particular software interrupt, rather than use a
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particular undefined instruction to provoke a trap. Upon exection
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of the software interrupt the kernel stops the inferior with a
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SIGTRAP, and wakes the debugger. */
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static const char arm_linux_arm_le_breakpoint[] = { 0x01, 0x00, 0x9f, 0xef };
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static const char arm_linux_arm_be_breakpoint[] = { 0xef, 0x9f, 0x00, 0x01 };
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/* However, the EABI syscall interface (new in Nov. 2005) does not look at
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the operand of the swi if old-ABI compatibility is disabled. Therefore,
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use an undefined instruction instead. This is supported as of kernel
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version 2.5.70 (May 2003), so should be a safe assumption for EABI
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binaries. */
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static const char eabi_linux_arm_le_breakpoint[] = { 0xf0, 0x01, 0xf0, 0xe7 };
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static const char eabi_linux_arm_be_breakpoint[] = { 0xe7, 0xf0, 0x01, 0xf0 };
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/* All the kernels which support Thumb support using a specific undefined
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instruction for the Thumb breakpoint. */
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static const char arm_linux_thumb_be_breakpoint[] = {0xde, 0x01};
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static const char arm_linux_thumb_le_breakpoint[] = {0x01, 0xde};
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/* Description of the longjmp buffer. */
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#define ARM_LINUX_JB_ELEMENT_SIZE INT_REGISTER_SIZE
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#define ARM_LINUX_JB_PC 21
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/* Extract from an array REGBUF containing the (raw) register state
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a function return value of type TYPE, and copy that, in virtual format,
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into VALBUF. */
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/* FIXME rearnsha/2002-02-23: This function shouldn't be necessary.
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The ARM generic one should be able to handle the model used by
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linux and the low-level formatting of the registers should be
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hidden behind the regcache abstraction. */
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static void
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arm_linux_extract_return_value (struct type *type,
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char regbuf[],
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char *valbuf)
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{
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/* ScottB: This needs to be looked at to handle the different
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floating point emulators on ARM GNU/Linux. Right now the code
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assumes that fetch inferior registers does the right thing for
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GDB. I suspect this won't handle NWFPE registers correctly, nor
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will the default ARM version (arm_extract_return_value()). */
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int regnum = ((TYPE_CODE_FLT == TYPE_CODE (type))
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? ARM_F0_REGNUM : ARM_A1_REGNUM);
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memcpy (valbuf, ®buf[DEPRECATED_REGISTER_BYTE (regnum)], TYPE_LENGTH (type));
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}
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/*
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Dynamic Linking on ARM GNU/Linux
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--------------------------------
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Note: PLT = procedure linkage table
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GOT = global offset table
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As much as possible, ELF dynamic linking defers the resolution of
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jump/call addresses until the last minute. The technique used is
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inspired by the i386 ELF design, and is based on the following
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constraints.
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1) The calling technique should not force a change in the assembly
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code produced for apps; it MAY cause changes in the way assembly
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code is produced for position independent code (i.e. shared
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libraries).
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2) The technique must be such that all executable areas must not be
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modified; and any modified areas must not be executed.
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To do this, there are three steps involved in a typical jump:
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1) in the code
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2) through the PLT
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3) using a pointer from the GOT
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When the executable or library is first loaded, each GOT entry is
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initialized to point to the code which implements dynamic name
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resolution and code finding. This is normally a function in the
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program interpreter (on ARM GNU/Linux this is usually
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ld-linux.so.2, but it does not have to be). On the first
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invocation, the function is located and the GOT entry is replaced
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with the real function address. Subsequent calls go through steps
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1, 2 and 3 and end up calling the real code.
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1) In the code:
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b function_call
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bl function_call
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This is typical ARM code using the 26 bit relative branch or branch
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and link instructions. The target of the instruction
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(function_call is usually the address of the function to be called.
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In position independent code, the target of the instruction is
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actually an entry in the PLT when calling functions in a shared
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library. Note that this call is identical to a normal function
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call, only the target differs.
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2) In the PLT:
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The PLT is a synthetic area, created by the linker. It exists in
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both executables and libraries. It is an array of stubs, one per
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imported function call. It looks like this:
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PLT[0]:
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str lr, [sp, #-4]! @push the return address (lr)
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ldr lr, [pc, #16] @load from 6 words ahead
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add lr, pc, lr @form an address for GOT[0]
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ldr pc, [lr, #8]! @jump to the contents of that addr
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The return address (lr) is pushed on the stack and used for
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calculations. The load on the second line loads the lr with
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&GOT[3] - . - 20. The addition on the third leaves:
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lr = (&GOT[3] - . - 20) + (. + 8)
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lr = (&GOT[3] - 12)
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lr = &GOT[0]
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On the fourth line, the pc and lr are both updated, so that:
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pc = GOT[2]
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lr = &GOT[0] + 8
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= &GOT[2]
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NOTE: PLT[0] borrows an offset .word from PLT[1]. This is a little
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"tight", but allows us to keep all the PLT entries the same size.
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PLT[n+1]:
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ldr ip, [pc, #4] @load offset from gotoff
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add ip, pc, ip @add the offset to the pc
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ldr pc, [ip] @jump to that address
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gotoff: .word GOT[n+3] - .
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The load on the first line, gets an offset from the fourth word of
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the PLT entry. The add on the second line makes ip = &GOT[n+3],
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which contains either a pointer to PLT[0] (the fixup trampoline) or
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a pointer to the actual code.
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3) In the GOT:
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The GOT contains helper pointers for both code (PLT) fixups and
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data fixups. The first 3 entries of the GOT are special. The next
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M entries (where M is the number of entries in the PLT) belong to
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the PLT fixups. The next D (all remaining) entries belong to
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various data fixups. The actual size of the GOT is 3 + M + D.
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The GOT is also a synthetic area, created by the linker. It exists
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in both executables and libraries. When the GOT is first
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initialized , all the GOT entries relating to PLT fixups are
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pointing to code back at PLT[0].
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The special entries in the GOT are:
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GOT[0] = linked list pointer used by the dynamic loader
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GOT[1] = pointer to the reloc table for this module
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GOT[2] = pointer to the fixup/resolver code
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The first invocation of function call comes through and uses the
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fixup/resolver code. On the entry to the fixup/resolver code:
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ip = &GOT[n+3]
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lr = &GOT[2]
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stack[0] = return address (lr) of the function call
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[r0, r1, r2, r3] are still the arguments to the function call
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This is enough information for the fixup/resolver code to work
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with. Before the fixup/resolver code returns, it actually calls
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the requested function and repairs &GOT[n+3]. */
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/* Fetch, and possibly build, an appropriate link_map_offsets structure
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for ARM linux targets using the struct offsets defined in <link.h>.
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Note, however, that link.h is not actually referred to in this file.
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Instead, the relevant structs offsets were obtained from examining
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link.h. (We can't refer to link.h from this file because the host
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system won't necessarily have it, or if it does, the structs which
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it defines will refer to the host system, not the target). */
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static struct link_map_offsets *
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arm_linux_svr4_fetch_link_map_offsets (void)
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{
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static struct link_map_offsets lmo;
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static struct link_map_offsets *lmp = 0;
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if (lmp == 0)
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{
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lmp = &lmo;
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lmo.r_debug_size = 8; /* Actual size is 20, but this is all we
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need. */
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lmo.r_map_offset = 4;
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lmo.r_map_size = 4;
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lmo.link_map_size = 20; /* Actual size is 552, but this is all we
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need. */
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lmo.l_addr_offset = 0;
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lmo.l_addr_size = 4;
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lmo.l_name_offset = 4;
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lmo.l_name_size = 4;
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lmo.l_next_offset = 12;
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lmo.l_next_size = 4;
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lmo.l_prev_offset = 16;
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lmo.l_prev_size = 4;
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}
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return lmp;
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}
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/* The constants below were determined by examining the following files
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in the linux kernel sources:
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arch/arm/kernel/signal.c
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- see SWI_SYS_SIGRETURN and SWI_SYS_RT_SIGRETURN
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include/asm-arm/unistd.h
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- see __NR_sigreturn, __NR_rt_sigreturn, and __NR_SYSCALL_BASE */
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#define ARM_LINUX_SIGRETURN_INSTR 0xef900077
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#define ARM_LINUX_RT_SIGRETURN_INSTR 0xef9000ad
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/* arm_linux_in_sigtramp determines if PC points at one of the
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instructions which cause control to return to the Linux kernel upon
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return from a signal handler. FUNC_NAME is unused. */
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int
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arm_linux_in_sigtramp (CORE_ADDR pc, char *func_name)
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{
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unsigned long inst;
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inst = read_memory_integer (pc, 4);
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return (inst == ARM_LINUX_SIGRETURN_INSTR
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|| inst == ARM_LINUX_RT_SIGRETURN_INSTR);
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}
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/* arm_linux_sigcontext_register_address returns the address in the
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sigcontext of register REGNO given a stack pointer value SP and
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program counter value PC. The value 0 is returned if PC is not
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pointing at one of the signal return instructions or if REGNO is
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not saved in the sigcontext struct. */
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CORE_ADDR
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arm_linux_sigcontext_register_address (CORE_ADDR sp, CORE_ADDR pc, int regno)
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{
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unsigned long inst;
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CORE_ADDR reg_addr = 0;
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inst = read_memory_integer (pc, 4);
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if (inst == ARM_LINUX_SIGRETURN_INSTR
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|| inst == ARM_LINUX_RT_SIGRETURN_INSTR)
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{
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CORE_ADDR sigcontext_addr;
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/* The sigcontext structure is at different places for the two
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signal return instructions. For ARM_LINUX_SIGRETURN_INSTR,
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it starts at the SP value. For ARM_LINUX_RT_SIGRETURN_INSTR,
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it is at SP+8. For the latter instruction, it may also be
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the case that the address of this structure may be determined
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by reading the 4 bytes at SP, but I'm not convinced this is
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reliable.
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In any event, these magic constants (0 and 8) may be
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determined by examining struct sigframe and struct
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rt_sigframe in arch/arm/kernel/signal.c in the Linux kernel
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sources. */
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if (inst == ARM_LINUX_RT_SIGRETURN_INSTR)
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sigcontext_addr = sp + 8;
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else /* inst == ARM_LINUX_SIGRETURN_INSTR */
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sigcontext_addr = sp + 0;
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/* The layout of the sigcontext structure for ARM GNU/Linux is
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in include/asm-arm/sigcontext.h in the Linux kernel sources.
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There are three 4-byte fields which precede the saved r0
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field. (This accounts for the 12 in the code below.) The
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sixteen registers (4 bytes per field) follow in order. The
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PSR value follows the sixteen registers which accounts for
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the constant 19 below. */
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if (0 <= regno && regno <= ARM_PC_REGNUM)
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reg_addr = sigcontext_addr + 12 + (4 * regno);
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else if (regno == ARM_PS_REGNUM)
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reg_addr = sigcontext_addr + 19 * 4;
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}
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return reg_addr;
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}
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static void
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arm_linux_init_abi (struct gdbarch_info info,
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struct gdbarch *gdbarch)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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tdep->lowest_pc = 0x8000;
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if (info.byte_order == BFD_ENDIAN_BIG)
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{
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if (tdep->arm_abi == ARM_ABI_AAPCS)
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tdep->arm_breakpoint = eabi_linux_arm_be_breakpoint;
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else
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tdep->arm_breakpoint = arm_linux_arm_be_breakpoint;
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tdep->thumb_breakpoint = arm_linux_thumb_be_breakpoint;
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}
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else
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{
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if (tdep->arm_abi == ARM_ABI_AAPCS)
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tdep->arm_breakpoint = eabi_linux_arm_le_breakpoint;
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else
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tdep->arm_breakpoint = arm_linux_arm_le_breakpoint;
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tdep->thumb_breakpoint = arm_linux_thumb_le_breakpoint;
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}
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tdep->arm_breakpoint_size = sizeof (arm_linux_arm_le_breakpoint);
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tdep->thumb_breakpoint_size = sizeof (arm_linux_thumb_le_breakpoint);
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if (tdep->fp_model == ARM_FLOAT_AUTO)
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tdep->fp_model = ARM_FLOAT_FPA;
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tdep->jb_pc = ARM_LINUX_JB_PC;
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tdep->jb_elt_size = ARM_LINUX_JB_ELEMENT_SIZE;
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set_solib_svr4_fetch_link_map_offsets
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(gdbarch, arm_linux_svr4_fetch_link_map_offsets);
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/* The following override shouldn't be needed. */
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set_gdbarch_deprecated_extract_return_value (gdbarch, arm_linux_extract_return_value);
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/* Shared library handling. */
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set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
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set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
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/* Enable TLS support. */
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set_gdbarch_fetch_tls_load_module_address (gdbarch,
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svr4_fetch_objfile_link_map);
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}
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void
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_initialize_arm_linux_tdep (void)
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{
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gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_LINUX,
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arm_linux_init_abi);
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}
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