563 lines
18 KiB
C
563 lines
18 KiB
C
/* Semantic operand instances for m32r.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "sysdep.h"
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#include "ansidecl.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "m32r-desc.h"
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#include "m32r-opc.h"
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/* Operand references. */
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#define INPUT CGEN_OPINST_INPUT
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#define OUTPUT CGEN_OPINST_OUTPUT
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#define END CGEN_OPINST_END
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#define COND_REF CGEN_OPINST_COND_REF
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#define OP_ENT(op) CONCAT2 (M32R_OPERAND_,op)
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static const CGEN_OPINST fmt_empty_ops[] = {
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{ END }
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};
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static const CGEN_OPINST fmt_add_ops[] = {
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{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_add3_ops[] = {
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{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_and3_ops[] = {
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_or3_ops[] = {
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_addi_ops[] = {
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{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_addv_ops[] = {
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{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_addv3_ops[] = {
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{ INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_addx_ops[] = {
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{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_bc8_ops[] = {
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{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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{ INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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{ END }
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};
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static const CGEN_OPINST fmt_bc24_ops[] = {
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{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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{ INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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{ END }
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};
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static const CGEN_OPINST fmt_beq_ops[] = {
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{ INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
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{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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{ END }
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};
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static const CGEN_OPINST fmt_beqz_ops[] = {
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{ INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
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{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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{ END }
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};
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static const CGEN_OPINST fmt_bl8_ops[] = {
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{ INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
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{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_bl24_ops[] = {
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{ INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
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{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_bra8_ops[] = {
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{ INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_bra24_ops[] = {
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{ INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_cmp_ops[] = {
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{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_cmpi_ops[] = {
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{ INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
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{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_div_ops[] = {
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{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
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{ END }
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};
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static const CGEN_OPINST fmt_jl_ops[] = {
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{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_jmp_ops[] = {
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ld_ops[] = {
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{ INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ld_d_ops[] = {
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{ INPUT, "h_memory_add__VM_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
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{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ldb_ops[] = {
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{ INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ldb_d_ops[] = {
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{ INPUT, "h_memory_add__VM_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
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{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ldh_ops[] = {
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{ INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ldh_d_ops[] = {
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{ INPUT, "h_memory_add__VM_sr_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
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{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ld_plus_ops[] = {
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{ INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ld24_ops[] = {
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{ INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ldi8_ops[] = {
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{ INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_ldi16_ops[] = {
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{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_lock_ops[] = {
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{ INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_machi_ops[] = {
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{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_mulhi_ops[] = {
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{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_mv_ops[] = {
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_mvfachi_ops[] = {
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{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_mvfc_ops[] = {
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{ INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_mvtachi_ops[] = {
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{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_mvtc_ops[] = {
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_nop_ops[] = {
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{ END }
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};
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static const CGEN_OPINST fmt_rac_ops[] = {
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{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_rte_ops[] = {
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{ INPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
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{ INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
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{ INPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
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{ INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
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{ OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
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{ OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
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{ OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_seth_ops[] = {
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{ INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_sll3_ops[] = {
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{ INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
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{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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{ END }
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};
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static const CGEN_OPINST fmt_slli_ops[] = {
|
|
{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|
{ INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
|
|
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|
{ END }
|
|
};
|
|
|
|
static const CGEN_OPINST fmt_st_ops[] = {
|
|
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
|
|
{ END }
|
|
};
|
|
|
|
static const CGEN_OPINST fmt_st_d_ops[] = {
|
|
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
|
|
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
|
|
{ END }
|
|
};
|
|
|
|
static const CGEN_OPINST fmt_stb_ops[] = {
|
|
{ INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
|
|
{ END }
|
|
};
|
|
|
|
static const CGEN_OPINST fmt_stb_d_ops[] = {
|
|
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
|
|
{ INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
|
|
{ END }
|
|
};
|
|
|
|
static const CGEN_OPINST fmt_sth_ops[] = {
|
|
{ INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
|
|
{ END }
|
|
};
|
|
|
|
static const CGEN_OPINST fmt_sth_d_ops[] = {
|
|
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
|
|
{ INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
|
|
{ END }
|
|
};
|
|
|
|
static const CGEN_OPINST fmt_st_plus_ops[] = {
|
|
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "h_memory_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|
{ END }
|
|
};
|
|
|
|
static const CGEN_OPINST fmt_trap_ops[] = {
|
|
{ INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
|
|
{ INPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
|
|
{ INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
|
|
{ OUTPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
|
|
{ OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
|
|
{ OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
|
|
{ END }
|
|
};
|
|
|
|
static const CGEN_OPINST fmt_unlock_ops[] = {
|
|
{ INPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
|
|
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF },
|
|
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
|
|
{ OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
|
|
{ END }
|
|
};
|
|
|
|
#undef INPUT
|
|
#undef OUTPUT
|
|
#undef END
|
|
#undef COND_REF
|
|
#undef OP_ENT
|
|
|
|
/* Operand instance lookup table. */
|
|
|
|
static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
|
|
0,
|
|
& fmt_add_ops[0],
|
|
& fmt_add3_ops[0],
|
|
& fmt_add_ops[0],
|
|
& fmt_and3_ops[0],
|
|
& fmt_add_ops[0],
|
|
& fmt_or3_ops[0],
|
|
& fmt_add_ops[0],
|
|
& fmt_and3_ops[0],
|
|
& fmt_addi_ops[0],
|
|
& fmt_addv_ops[0],
|
|
& fmt_addv3_ops[0],
|
|
& fmt_addx_ops[0],
|
|
& fmt_bc8_ops[0],
|
|
& fmt_bc24_ops[0],
|
|
& fmt_beq_ops[0],
|
|
& fmt_beqz_ops[0],
|
|
& fmt_beqz_ops[0],
|
|
& fmt_beqz_ops[0],
|
|
& fmt_beqz_ops[0],
|
|
& fmt_beqz_ops[0],
|
|
& fmt_beqz_ops[0],
|
|
& fmt_bl8_ops[0],
|
|
& fmt_bl24_ops[0],
|
|
& fmt_bc8_ops[0],
|
|
& fmt_bc24_ops[0],
|
|
& fmt_beq_ops[0],
|
|
& fmt_bra8_ops[0],
|
|
& fmt_bra24_ops[0],
|
|
& fmt_cmp_ops[0],
|
|
& fmt_cmpi_ops[0],
|
|
& fmt_cmp_ops[0],
|
|
& fmt_cmpi_ops[0],
|
|
& fmt_div_ops[0],
|
|
& fmt_div_ops[0],
|
|
& fmt_div_ops[0],
|
|
& fmt_div_ops[0],
|
|
& fmt_jl_ops[0],
|
|
& fmt_jmp_ops[0],
|
|
& fmt_ld_ops[0],
|
|
& fmt_ld_d_ops[0],
|
|
& fmt_ldb_ops[0],
|
|
& fmt_ldb_d_ops[0],
|
|
& fmt_ldh_ops[0],
|
|
& fmt_ldh_d_ops[0],
|
|
& fmt_ldb_ops[0],
|
|
& fmt_ldb_d_ops[0],
|
|
& fmt_ldh_ops[0],
|
|
& fmt_ldh_d_ops[0],
|
|
& fmt_ld_plus_ops[0],
|
|
& fmt_ld24_ops[0],
|
|
& fmt_ldi8_ops[0],
|
|
& fmt_ldi16_ops[0],
|
|
& fmt_lock_ops[0],
|
|
& fmt_machi_ops[0],
|
|
& fmt_machi_ops[0],
|
|
& fmt_machi_ops[0],
|
|
& fmt_machi_ops[0],
|
|
& fmt_add_ops[0],
|
|
& fmt_mulhi_ops[0],
|
|
& fmt_mulhi_ops[0],
|
|
& fmt_mulhi_ops[0],
|
|
& fmt_mulhi_ops[0],
|
|
& fmt_mv_ops[0],
|
|
& fmt_mvfachi_ops[0],
|
|
& fmt_mvfachi_ops[0],
|
|
& fmt_mvfachi_ops[0],
|
|
& fmt_mvfc_ops[0],
|
|
& fmt_mvtachi_ops[0],
|
|
& fmt_mvtachi_ops[0],
|
|
& fmt_mvtc_ops[0],
|
|
& fmt_mv_ops[0],
|
|
& fmt_nop_ops[0],
|
|
& fmt_mv_ops[0],
|
|
& fmt_rac_ops[0],
|
|
& fmt_rac_ops[0],
|
|
& fmt_rte_ops[0],
|
|
& fmt_seth_ops[0],
|
|
& fmt_add_ops[0],
|
|
& fmt_sll3_ops[0],
|
|
& fmt_slli_ops[0],
|
|
& fmt_add_ops[0],
|
|
& fmt_sll3_ops[0],
|
|
& fmt_slli_ops[0],
|
|
& fmt_add_ops[0],
|
|
& fmt_sll3_ops[0],
|
|
& fmt_slli_ops[0],
|
|
& fmt_st_ops[0],
|
|
& fmt_st_d_ops[0],
|
|
& fmt_stb_ops[0],
|
|
& fmt_stb_d_ops[0],
|
|
& fmt_sth_ops[0],
|
|
& fmt_sth_d_ops[0],
|
|
& fmt_st_plus_ops[0],
|
|
& fmt_st_plus_ops[0],
|
|
& fmt_add_ops[0],
|
|
& fmt_addv_ops[0],
|
|
& fmt_addx_ops[0],
|
|
& fmt_trap_ops[0],
|
|
& fmt_unlock_ops[0],
|
|
};
|
|
|
|
/* Function to call before using the operand instance table. */
|
|
|
|
void
|
|
m32r_cgen_init_opinst_table (cd)
|
|
CGEN_CPU_DESC cd;
|
|
{
|
|
int i;
|
|
const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0];
|
|
CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
|
|
for (i = 0; i < MAX_INSNS; ++i)
|
|
insns[i].opinst = oi[i];
|
|
}
|