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584 lines
16 KiB
C
584 lines
16 KiB
C
/* Blackfin Memory Management Unit (MMU) model.
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Copyright (C) 2010-2017 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "sim-options.h"
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#include "devices.h"
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#include "dv-bfin_mmu.h"
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#include "dv-bfin_cec.h"
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/* XXX: Should this really be two blocks of registers ? PRM describes
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these as two Content Addressable Memory (CAM) blocks. */
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struct bfin_mmu
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{
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bu32 base;
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/* Order after here is important -- matches hardware MMR layout. */
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bu32 sram_base_address;
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bu32 dmem_control, dcplb_fault_status, dcplb_fault_addr;
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char _dpad0[0x100 - 0x0 - (4 * 4)];
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bu32 dcplb_addr[16];
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char _dpad1[0x200 - 0x100 - (4 * 16)];
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bu32 dcplb_data[16];
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char _dpad2[0x300 - 0x200 - (4 * 16)];
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bu32 dtest_command;
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char _dpad3[0x400 - 0x300 - (4 * 1)];
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bu32 dtest_data[2];
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char _dpad4[0x1000 - 0x400 - (4 * 2)];
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bu32 idk; /* Filler MMR; hardware simply ignores. */
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bu32 imem_control, icplb_fault_status, icplb_fault_addr;
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char _ipad0[0x100 - 0x0 - (4 * 4)];
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bu32 icplb_addr[16];
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char _ipad1[0x200 - 0x100 - (4 * 16)];
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bu32 icplb_data[16];
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char _ipad2[0x300 - 0x200 - (4 * 16)];
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bu32 itest_command;
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char _ipad3[0x400 - 0x300 - (4 * 1)];
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bu32 itest_data[2];
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};
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#define mmr_base() offsetof(struct bfin_mmu, sram_base_address)
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#define mmr_offset(mmr) (offsetof(struct bfin_mmu, mmr) - mmr_base())
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#define mmr_idx(mmr) (mmr_offset (mmr) / 4)
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static const char * const mmr_names[BFIN_COREMMR_MMU_SIZE / 4] =
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{
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"SRAM_BASE_ADDRESS", "DMEM_CONTROL", "DCPLB_FAULT_STATUS", "DCPLB_FAULT_ADDR",
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[mmr_idx (dcplb_addr[0])] = "DCPLB_ADDR0",
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"DCPLB_ADDR1", "DCPLB_ADDR2", "DCPLB_ADDR3", "DCPLB_ADDR4", "DCPLB_ADDR5",
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"DCPLB_ADDR6", "DCPLB_ADDR7", "DCPLB_ADDR8", "DCPLB_ADDR9", "DCPLB_ADDR10",
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"DCPLB_ADDR11", "DCPLB_ADDR12", "DCPLB_ADDR13", "DCPLB_ADDR14", "DCPLB_ADDR15",
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[mmr_idx (dcplb_data[0])] = "DCPLB_DATA0",
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"DCPLB_DATA1", "DCPLB_DATA2", "DCPLB_DATA3", "DCPLB_DATA4", "DCPLB_DATA5",
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"DCPLB_DATA6", "DCPLB_DATA7", "DCPLB_DATA8", "DCPLB_DATA9", "DCPLB_DATA10",
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"DCPLB_DATA11", "DCPLB_DATA12", "DCPLB_DATA13", "DCPLB_DATA14", "DCPLB_DATA15",
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[mmr_idx (dtest_command)] = "DTEST_COMMAND",
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[mmr_idx (dtest_data[0])] = "DTEST_DATA0", "DTEST_DATA1",
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[mmr_idx (imem_control)] = "IMEM_CONTROL", "ICPLB_FAULT_STATUS", "ICPLB_FAULT_ADDR",
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[mmr_idx (icplb_addr[0])] = "ICPLB_ADDR0",
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"ICPLB_ADDR1", "ICPLB_ADDR2", "ICPLB_ADDR3", "ICPLB_ADDR4", "ICPLB_ADDR5",
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"ICPLB_ADDR6", "ICPLB_ADDR7", "ICPLB_ADDR8", "ICPLB_ADDR9", "ICPLB_ADDR10",
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"ICPLB_ADDR11", "ICPLB_ADDR12", "ICPLB_ADDR13", "ICPLB_ADDR14", "ICPLB_ADDR15",
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[mmr_idx (icplb_data[0])] = "ICPLB_DATA0",
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"ICPLB_DATA1", "ICPLB_DATA2", "ICPLB_DATA3", "ICPLB_DATA4", "ICPLB_DATA5",
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"ICPLB_DATA6", "ICPLB_DATA7", "ICPLB_DATA8", "ICPLB_DATA9", "ICPLB_DATA10",
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"ICPLB_DATA11", "ICPLB_DATA12", "ICPLB_DATA13", "ICPLB_DATA14", "ICPLB_DATA15",
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[mmr_idx (itest_command)] = "ITEST_COMMAND",
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[mmr_idx (itest_data[0])] = "ITEST_DATA0", "ITEST_DATA1",
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};
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#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
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static bool bfin_mmu_skip_cplbs = false;
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static unsigned
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bfin_mmu_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_mmu *mmu = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu32 *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
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return 0;
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value = dv_load_4 (source);
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mmr_off = addr - mmu->base;
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valuep = (void *)((unsigned long)mmu + mmr_base() + mmr_off);
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(dmem_control):
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case mmr_offset(imem_control):
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/* XXX: IMC/DMC bit should add/remove L1 cache regions ... */
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case mmr_offset(dtest_data[0]) ... mmr_offset(dtest_data[1]):
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case mmr_offset(itest_data[0]) ... mmr_offset(itest_data[1]):
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case mmr_offset(dcplb_addr[0]) ... mmr_offset(dcplb_addr[15]):
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case mmr_offset(dcplb_data[0]) ... mmr_offset(dcplb_data[15]):
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case mmr_offset(icplb_addr[0]) ... mmr_offset(icplb_addr[15]):
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case mmr_offset(icplb_data[0]) ... mmr_offset(icplb_data[15]):
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*valuep = value;
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break;
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case mmr_offset(sram_base_address):
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case mmr_offset(dcplb_fault_status):
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case mmr_offset(dcplb_fault_addr):
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case mmr_offset(idk):
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case mmr_offset(icplb_fault_status):
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case mmr_offset(icplb_fault_addr):
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/* Discard writes to these. */
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break;
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case mmr_offset(itest_command):
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/* XXX: Not supported atm. */
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if (value)
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hw_abort (me, "ITEST_COMMAND unimplemented");
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break;
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case mmr_offset(dtest_command):
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/* Access L1 memory indirectly. */
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*valuep = value;
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if (value)
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{
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bu32 addr = mmu->sram_base_address |
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((value >> (26 - 11)) & (1 << 11)) | /* addr bit 11 (Way0/Way1) */
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((value >> (24 - 21)) & (1 << 21)) | /* addr bit 21 (Data/Inst) */
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((value >> (23 - 15)) & (1 << 15)) | /* addr bit 15 (Data Bank) */
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((value >> (16 - 12)) & (3 << 12)) | /* addr bits 13:12 (Subbank) */
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(value & 0x47F8); /* addr bits 14 & 10:3 */
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if (!(value & TEST_DATA_ARRAY))
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hw_abort (me, "DTEST_COMMAND tag array unimplemented");
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if (value & 0xfa7cb801)
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hw_abort (me, "DTEST_COMMAND bits undefined");
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if (value & TEST_WRITE)
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sim_write (hw_system (me), addr, (void *)mmu->dtest_data, 8);
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else
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sim_read (hw_system (me), addr, (void *)mmu->dtest_data, 8);
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}
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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return 0;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_mmu_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_mmu *mmu = hw_data (me);
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bu32 mmr_off;
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bu32 *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
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return 0;
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mmr_off = addr - mmu->base;
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valuep = (void *)((unsigned long)mmu + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(dmem_control):
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case mmr_offset(imem_control):
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case mmr_offset(dtest_command):
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case mmr_offset(dtest_data[0]) ... mmr_offset(dtest_data[2]):
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case mmr_offset(itest_command):
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case mmr_offset(itest_data[0]) ... mmr_offset(itest_data[2]):
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/* XXX: should do something here. */
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case mmr_offset(dcplb_addr[0]) ... mmr_offset(dcplb_addr[15]):
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case mmr_offset(dcplb_data[0]) ... mmr_offset(dcplb_data[15]):
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case mmr_offset(icplb_addr[0]) ... mmr_offset(icplb_addr[15]):
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case mmr_offset(icplb_data[0]) ... mmr_offset(icplb_data[15]):
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case mmr_offset(sram_base_address):
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case mmr_offset(dcplb_fault_status):
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case mmr_offset(dcplb_fault_addr):
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case mmr_offset(idk):
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case mmr_offset(icplb_fault_status):
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case mmr_offset(icplb_fault_addr):
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dv_store_4 (dest, *valuep);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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return 0;
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}
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return nr_bytes;
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}
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static void
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attach_bfin_mmu_regs (struct hw *me, struct bfin_mmu *mmu)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_COREMMR_MMU_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_MMU_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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mmu->base = attach_address;
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}
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static void
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bfin_mmu_finish (struct hw *me)
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{
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struct bfin_mmu *mmu;
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mmu = HW_ZALLOC (me, struct bfin_mmu);
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set_hw_data (me, mmu);
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set_hw_io_read_buffer (me, bfin_mmu_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_mmu_io_write_buffer);
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attach_bfin_mmu_regs (me, mmu);
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/* Initialize the MMU. */
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mmu->sram_base_address = 0xff800000 - 0;
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/*(4 * 1024 * 1024 * CPU_INDEX (hw_system_cpu (me)));*/
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mmu->dmem_control = 0x00000001;
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mmu->imem_control = 0x00000001;
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}
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const struct hw_descriptor dv_bfin_mmu_descriptor[] =
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{
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{"bfin_mmu", bfin_mmu_finish,},
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{NULL, NULL},
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};
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/* Device option parsing. */
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static DECLARE_OPTION_HANDLER (bfin_mmu_option_handler);
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enum {
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OPTION_MMU_SKIP_TABLES = OPTION_START,
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};
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const OPTION bfin_mmu_options[] =
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{
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{ {"mmu-skip-cplbs", no_argument, NULL, OPTION_MMU_SKIP_TABLES },
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'\0', NULL, "Skip parsing of CPLB tables (big speed increase)",
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bfin_mmu_option_handler, NULL },
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{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
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};
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static SIM_RC
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bfin_mmu_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
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char *arg, int is_command)
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{
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switch (opt)
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{
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case OPTION_MMU_SKIP_TABLES:
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bfin_mmu_skip_cplbs = true;
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return SIM_RC_OK;
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default:
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sim_io_eprintf (sd, "Unknown Blackfin MMU option %d\n", opt);
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return SIM_RC_FAIL;
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}
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}
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#define MMU_STATE(cpu) DV_STATE_CACHED (cpu, mmu)
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static void
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_mmu_log_ifault (SIM_CPU *cpu, struct bfin_mmu *mmu, bu32 pc, bool supv)
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{
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mmu->icplb_fault_addr = pc;
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mmu->icplb_fault_status = supv << 17;
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}
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void
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mmu_log_ifault (SIM_CPU *cpu)
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{
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_mmu_log_ifault (cpu, MMU_STATE (cpu), PCREG, cec_get_ivg (cpu) >= 0);
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}
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static void
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_mmu_log_fault (SIM_CPU *cpu, struct bfin_mmu *mmu, bu32 addr, bool write,
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bool inst, bool miss, bool supv, bool dag1, bu32 faults)
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{
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bu32 *fault_status, *fault_addr;
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/* No logging in non-OS mode. */
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if (!mmu)
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return;
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fault_status = inst ? &mmu->icplb_fault_status : &mmu->dcplb_fault_status;
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fault_addr = inst ? &mmu->icplb_fault_addr : &mmu->dcplb_fault_addr;
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/* ICPLB regs always get updated. */
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if (!inst)
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_mmu_log_ifault (cpu, mmu, PCREG, supv);
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*fault_addr = addr;
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*fault_status =
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(miss << 19) |
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(dag1 << 18) |
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(supv << 17) |
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(write << 16) |
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faults;
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}
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static void
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_mmu_process_fault (SIM_CPU *cpu, struct bfin_mmu *mmu, bu32 addr, bool write,
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bool inst, bool unaligned, bool miss, bool supv, bool dag1)
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{
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int excp;
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/* See order in mmu_check_addr() */
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if (unaligned)
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excp = inst ? VEC_MISALI_I : VEC_MISALI_D;
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else if (addr >= BFIN_SYSTEM_MMR_BASE)
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excp = VEC_ILL_RES;
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else if (!mmu)
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excp = inst ? VEC_CPLB_I_M : VEC_CPLB_M;
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else
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{
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/* Misses are hardware errors. */
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cec_hwerr (cpu, HWERR_EXTERN_ADDR);
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return;
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}
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_mmu_log_fault (cpu, mmu, addr, write, inst, miss, supv, dag1, 0);
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cec_exception (cpu, excp);
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}
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void
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mmu_process_fault (SIM_CPU *cpu, bu32 addr, bool write, bool inst,
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bool unaligned, bool miss)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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struct bfin_mmu *mmu;
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if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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mmu = NULL;
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else
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mmu = MMU_STATE (cpu);
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_mmu_process_fault (cpu, mmu, addr, write, inst, unaligned, miss,
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cec_is_supervisor_mode (cpu),
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BFIN_CPU_STATE.multi_pc == PCREG + 6);
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}
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/* Return values:
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-2: no known problems
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-1: valid
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0: miss
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1: protection violation
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2: multiple hits
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3: unaligned
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4: miss; hwerr */
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static int
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mmu_check_implicit_addr (SIM_CPU *cpu, bu32 addr, bool inst, int size,
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bool supv, bool dag1)
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{
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bool l1 = ((addr & 0xFF000000) == 0xFF000000);
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bu32 amask = (addr & 0xFFF00000);
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if (addr & (size - 1))
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return 3;
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/* MMRs may never be executable or accessed from usermode. */
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if (addr >= BFIN_SYSTEM_MMR_BASE)
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{
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if (inst)
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return 0;
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else if (!supv || dag1)
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return 1;
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else
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return -1;
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}
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else if (inst)
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{
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/* Some regions are not executable. */
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/* XXX: Should this be in the model data ? Core B 561 ? */
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if (l1)
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return (amask == 0xFFA00000) ? -1 : 1;
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}
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else
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{
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/* Some regions are not readable. */
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/* XXX: Should this be in the model data ? Core B 561 ? */
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if (l1)
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return (amask != 0xFFA00000) ? -1 : 4;
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}
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return -2;
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}
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/* Exception order per the PRM (first has highest):
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Inst Multiple CPLB Hits
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Inst Misaligned Access
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Inst Protection Violation
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Inst CPLB Miss
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Only the alignment matters in non-OS mode though. */
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static int
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_mmu_check_addr (SIM_CPU *cpu, bu32 addr, bool write, bool inst, int size)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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struct bfin_mmu *mmu;
|
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bu32 *fault_status, *fault_addr, *mem_control, *cplb_addr, *cplb_data;
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bu32 faults;
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bool supv, do_excp, dag1;
|
||
int i, hits;
|
||
|
||
supv = cec_is_supervisor_mode (cpu);
|
||
dag1 = (BFIN_CPU_STATE.multi_pc == PCREG + 6);
|
||
|
||
if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT || bfin_mmu_skip_cplbs)
|
||
{
|
||
int ret = mmu_check_implicit_addr (cpu, addr, inst, size, supv, dag1);
|
||
/* Valid hits and misses are OK in non-OS envs. */
|
||
if (ret < 0)
|
||
return 0;
|
||
_mmu_process_fault (cpu, NULL, addr, write, inst, (ret == 3), false, supv, dag1);
|
||
}
|
||
|
||
mmu = MMU_STATE (cpu);
|
||
fault_status = inst ? &mmu->icplb_fault_status : &mmu->dcplb_fault_status;
|
||
fault_addr = inst ? &mmu->icplb_fault_addr : &mmu->dcplb_fault_addr;
|
||
mem_control = inst ? &mmu->imem_control : &mmu->dmem_control;
|
||
cplb_addr = inst ? &mmu->icplb_addr[0] : &mmu->dcplb_addr[0];
|
||
cplb_data = inst ? &mmu->icplb_data[0] : &mmu->dcplb_data[0];
|
||
|
||
faults = 0;
|
||
hits = 0;
|
||
do_excp = false;
|
||
|
||
/* CPLBs disabled -> little to do. */
|
||
if (!(*mem_control & ENCPLB))
|
||
{
|
||
hits = 1;
|
||
goto implicit_check;
|
||
}
|
||
|
||
/* Check all the CPLBs first. */
|
||
for (i = 0; i < 16; ++i)
|
||
{
|
||
const bu32 pages[4] = { 0x400, 0x1000, 0x100000, 0x400000 };
|
||
bu32 addr_lo, addr_hi;
|
||
|
||
/* Skip invalid entries. */
|
||
if (!(cplb_data[i] & CPLB_VALID))
|
||
continue;
|
||
|
||
/* See if this entry covers this address. */
|
||
addr_lo = cplb_addr[i];
|
||
addr_hi = cplb_addr[i] + pages[(cplb_data[i] & PAGE_SIZE) >> 16];
|
||
if (addr < addr_lo || addr >= addr_hi)
|
||
continue;
|
||
|
||
++hits;
|
||
faults |= (1 << i);
|
||
if (write)
|
||
{
|
||
if (!supv && !(cplb_data[i] & CPLB_USER_WR))
|
||
do_excp = true;
|
||
if (supv && !(cplb_data[i] & CPLB_SUPV_WR))
|
||
do_excp = true;
|
||
if ((cplb_data[i] & (CPLB_WT | CPLB_L1_CHBL | CPLB_DIRTY)) == CPLB_L1_CHBL)
|
||
do_excp = true;
|
||
}
|
||
else
|
||
{
|
||
if (!supv && !(cplb_data[i] & CPLB_USER_RD))
|
||
do_excp = true;
|
||
}
|
||
}
|
||
|
||
/* Handle default/implicit CPLBs. */
|
||
if (!do_excp && hits < 2)
|
||
{
|
||
int ihits;
|
||
implicit_check:
|
||
ihits = mmu_check_implicit_addr (cpu, addr, inst, size, supv, dag1);
|
||
switch (ihits)
|
||
{
|
||
/* No faults and one match -> good to go. */
|
||
case -1: return 0;
|
||
case -2:
|
||
if (hits == 1)
|
||
return 0;
|
||
break;
|
||
case 4:
|
||
cec_hwerr (cpu, HWERR_EXTERN_ADDR);
|
||
return 0;
|
||
default:
|
||
hits = ihits;
|
||
}
|
||
}
|
||
else
|
||
/* Normalize hit count so hits==2 is always multiple hit exception. */
|
||
hits = min (2, hits);
|
||
|
||
_mmu_log_fault (cpu, mmu, addr, write, inst, hits == 0, supv, dag1, faults);
|
||
|
||
if (inst)
|
||
{
|
||
int iexcps[] = { VEC_CPLB_I_M, VEC_CPLB_I_VL, VEC_CPLB_I_MHIT, VEC_MISALI_I };
|
||
return iexcps[hits];
|
||
}
|
||
else
|
||
{
|
||
int dexcps[] = { VEC_CPLB_M, VEC_CPLB_VL, VEC_CPLB_MHIT, VEC_MISALI_D };
|
||
return dexcps[hits];
|
||
}
|
||
}
|
||
|
||
void
|
||
mmu_check_addr (SIM_CPU *cpu, bu32 addr, bool write, bool inst, int size)
|
||
{
|
||
int excp = _mmu_check_addr (cpu, addr, write, inst, size);
|
||
if (excp)
|
||
cec_exception (cpu, excp);
|
||
}
|
||
|
||
void
|
||
mmu_check_cache_addr (SIM_CPU *cpu, bu32 addr, bool write, bool inst)
|
||
{
|
||
bu32 cacheaddr;
|
||
int excp;
|
||
|
||
cacheaddr = addr & ~(BFIN_L1_CACHE_BYTES - 1);
|
||
excp = _mmu_check_addr (cpu, cacheaddr, write, inst, BFIN_L1_CACHE_BYTES);
|
||
if (excp == 0)
|
||
return;
|
||
|
||
/* Most exceptions are ignored with cache funcs. */
|
||
/* XXX: Not sure if we should be ignoring CPLB misses. */
|
||
if (inst)
|
||
{
|
||
if (excp == VEC_CPLB_I_VL)
|
||
return;
|
||
}
|
||
else
|
||
{
|
||
if (excp == VEC_CPLB_VL)
|
||
return;
|
||
}
|
||
cec_exception (cpu, excp);
|
||
}
|