140 lines
4.0 KiB
C
140 lines
4.0 KiB
C
/* Common target dependent code for GNU/Linux on ARM systems.
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Copyright (C) 1999-2018 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "common-defs.h"
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#include "common-regcache.h"
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#include "arch/arm.h"
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#include "arm-linux.h"
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#include "arch/arm-get-next-pcs.h"
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/* Calculate the offset from stack pointer of the pc register on the stack
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in the case of a sigreturn or sigreturn_rt syscall. */
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int
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arm_linux_sigreturn_next_pc_offset (unsigned long sp,
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unsigned long sp_data,
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unsigned long svc_number,
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int is_sigreturn)
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{
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/* Offset of R0 register. */
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int r0_offset = 0;
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/* Offset of PC register. */
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int pc_offset = 0;
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if (is_sigreturn)
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{
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if (sp_data == ARM_NEW_SIGFRAME_MAGIC)
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r0_offset = ARM_UCONTEXT_SIGCONTEXT + ARM_SIGCONTEXT_R0;
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else
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r0_offset = ARM_SIGCONTEXT_R0;
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}
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else
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{
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if (sp_data == sp + ARM_OLD_RT_SIGFRAME_SIGINFO)
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r0_offset = ARM_OLD_RT_SIGFRAME_UCONTEXT;
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else
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r0_offset = ARM_NEW_RT_SIGFRAME_UCONTEXT;
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r0_offset += ARM_UCONTEXT_SIGCONTEXT + ARM_SIGCONTEXT_R0;
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}
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pc_offset = r0_offset + INT_REGISTER_SIZE * ARM_PC_REGNUM;
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return pc_offset;
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}
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/* Implementation of "fixup" method of struct arm_get_next_pcs_ops
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for arm-linux. */
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CORE_ADDR
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arm_linux_get_next_pcs_fixup (struct arm_get_next_pcs *self,
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CORE_ADDR nextpc)
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{
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/* The Linux kernel offers some user-mode helpers in a high page. We can
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not read this page (as of 2.6.23), and even if we could then we
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couldn't set breakpoints in it, and even if we could then the atomic
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operations would fail when interrupted. They are all (tail) called
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as functions and return to the address in LR. However, when GDB single
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step this instruction, this instruction isn't executed yet, and LR
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may not be updated yet. In other words, GDB can get the target
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address from LR if this instruction isn't BL or BLX. */
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if (nextpc > 0xffff0000)
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{
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int bl_blx_p = 0;
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CORE_ADDR pc = regcache_read_pc (self->regcache);
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int pc_incr = 0;
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if (self->ops->is_thumb (self))
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{
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unsigned short inst1
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= self->ops->read_mem_uint (pc, 2, self->byte_order_for_code);
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if (bits (inst1, 8, 15) == 0x47 && bit (inst1, 7))
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{
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/* BLX Rm */
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bl_blx_p = 1;
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pc_incr = 2;
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}
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else if (thumb_insn_size (inst1) == 4)
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{
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unsigned short inst2;
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inst2 = self->ops->read_mem_uint (pc + 2, 2,
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self->byte_order_for_code);
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if ((inst1 & 0xf800) == 0xf000 && bits (inst2, 14, 15) == 0x3)
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{
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/* BL <label> and BLX <label> */
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bl_blx_p = 1;
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pc_incr = 4;
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}
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}
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pc_incr = MAKE_THUMB_ADDR (pc_incr);
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}
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else
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{
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unsigned int insn
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= self->ops->read_mem_uint (pc, 4, self->byte_order_for_code);
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if (bits (insn, 28, 31) == INST_NV)
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{
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if (bits (insn, 25, 27) == 0x5) /* BLX <label> */
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bl_blx_p = 1;
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}
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else
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{
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if (bits (insn, 24, 27) == 0xb /* BL <label> */
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|| bits (insn, 4, 27) == 0x12fff3 /* BLX Rm */)
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bl_blx_p = 1;
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}
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pc_incr = 4;
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}
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/* If the instruction BL or BLX, the target address is the following
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instruction of BL or BLX, otherwise, the target address is in LR
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already. */
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if (bl_blx_p)
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nextpc = pc + pc_incr;
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else
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nextpc = regcache_raw_get_unsigned (self->regcache, ARM_LR_REGNUM);
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}
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return nextpc;
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}
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