522 lines
15 KiB
C
522 lines
15 KiB
C
# Simulator main loop for frv. -*- C -*-
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# Copyright (C) 1998, 1999, 2000, 2001, 2003, 2007, 2008, 2009
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# Free Software Foundation, Inc.
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# Contributed by Red Hat.
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#
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# This file is part of the GNU Simulators.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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# Syntax:
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# /bin/sh mainloop.in command
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#
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# Command is one of:
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#
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# init
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# support
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# extract-{simple,scache,pbb}
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# {full,fast}-exec-{simple,scache,pbb}
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#
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# A target need only provide a "full" version of one of simple,scache,pbb.
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# If the target wants it can also provide a fast version of same.
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# It can't provide more than this.
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# ??? After a few more ports are done, revisit.
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# Will eventually need to machine generate a lot of this.
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case "x$1" in
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xsupport)
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cat <<EOF
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static INLINE const IDESC *
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extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
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int fast_p)
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{
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const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
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@cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
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if (! fast_p)
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{
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int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
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int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
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@cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
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}
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return id;
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}
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static INLINE SEM_PC
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execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
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{
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SEM_PC vpc;
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/* Force gr0 to zero before every insn. */
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@cpu@_h_gr_set (current_cpu, 0, 0);
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if (fast_p)
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{
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vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
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}
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else
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{
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ARGBUF *abuf = &sc->argbuf;
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const IDESC *idesc = abuf->idesc;
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#if WITH_SCACHE_PBB
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int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
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#else
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int virtual_p = 0;
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#endif
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if (! virtual_p)
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{
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/* FIXME: call x-before */
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if (ARGBUF_PROFILE_P (abuf))
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PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
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/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
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if (FRV_COUNT_CYCLES (current_cpu, ARGBUF_PROFILE_P (abuf)))
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{
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@cpu@_model_insn_before (current_cpu, sc->first_insn_p);
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model_insn = FRV_INSN_MODEL_PASS_1;
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if (idesc->timing->model_fn != NULL)
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(*idesc->timing->model_fn) (current_cpu, sc);
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}
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else
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model_insn = FRV_INSN_NO_MODELING;
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TRACE_INSN_INIT (current_cpu, abuf, 1);
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TRACE_INSN (current_cpu, idesc->idata,
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(const struct argbuf *) abuf, abuf->addr);
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}
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#if WITH_SCACHE
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vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
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#else
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vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
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#endif
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if (! virtual_p)
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{
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/* FIXME: call x-after */
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if (FRV_COUNT_CYCLES (current_cpu, ARGBUF_PROFILE_P (abuf)))
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{
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int cycles;
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if (idesc->timing->model_fn != NULL)
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{
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model_insn = FRV_INSN_MODEL_PASS_2;
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cycles = (*idesc->timing->model_fn) (current_cpu, sc);
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}
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else
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cycles = 1;
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@cpu@_model_insn_after (current_cpu, sc->last_insn_p, cycles);
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}
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TRACE_INSN_FINI (current_cpu, abuf, 1);
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}
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}
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return vpc;
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}
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static void
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@cpu@_parallel_write_init (SIM_CPU *current_cpu)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
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CGEN_WRITE_QUEUE_CLEAR (q);
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previous_vliw_pc = CPU_PC_GET(current_cpu);
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frv_interrupt_state.f_ne_flags[0] = 0;
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frv_interrupt_state.f_ne_flags[1] = 0;
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frv_interrupt_state.imprecise_interrupt = NULL;
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}
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static void
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@cpu@_parallel_write_queued (SIM_CPU *current_cpu)
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{
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int i;
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FRV_VLIW *vliw = CPU_VLIW (current_cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
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/* Loop over the queued writes, executing them. Set the pc to the address
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of the insn which queued each write for the proper context in case an
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interrupt is caused. Restore the proper pc after the writes are
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completed. */
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IADDR save_pc = CPU_PC_GET (current_cpu);
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IADDR new_pc = save_pc;
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int branch_taken = 0;
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int limit = CGEN_WRITE_QUEUE_INDEX (q);
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frv_interrupt_state.data_written.length = 0;
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for (i = 0; i < limit; ++i)
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{
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CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, i);
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/* If an imprecise interrupt was generated, then, check whether the
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result should still be written. */
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if (frv_interrupt_state.imprecise_interrupt != NULL)
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{
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/* Only check writes by the insn causing the exception. */
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if (CGEN_WRITE_QUEUE_ELEMENT_IADDR (item)
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== frv_interrupt_state.imprecise_interrupt->vpc)
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{
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/* Execute writes of floating point operations resulting in
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overflow, underflow or inexact. */
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if (frv_interrupt_state.imprecise_interrupt->kind
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== FRV_FP_EXCEPTION)
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{
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if ((frv_interrupt_state.imprecise_interrupt
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->u.fp_info.fsr_mask
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& ~(FSR_INEXACT | FSR_OVERFLOW | FSR_UNDERFLOW)))
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continue; /* Don't execute */
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}
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/* Execute writes marked as 'forced'. */
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else if (! (CGEN_WRITE_QUEUE_ELEMENT_FLAGS (item)
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& FRV_WRITE_QUEUE_FORCE_WRITE))
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continue; /* Don't execute */
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}
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}
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/* Only execute the first branch on the queue. */
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if (CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_PC_WRITE
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|| CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_FN_PC_WRITE)
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{
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if (branch_taken)
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continue;
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branch_taken = 1;
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if (CGEN_WRITE_QUEUE_ELEMENT_KIND (item) == CGEN_PC_WRITE)
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new_pc = item->kinds.pc_write.value;
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else
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new_pc = item->kinds.fn_pc_write.value;
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}
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CPU_PC_SET (current_cpu, CGEN_WRITE_QUEUE_ELEMENT_IADDR (item));
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frv_save_data_written_for_interrupts (current_cpu, item);
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cgen_write_queue_element_execute (current_cpu, item);
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}
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/* Update the LR with the address of the next insn if the flag is set.
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This flag gets set in frvbf_set_write_next_vliw_to_LR by the JMPL,
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JMPIL and CALL insns. */
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if (frvbf_write_next_vliw_addr_to_LR)
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{
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frvbf_h_spr_set_handler (current_cpu, H_SPR_LR, save_pc);
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frvbf_write_next_vliw_addr_to_LR = 0;
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}
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CPU_PC_SET (current_cpu, new_pc);
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CGEN_WRITE_QUEUE_CLEAR (q);
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}
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void
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@cpu@_perform_writeback (SIM_CPU *current_cpu)
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{
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@cpu@_parallel_write_queued (current_cpu);
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}
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static unsigned cache_reqno = 0x80000000; /* Start value is for debugging. */
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#if 0 /* experimental */
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/* FR400 has single prefetch. */
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static void
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fr400_simulate_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc)
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{
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int cur_ix;
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FRV_CACHE *cache;
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/* The cpu receives 8 bytes worth of insn data for each fetch aligned
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on 8 byte boundary. */
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#define FR400_FETCH_SIZE 8
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cur_ix = LS;
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vpc &= ~(FR400_FETCH_SIZE - 1);
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cache = CPU_INSN_CACHE (current_cpu);
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/* Request a load of the current address buffer, if necessary. */
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if (frv_insn_fetch_buffer[cur_ix].address != vpc)
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{
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frv_insn_fetch_buffer[cur_ix].address = vpc;
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frv_insn_fetch_buffer[cur_ix].reqno = cache_reqno++;
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if (FRV_COUNT_CYCLES (current_cpu, 1))
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frv_cache_request_load (cache, frv_insn_fetch_buffer[cur_ix].reqno,
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frv_insn_fetch_buffer[cur_ix].address,
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UNIT_I0 + cur_ix);
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}
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/* Wait for the current address buffer to be loaded, if necessary. */
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if (FRV_COUNT_CYCLES (current_cpu, 1))
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{
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FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
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int wait;
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/* Account for any branch penalty. */
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if (ps->branch_penalty > 0 && ! ps->past_first_p)
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{
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frv_model_advance_cycles (current_cpu, ps->branch_penalty);
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frv_model_trace_wait_cycles (current_cpu, ps->branch_penalty,
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"Branch penalty:");
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ps->branch_penalty = 0;
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}
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/* Account for insn fetch latency. */
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wait = 0;
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while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
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{
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frv_model_advance_cycles (current_cpu, 1);
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++wait;
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}
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frv_model_trace_wait_cycles (current_cpu, wait, "Insn fetch:");
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return;
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}
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/* Otherwise just load the insns directly from the cache.
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*/
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if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
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{
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frv_cache_read (cache, cur_ix, vpc);
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frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
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}
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}
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#endif /* experimental */
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/* FR500 has dual prefetch. */
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static void
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simulate_dual_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc, int fetch_size)
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{
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int i;
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int cur_ix, pre_ix;
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SI pre_address;
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FRV_CACHE *cache;
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/* See if the pc is within the addresses specified by either of the
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fetch buffers. If so, that will be the current buffer. Otherwise,
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arbitrarily select the LD buffer as the current one since it gets
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priority in the case of interfering load requests. */
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cur_ix = LD;
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vpc &= ~(fetch_size - 1);
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for (i = LS; i < FRV_CACHE_PIPELINES; ++i)
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{
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if (frv_insn_fetch_buffer[i].address == vpc)
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{
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cur_ix = i;
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break;
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}
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}
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cache = CPU_INSN_CACHE (current_cpu);
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/* Request a load of the current address buffer, if necessary. */
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if (frv_insn_fetch_buffer[cur_ix].address != vpc)
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{
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frv_insn_fetch_buffer[cur_ix].address = vpc;
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frv_insn_fetch_buffer[cur_ix].reqno = cache_reqno++;
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if (FRV_COUNT_CYCLES (current_cpu, 1))
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frv_cache_request_load (cache, frv_insn_fetch_buffer[cur_ix].reqno,
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frv_insn_fetch_buffer[cur_ix].address,
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UNIT_I0 + cur_ix);
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}
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/* If the prefetch buffer does not represent the next sequential address, then
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request a load of the next sequential address. */
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pre_ix = (cur_ix + 1) % FRV_CACHE_PIPELINES;
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pre_address = vpc + fetch_size;
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if (frv_insn_fetch_buffer[pre_ix].address != pre_address)
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{
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frv_insn_fetch_buffer[pre_ix].address = pre_address;
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frv_insn_fetch_buffer[pre_ix].reqno = cache_reqno++;
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if (FRV_COUNT_CYCLES (current_cpu, 1))
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frv_cache_request_load (cache, frv_insn_fetch_buffer[pre_ix].reqno,
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frv_insn_fetch_buffer[pre_ix].address,
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UNIT_I0 + pre_ix);
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}
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/* If counting cycles, account for any branch penalty and/or insn fetch
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latency here. */
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if (FRV_COUNT_CYCLES (current_cpu, 1))
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{
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FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
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int wait;
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/* Account for any branch penalty. */
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if (ps->branch_penalty > 0 && ! ps->past_first_p)
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{
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frv_model_advance_cycles (current_cpu, ps->branch_penalty);
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frv_model_trace_wait_cycles (current_cpu, ps->branch_penalty,
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"Branch penalty:");
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ps->branch_penalty = 0;
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}
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/* Account for insn fetch latency. */
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wait = 0;
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while (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
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{
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frv_model_advance_cycles (current_cpu, 1);
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++wait;
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}
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frv_model_trace_wait_cycles (current_cpu, wait, "Insn fetch:");
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return;
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}
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/* Otherwise just load the insns directly from the cache.
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*/
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if (frv_insn_fetch_buffer[cur_ix].reqno != NO_REQNO)
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{
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frv_cache_read (cache, cur_ix, vpc);
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frv_insn_fetch_buffer[cur_ix].reqno = NO_REQNO;
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}
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if (frv_insn_fetch_buffer[pre_ix].reqno != NO_REQNO)
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{
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frv_cache_read (cache, pre_ix, pre_address);
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frv_insn_fetch_buffer[pre_ix].reqno = NO_REQNO;
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}
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}
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static void
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@cpu@_simulate_insn_prefetch (SIM_CPU *current_cpu, IADDR vpc)
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{
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SI hsr0;
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SIM_DESC sd;
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/* Nothing to do if not counting cycles and the cache is not enabled. */
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hsr0 = GET_HSR0 ();
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if (! GET_HSR0_ICE (hsr0) && ! FRV_COUNT_CYCLES (current_cpu, 1))
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return;
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/* Different machines handle prefetch defferently. */
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sd = CPU_STATE (current_cpu);
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_fr400:
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case bfd_mach_fr450:
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simulate_dual_insn_prefetch (current_cpu, vpc, 8);
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break;
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case bfd_mach_frvtomcat:
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case bfd_mach_fr500:
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case bfd_mach_fr550:
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case bfd_mach_frv:
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simulate_dual_insn_prefetch (current_cpu, vpc, 16);
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break;
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default:
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break;
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}
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}
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int frv_save_profile_model_p;
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EOF
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;;
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xinit)
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cat <<EOF
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/*xxxinit*/
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/* If the timer is enabled, then we will enable model profiling during
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execution. This is because the timer needs accurate cycles counts to
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work properly. Save the original setting of model profiling. */
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if (frv_interrupt_state.timer.enabled)
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frv_save_profile_model_p = PROFILE_MODEL_P (current_cpu);
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EOF
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;;
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xextract-simple | xextract-scache)
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# Inputs: current_cpu, vpc, sc, FAST_P
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# Outputs: sc filled in
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# SET_LAST_INSN_P(last_p) called to indicate whether insn is last one
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cat <<EOF
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{
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CGEN_INSN_INT insn = frvbf_read_imem_USI (current_cpu, vpc);
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extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
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SET_LAST_INSN_P ((insn & 0x80000000) != 0);
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}
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EOF
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;;
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xfull-exec-* | xfast-exec-*)
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# Inputs: current_cpu, vpc, FAST_P
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# Outputs:
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# vpc contains the address of the next insn to execute
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# pc of current_cpu must be up to date (=vpc) upon exit
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# CPU_INSN_COUNT (current_cpu) must be updated by number of insns executed
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#
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# Unlike the non-parallel case, this version is responsible for doing the
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# scache lookup.
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cat <<EOF
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{
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FRV_VLIW *vliw;
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int first_insn_p = 1;
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int last_insn_p = 0;
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int ninsns;
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CGEN_ATTR_VALUE_ENUM_TYPE slot;
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/* If the timer is enabled, then enable model profiling. This is because
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the timer needs accurate cycles counts to work properly. */
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if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p)
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sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "1");
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/* Init parallel-write queue and vliw. */
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@cpu@_parallel_write_init (current_cpu);
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vliw = CPU_VLIW (current_cpu);
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frv_vliw_reset (vliw, STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach,
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CPU_ELF_FLAGS (current_cpu));
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frv_current_fm_slot = UNIT_NIL;
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for (ninsns = 0; ! last_insn_p && ninsns < FRV_VLIW_SIZE; ++ninsns)
|
|
{
|
|
SCACHE *sc;
|
|
const CGEN_INSN *insn;
|
|
int error;
|
|
/* Go through the motions of finding the insns in the cache. */
|
|
@cpu@_simulate_insn_prefetch (current_cpu, vpc);
|
|
|
|
sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
|
|
sc->first_insn_p = first_insn_p;
|
|
last_insn_p = sc->last_insn_p;
|
|
|
|
/* Add the insn to the vliw and set up the interrupt state. */
|
|
insn = sc->argbuf.idesc->idata;
|
|
error = frv_vliw_add_insn (vliw, insn);
|
|
if (! error)
|
|
frv_vliw_setup_insn (current_cpu, insn);
|
|
frv_detect_insn_access_interrupts (current_cpu, sc);
|
|
slot = (*vliw->current_vliw)[vliw->next_slot - 1];
|
|
if (slot >= UNIT_FM0 && slot <= UNIT_FM3)
|
|
frv_current_fm_slot = slot;
|
|
|
|
vpc = execute (current_cpu, sc, FAST_P);
|
|
|
|
SET_H_PC (vpc); /* needed for interrupt handling */
|
|
first_insn_p = 0;
|
|
}
|
|
|
|
/* If the timer is enabled, and model profiling was not originally enabled,
|
|
then turn it off again. This is the only place we can currently gain
|
|
control to do this. */
|
|
if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p)
|
|
sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "0");
|
|
|
|
/* Check for interrupts. Also handles writeback if necessary. */
|
|
frv_process_interrupts (current_cpu);
|
|
|
|
CPU_INSN_COUNT (current_cpu) += ninsns;
|
|
}
|
|
EOF
|
|
|
|
;;
|
|
|
|
*)
|
|
echo "Invalid argument to mainloop.in: $1" >&2
|
|
exit 1
|
|
;;
|
|
|
|
esac
|