510 lines
18 KiB
C
510 lines
18 KiB
C
/* tc-i386.h -- Header file for tc-i386.c
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Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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2001, 2002, 2003, 2004
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Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#ifndef TC_I386
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#define TC_I386 1
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#ifndef BFD_ASSEMBLER
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#error So, do you know what you are doing?
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#endif
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#ifdef ANSI_PROTOTYPES
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struct fix;
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#endif
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#define TARGET_BYTES_BIG_ENDIAN 0
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#ifdef TE_LYNX
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#define TARGET_FORMAT "coff-i386-lynx"
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#endif
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#define TARGET_ARCH bfd_arch_i386
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#define TARGET_MACH (i386_mach ())
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extern unsigned long i386_mach PARAMS ((void));
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#ifdef TE_FreeBSD
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#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
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#endif
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#ifdef TE_NetBSD
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#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
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#endif
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#ifdef TE_386BSD
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#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
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#endif
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#ifdef TE_LINUX
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#define AOUT_TARGET_FORMAT "a.out-i386-linux"
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#endif
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#ifdef TE_Mach
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#define AOUT_TARGET_FORMAT "a.out-mach3"
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#endif
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#ifdef TE_DYNIX
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#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
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#endif
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#ifndef AOUT_TARGET_FORMAT
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#define AOUT_TARGET_FORMAT "a.out-i386"
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#endif
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#ifdef TE_FreeBSD
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#define ELF_TARGET_FORMAT "elf32-i386-freebsd"
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#endif
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#ifndef ELF_TARGET_FORMAT
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#define ELF_TARGET_FORMAT "elf32-i386"
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#endif
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#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
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|| defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
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extern const char *i386_target_format PARAMS ((void));
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#define TARGET_FORMAT i386_target_format ()
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#else
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#ifdef OBJ_ELF
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#define TARGET_FORMAT ELF_TARGET_FORMAT
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#endif
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#ifdef OBJ_AOUT
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#define TARGET_FORMAT AOUT_TARGET_FORMAT
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#endif
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#endif
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#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
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#define md_end i386_elf_emit_arch_note
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extern void i386_elf_emit_arch_note PARAMS ((void));
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#endif
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#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
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#define LOCAL_LABELS_FB 1
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extern const char extra_symbol_chars[];
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#define tc_symbol_chars extra_symbol_chars
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#define MAX_OPERANDS 3 /* max operands per insn */
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#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
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#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
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/* Prefixes will be emitted in the order defined below.
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WAIT_PREFIX must be the first prefix since FWAIT is really is an
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instruction, and so must come before any prefixes. */
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#define WAIT_PREFIX 0
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#define LOCKREP_PREFIX 1
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#define ADDR_PREFIX 2
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#define DATA_PREFIX 3
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#define SEG_PREFIX 4
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#define REX_PREFIX 5 /* must come last. */
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#define MAX_PREFIXES 6 /* max prefixes per opcode */
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/* we define the syntax here (modulo base,index,scale syntax) */
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#define REGISTER_PREFIX '%'
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#define IMMEDIATE_PREFIX '$'
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#define ABSOLUTE_PREFIX '*'
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#define TWO_BYTE_OPCODE_ESCAPE 0x0f
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#define NOP_OPCODE (char) 0x90
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/* register numbers */
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#define EBP_REG_NUM 5
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#define ESP_REG_NUM 4
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/* modrm_byte.regmem for twobyte escape */
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#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
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/* index_base_byte.index for no index register addressing */
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#define NO_INDEX_REGISTER ESP_REG_NUM
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/* index_base_byte.base for no base register addressing */
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#define NO_BASE_REGISTER EBP_REG_NUM
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#define NO_BASE_REGISTER_16 6
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/* these are the instruction mnemonic suffixes. */
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#define WORD_MNEM_SUFFIX 'w'
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#define BYTE_MNEM_SUFFIX 'b'
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#define SHORT_MNEM_SUFFIX 's'
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#define LONG_MNEM_SUFFIX 'l'
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#define QWORD_MNEM_SUFFIX 'q'
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/* Intel Syntax */
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#define LONG_DOUBLE_MNEM_SUFFIX 'x'
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/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
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#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
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#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
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#define END_OF_INSN '\0'
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/* Intel Syntax */
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/* Values 0-4 map onto scale factor */
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#define BYTE_PTR 0
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#define WORD_PTR 1
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#define DWORD_PTR 2
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#define QWORD_PTR 3
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#define XWORD_PTR 4
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#define SHORT 5
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#define OFFSET_FLAT 6
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#define FLAT 7
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#define NONE_FOUND 8
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typedef struct
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{
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/* instruction name sans width suffix ("mov" for movl insns) */
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char *name;
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/* how many operands */
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unsigned int operands;
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/* base_opcode is the fundamental opcode byte without optional
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prefix(es). */
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unsigned int base_opcode;
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/* extension_opcode is the 3 bit extension for group <n> insns.
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This field is also used to store the 8-bit opcode suffix for the
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AMD 3DNow! instructions.
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If this template has no extension opcode (the usual case) use None */
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unsigned int extension_opcode;
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#define None 0xffff /* If no extension_opcode is possible. */
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/* cpu feature flags */
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unsigned int cpu_flags;
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#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
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#define Cpu186 0x2 /* i186 or better required */
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#define Cpu286 0x4 /* i286 or better required */
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#define Cpu386 0x8 /* i386 or better required */
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#define Cpu486 0x10 /* i486 or better required */
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#define Cpu586 0x20 /* i585 or better required */
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#define Cpu686 0x40 /* i686 or better required */
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#define CpuP4 0x80 /* Pentium4 or better required */
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#define CpuK6 0x100 /* AMD K6 or better required*/
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#define CpuAthlon 0x200 /* AMD Athlon or better required*/
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#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
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#define CpuMMX 0x800 /* MMX support required */
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#define CpuSSE 0x1000 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x4000 /* 3dnow! support required */
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#define CpuPNI 0x8000 /* Prescott New Instructions required */
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#define CpuPadLock 0x10000 /* VIA PadLock required */
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/* These flags are set by gas depending on the flag_code. */
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#define Cpu64 0x4000000 /* 64bit support required */
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#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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/* The default value for unknown CPUs - enable all features to avoid problems. */
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#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|CpuK6|CpuAthlon|CpuPadLock)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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the same instruction */
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unsigned int opcode_modifier;
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/* opcode_modifier bits: */
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#define W 0x1 /* set if operands can be words or dwords
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encoded the canonical way */
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#define D 0x2 /* D = 0 if Reg --> Regmem;
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D = 1 if Regmem --> Reg: MUST BE 0x2 */
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#define Modrm 0x4
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#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
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#define ShortForm 0x10 /* register is in low 3 bits of opcode */
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#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
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#define Jump 0x40 /* special case for jump insns. */
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#define JumpDword 0x80 /* call and jump */
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#define JumpByte 0x100 /* loop and jecxz */
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#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
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#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
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#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
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#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
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#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
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#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
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#define Size64 0x8000 /* needs size prefix if in 16-bit mode */
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#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
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#define DefaultSize 0x20000 /* default insn size depends on mode */
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#define No_bSuf 0x40000 /* b suffix on instruction illegal */
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#define No_wSuf 0x80000 /* w suffix on instruction illegal */
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#define No_lSuf 0x100000 /* l suffix on instruction illegal */
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#define No_sSuf 0x200000 /* s suffix on instruction illegal */
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#define No_qSuf 0x400000 /* q suffix on instruction illegal */
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#define No_xSuf 0x800000 /* x suffix on instruction illegal */
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#define FWait 0x1000000 /* instruction needs FWAIT */
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#define IsString 0x2000000 /* quick test for string instructions */
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#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
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#define IsPrefix 0x8000000 /* opcode is a prefix */
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#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
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#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
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#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
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#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
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/* operand_types[i] describes the type of operand i. This is made
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by OR'ing together all of the possible type masks. (e.g.
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'operand_types[i] = Reg|Imm' specifies that operand i can be
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either a register or an immediate operand. */
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unsigned int operand_types[3];
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/* operand_types[i] bits */
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/* register */
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#define Reg8 0x1 /* 8 bit reg */
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#define Reg16 0x2 /* 16 bit reg */
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#define Reg32 0x4 /* 32 bit reg */
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#define Reg64 0x8 /* 64 bit reg */
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/* immediate */
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#define Imm8 0x10 /* 8 bit immediate */
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#define Imm8S 0x20 /* 8 bit immediate sign extended */
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#define Imm16 0x40 /* 16 bit immediate */
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#define Imm32 0x80 /* 32 bit immediate */
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#define Imm32S 0x100 /* 32 bit immediate sign extended */
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#define Imm64 0x200 /* 64 bit immediate */
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#define Imm1 0x400 /* 1 bit immediate */
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/* memory */
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#define BaseIndex 0x800
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/* Disp8,16,32 are used in different ways, depending on the
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instruction. For jumps, they specify the size of the PC relative
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displacement, for baseindex type instructions, they specify the
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size of the offset relative to the base register, and for memory
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offset instructions such as `mov 1234,%al' they specify the size of
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the offset relative to the segment base. */
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#define Disp8 0x1000 /* 8 bit displacement */
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#define Disp16 0x2000 /* 16 bit displacement */
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#define Disp32 0x4000 /* 32 bit displacement */
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#define Disp32S 0x8000 /* 32 bit signed displacement */
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#define Disp64 0x10000 /* 64 bit displacement */
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/* specials */
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#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
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#define ShiftCount 0x40000 /* register to hold shift cound = cl */
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#define Control 0x80000 /* Control register */
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#define Debug 0x100000 /* Debug register */
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#define Test 0x200000 /* Test register */
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#define FloatReg 0x400000 /* Float register */
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#define FloatAcc 0x800000 /* Float stack top %st(0) */
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#define SReg2 0x1000000 /* 2 bit segment register */
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#define SReg3 0x2000000 /* 3 bit segment register */
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#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
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#define JumpAbsolute 0x8000000
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#define RegMMX 0x10000000 /* MMX register */
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#define RegXMM 0x20000000 /* XMM registers in PIII */
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#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
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/* InvMem is for instructions with a modrm byte that only allow a
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general register encoding in the i.tm.mode and i.tm.regmem fields,
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eg. control reg moves. They really ought to support a memory form,
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but don't, so we add an InvMem flag to the register operand to
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indicate that it should be encoded in the i.tm.regmem field. */
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#define InvMem 0x80000000
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#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
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#define WordReg (Reg16|Reg32|Reg64)
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#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
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#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
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#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
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#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
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#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
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/* The following aliases are defined because the opcode table
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carefully specifies the allowed memory types for each instruction.
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At the moment we can only tell a memory reference size by the
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instruction suffix, so there's not much point in defining Mem8,
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Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
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the suffix directly to check memory operands. */
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#define LLongMem AnyMem /* 64 bits (or more) */
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#define LongMem AnyMem /* 32 bit memory ref */
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#define ShortMem AnyMem /* 16 bit memory ref */
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#define WordMem AnyMem /* 16 or 32 bit memory ref */
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#define ByteMem AnyMem /* 8 bit memory ref */
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}
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template;
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/*
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'templates' is for grouping together 'template' structures for opcodes
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of the same name. This is only used for storing the insns in the grand
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ole hash table of insns.
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The templates themselves start at START and range up to (but not including)
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END.
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*/
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typedef struct
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{
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const template *start;
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const template *end;
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}
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templates;
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/* these are for register name --> number & type hash lookup */
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typedef struct
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{
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char *reg_name;
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unsigned int reg_type;
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unsigned int reg_flags;
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#define RegRex 0x1 /* Extended register. */
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#define RegRex64 0x2 /* Extended 8 bit register. */
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unsigned int reg_num;
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}
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reg_entry;
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typedef struct
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{
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char *seg_name;
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unsigned int seg_prefix;
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}
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seg_entry;
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/* 386 operand encoding bytes: see 386 book for details of this. */
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typedef struct
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{
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unsigned int regmem; /* codes register or memory operand */
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unsigned int reg; /* codes register operand (or extended opcode) */
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unsigned int mode; /* how to interpret regmem & reg */
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}
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modrm_byte;
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/* x86-64 extension prefix. */
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typedef int rex_byte;
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#define REX_OPCODE 0x40
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/* Indicates 64 bit operand size. */
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#define REX_MODE64 8
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/* High extension to reg field of modrm byte. */
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#define REX_EXTX 4
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/* High extension to SIB index field. */
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#define REX_EXTY 2
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/* High extension to base field of modrm or SIB, or reg field of opcode. */
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#define REX_EXTZ 1
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/* 386 opcode byte to code indirect addressing. */
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typedef struct
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{
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unsigned base;
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unsigned index;
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unsigned scale;
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}
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sib_byte;
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/* x86 arch names and features */
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typedef struct
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{
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const char *name; /* arch name */
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unsigned int flags; /* cpu feature flags */
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}
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arch_entry;
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/* The name of the global offset table generated by the compiler. Allow
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this to be overridden if need be. */
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#ifndef GLOBAL_OFFSET_TABLE_NAME
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#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
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#endif
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#ifndef LEX_AT
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#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
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extern void x86_cons PARAMS ((expressionS *, int));
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#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
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extern void x86_cons_fix_new
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PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
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#endif
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#ifdef TE_PE
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#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_pe_cons_fix_new(FRAG, OFF, LEN, EXP)
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extern void x86_pe_cons_fix_new
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PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
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#endif
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#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
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#define NO_RELOC BFD_RELOC_NONE
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void i386_validate_fix PARAMS ((struct fix *));
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#define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
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#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
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extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
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/* Values passed to md_apply_fix3 don't include the symbol value. */
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#define MD_APPLY_SYM_VALUE(FIX) 0
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/* ELF wants external syms kept, as does PE COFF. */
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#if defined (TE_PE) && defined (STRICT_PE_FORMAT)
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#define EXTERN_FORCE_RELOC \
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(OUTPUT_FLAVOR == bfd_target_elf_flavour \
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|| OUTPUT_FLAVOR == bfd_target_coff_flavour)
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#else
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#define EXTERN_FORCE_RELOC \
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(OUTPUT_FLAVOR == bfd_target_elf_flavour)
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#endif
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/* This expression evaluates to true if the relocation is for a local
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object for which we still want to do the relocation at runtime.
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False if we are willing to perform this relocation while building
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the .o file. GOTOFF does not need to be checked here because it is
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not pcrel. I am not sure if some of the others are ever used with
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pcrel, but it is easier to be safe than sorry. */
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#define TC_FORCE_RELOCATION_LOCAL(FIX) \
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(!(FIX)->fx_pcrel \
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|| (FIX)->fx_plt \
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|| (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \
|
|
|| (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \
|
|
|| (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \
|
|
|| TC_FORCE_RELOCATION (FIX))
|
|
|
|
#define md_operand(x)
|
|
|
|
extern const struct relax_type md_relax_table[];
|
|
#define TC_GENERIC_RELAX_TABLE md_relax_table
|
|
|
|
extern int optimize_align_code;
|
|
|
|
#define md_do_align(n, fill, len, max, around) \
|
|
if ((n) \
|
|
&& !need_pass_2 \
|
|
&& optimize_align_code \
|
|
&& (!(fill) \
|
|
|| ((char)*(fill) == (char)0x90 && (len) == 1)) \
|
|
&& subseg_text_p (now_seg)) \
|
|
{ \
|
|
frag_align_code ((n), (max)); \
|
|
goto around; \
|
|
}
|
|
|
|
#define MAX_MEM_FOR_RS_ALIGN_CODE 15
|
|
|
|
extern void i386_align_code PARAMS ((fragS *, int));
|
|
|
|
#define HANDLE_ALIGN(fragP) \
|
|
if (fragP->fr_type == rs_align_code) \
|
|
i386_align_code (fragP, (fragP->fr_next->fr_address \
|
|
- fragP->fr_address \
|
|
- fragP->fr_fix));
|
|
|
|
void i386_print_statistics PARAMS ((FILE *));
|
|
#define tc_print_statistics i386_print_statistics
|
|
|
|
#define md_number_to_chars number_to_chars_littleendian
|
|
|
|
#ifdef SCO_ELF
|
|
#define tc_init_after_args() sco_id ()
|
|
extern void sco_id PARAMS ((void));
|
|
#endif
|
|
|
|
/* We want .cfi_* pseudo-ops for generating unwind info. */
|
|
#define TARGET_USE_CFIPOP 1
|
|
|
|
extern unsigned int x86_dwarf2_return_column;
|
|
#define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
|
|
|
|
extern int x86_cie_data_alignment;
|
|
#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
|
|
|
|
#define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
|
|
extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
|
|
|
|
#define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
|
|
extern void tc_x86_frame_initial_instructions PARAMS ((void));
|
|
|
|
#endif /* TC_I386 */
|