ddfae34d82
* arch.c,arch.h,cpuall.h: Regenerate. * cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate. * traps.c (sim_engine_invalid_insn): PCADDR->IADDR. * cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Regenerate.
238 lines
6.5 KiB
C
238 lines
6.5 KiB
C
/* Decode header for m32rbf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef M32RBF_DECODE_H
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#define M32RBF_DECODE_H
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/* Run-time computed instruction descriptor. */
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struct idesc {
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#if WITH_SEM_SWITCH_FULL
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#ifdef __GNUC__
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void *sem_full_lab;
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#endif
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#else
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SEMANTIC_FN *sem_full;
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#endif
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#if WITH_SEM_SWITCH_FAST
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#ifdef __GNUC__
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void *sem_fast_lab;
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#endif
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#else
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SEMANTIC_FN *sem_fast;
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#endif
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/* Instruction number (index in IDESC table, profile table).
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Also used to switch on in non-gcc semantic switches. */
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int num;
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/* opcode table data */
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const CGEN_INSN *opcode;
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/* profiling/modelling support */
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const INSN_TIMING *timing;
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};
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extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
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CGEN_INSN_INT, CGEN_INSN_INT,
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ARGBUF *);
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/* Enum declaration for instructions in cpu family m32rbf. */
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typedef enum m32rbf_insn_type {
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M32RBF_INSN_X_INVALID, M32RBF_INSN_X_AFTER, M32RBF_INSN_X_BEFORE, M32RBF_INSN_X_CTI_CHAIN
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, M32RBF_INSN_X_CHAIN, M32RBF_INSN_X_BEGIN, M32RBF_INSN_ADD, M32RBF_INSN_ADD3
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, M32RBF_INSN_AND, M32RBF_INSN_AND3, M32RBF_INSN_OR, M32RBF_INSN_OR3
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, M32RBF_INSN_XOR, M32RBF_INSN_XOR3, M32RBF_INSN_ADDI, M32RBF_INSN_ADDV
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, M32RBF_INSN_ADDV3, M32RBF_INSN_ADDX, M32RBF_INSN_BC8, M32RBF_INSN_BC24
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, M32RBF_INSN_BEQ, M32RBF_INSN_BEQZ, M32RBF_INSN_BGEZ, M32RBF_INSN_BGTZ
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, M32RBF_INSN_BLEZ, M32RBF_INSN_BLTZ, M32RBF_INSN_BNEZ, M32RBF_INSN_BL8
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, M32RBF_INSN_BL24, M32RBF_INSN_BNC8, M32RBF_INSN_BNC24, M32RBF_INSN_BNE
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, M32RBF_INSN_BRA8, M32RBF_INSN_BRA24, M32RBF_INSN_CMP, M32RBF_INSN_CMPI
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, M32RBF_INSN_CMPU, M32RBF_INSN_CMPUI, M32RBF_INSN_DIV, M32RBF_INSN_DIVU
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, M32RBF_INSN_REM, M32RBF_INSN_REMU, M32RBF_INSN_JL, M32RBF_INSN_JMP
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, M32RBF_INSN_LD, M32RBF_INSN_LD_D, M32RBF_INSN_LDB, M32RBF_INSN_LDB_D
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, M32RBF_INSN_LDH, M32RBF_INSN_LDH_D, M32RBF_INSN_LDUB, M32RBF_INSN_LDUB_D
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, M32RBF_INSN_LDUH, M32RBF_INSN_LDUH_D, M32RBF_INSN_LD_PLUS, M32RBF_INSN_LD24
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, M32RBF_INSN_LDI8, M32RBF_INSN_LDI16, M32RBF_INSN_LOCK, M32RBF_INSN_MACHI
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, M32RBF_INSN_MACLO, M32RBF_INSN_MACWHI, M32RBF_INSN_MACWLO, M32RBF_INSN_MUL
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, M32RBF_INSN_MULHI, M32RBF_INSN_MULLO, M32RBF_INSN_MULWHI, M32RBF_INSN_MULWLO
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, M32RBF_INSN_MV, M32RBF_INSN_MVFACHI, M32RBF_INSN_MVFACLO, M32RBF_INSN_MVFACMI
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, M32RBF_INSN_MVFC, M32RBF_INSN_MVTACHI, M32RBF_INSN_MVTACLO, M32RBF_INSN_MVTC
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, M32RBF_INSN_NEG, M32RBF_INSN_NOP, M32RBF_INSN_NOT, M32RBF_INSN_RAC
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, M32RBF_INSN_RACH, M32RBF_INSN_RTE, M32RBF_INSN_SETH, M32RBF_INSN_SLL
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, M32RBF_INSN_SLL3, M32RBF_INSN_SLLI, M32RBF_INSN_SRA, M32RBF_INSN_SRA3
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, M32RBF_INSN_SRAI, M32RBF_INSN_SRL, M32RBF_INSN_SRL3, M32RBF_INSN_SRLI
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, M32RBF_INSN_ST, M32RBF_INSN_ST_D, M32RBF_INSN_STB, M32RBF_INSN_STB_D
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, M32RBF_INSN_STH, M32RBF_INSN_STH_D, M32RBF_INSN_ST_PLUS, M32RBF_INSN_ST_MINUS
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, M32RBF_INSN_SUB, M32RBF_INSN_SUBV, M32RBF_INSN_SUBX, M32RBF_INSN_TRAP
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, M32RBF_INSN_UNLOCK, M32RBF_INSN_MAX
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} M32RBF_INSN_TYPE;
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#if ! WITH_SEM_SWITCH_FULL
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#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,fn);
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#else
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#define SEMFULL(fn)
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#endif
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#if ! WITH_SEM_SWITCH_FAST
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#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_semf_,fn);
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#else
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#define SEMFAST(fn)
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#endif
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#define SEM(fn) SEMFULL (fn) SEMFAST (fn)
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/* The function version of the before/after handlers is always needed,
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so we always want the SEMFULL declaration of them. */
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extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_before);
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extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_after);
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SEM (x_invalid)
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SEM (x_after)
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SEM (x_before)
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SEM (x_cti_chain)
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SEM (x_chain)
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SEM (x_begin)
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SEM (add)
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SEM (add3)
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SEM (and)
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SEM (and3)
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SEM (or)
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SEM (or3)
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SEM (xor)
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SEM (xor3)
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SEM (addi)
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SEM (addv)
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SEM (addv3)
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SEM (addx)
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SEM (bc8)
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SEM (bc24)
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SEM (beq)
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SEM (beqz)
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SEM (bgez)
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SEM (bgtz)
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SEM (blez)
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SEM (bltz)
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SEM (bnez)
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SEM (bl8)
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SEM (bl24)
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SEM (bnc8)
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SEM (bnc24)
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SEM (bne)
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SEM (bra8)
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SEM (bra24)
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SEM (cmp)
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SEM (cmpi)
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SEM (cmpu)
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SEM (cmpui)
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SEM (div)
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SEM (divu)
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SEM (rem)
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SEM (remu)
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SEM (jl)
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SEM (jmp)
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SEM (ld)
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SEM (ld_d)
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SEM (ldb)
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SEM (ldb_d)
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SEM (ldh)
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SEM (ldh_d)
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SEM (ldub)
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SEM (ldub_d)
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SEM (lduh)
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SEM (lduh_d)
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SEM (ld_plus)
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SEM (ld24)
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SEM (ldi8)
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SEM (ldi16)
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SEM (lock)
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SEM (machi)
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SEM (maclo)
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SEM (macwhi)
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SEM (macwlo)
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SEM (mul)
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SEM (mulhi)
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SEM (mullo)
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SEM (mulwhi)
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SEM (mulwlo)
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SEM (mv)
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SEM (mvfachi)
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SEM (mvfaclo)
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SEM (mvfacmi)
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SEM (mvfc)
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SEM (mvtachi)
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SEM (mvtaclo)
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SEM (mvtc)
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SEM (neg)
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SEM (nop)
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SEM (not)
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SEM (rac)
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SEM (rach)
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SEM (rte)
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SEM (seth)
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SEM (sll)
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SEM (sll3)
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SEM (slli)
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SEM (sra)
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SEM (sra3)
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SEM (srai)
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SEM (srl)
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SEM (srl3)
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SEM (srli)
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SEM (st)
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SEM (st_d)
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SEM (stb)
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SEM (stb_d)
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SEM (sth)
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SEM (sth_d)
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SEM (st_plus)
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SEM (st_minus)
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SEM (sub)
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SEM (subv)
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SEM (subx)
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SEM (trap)
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SEM (unlock)
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#undef SEMFULL
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#undef SEMFAST
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#undef SEM
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/* Function unit handlers (user written). */
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extern int m32rbf_model_m32r_d_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
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extern int m32rbf_model_m32r_d_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
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extern int m32rbf_model_m32r_d_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
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extern int m32rbf_model_m32r_d_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
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extern int m32rbf_model_m32r_d_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
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extern int m32rbf_model_m32r_d_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*sr2*/, INT /*dr*/);
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extern int m32rbf_model_test_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
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/* Profiling before/after handlers (user written) */
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extern void m32rbf_model_insn_before (SIM_CPU *, int /*first_p*/);
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extern void m32rbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
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#endif /* M32RBF_DECODE_H */
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