783 lines
24 KiB
C
783 lines
24 KiB
C
/* Disassembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS USED TO GENERATE i960c-dis.c.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "dis-asm.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "i960c-opc.h"
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#include "opintl.h"
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#undef INLINE
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#ifdef __GNUC__
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#define INLINE __inline__
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#else
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#define INLINE
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#endif
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/* Default text to print if an instruction isn't recognized. */
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#define UNKNOWN_INSN_MSG _("*unknown*")
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/* Used by the ifield rtx function. */
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#define FLD(f) (fields->f)
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static int extract_normal
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PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
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unsigned int, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, bfd_vma, long *));
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static void print_normal
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PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int));
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static void print_address
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PARAMS ((CGEN_OPCODE_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
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static void print_keyword
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PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
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static int extract_insn_normal
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PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
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CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
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static void print_insn_normal
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PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
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bfd_vma, int));
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static int print_insn PARAMS ((CGEN_OPCODE_DESC, bfd_vma,
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disassemble_info *, char *, int));
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static int default_print_insn
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PARAMS ((CGEN_OPCODE_DESC, bfd_vma, disassemble_info *));
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/* -- disassembler routines inserted here */
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/* Main entry point for operand extraction.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `print_insn_normal', but keeping it
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separate makes clear the interface between `print_insn_normal' and each of
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the handlers.
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*/
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int
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i960_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc)
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CGEN_OPCODE_DESC od;
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int opindex;
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CGEN_EXTRACT_INFO *ex_info;
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CGEN_INSN_INT insn_value;
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CGEN_FIELDS * fields;
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bfd_vma pc;
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{
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int length;
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unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
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switch (opindex)
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{
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case I960_OPERAND_SRC1 :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, pc, & fields->f_src1);
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break;
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case I960_OPERAND_SRC2 :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, pc, & fields->f_src2);
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break;
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case I960_OPERAND_DST :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, pc, & fields->f_srcdst);
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break;
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case I960_OPERAND_LIT1 :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, pc, & fields->f_src1);
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break;
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case I960_OPERAND_LIT2 :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, pc, & fields->f_src2);
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break;
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case I960_OPERAND_ST_SRC :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, pc, & fields->f_srcdst);
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break;
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case I960_OPERAND_ABASE :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, pc, & fields->f_abase);
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break;
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case I960_OPERAND_OFFSET :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 20, 12, 32, total_length, pc, & fields->f_offset);
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break;
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case I960_OPERAND_SCALE :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 22, 3, 32, total_length, pc, & fields->f_scale);
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break;
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case I960_OPERAND_INDEX :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, pc, & fields->f_index);
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break;
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case I960_OPERAND_OPTDISP :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 32, 0, 32, 32, total_length, pc, & fields->f_optdisp);
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break;
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case I960_OPERAND_BR_SRC1 :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, pc, & fields->f_br_src1);
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break;
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case I960_OPERAND_BR_SRC2 :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, pc, & fields->f_br_src2);
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break;
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case I960_OPERAND_BR_DISP :
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{
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long value;
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 19, 11, 32, total_length, pc, & value);
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value = ((((value) << (2))) + (pc));
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fields->f_br_disp = value;
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}
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break;
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case I960_OPERAND_BR_LIT1 :
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, pc, & fields->f_br_src1);
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break;
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case I960_OPERAND_CTRL_DISP :
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{
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long value;
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length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 22, 32, total_length, pc, & value);
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value = ((((value) << (2))) + (pc));
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fields->f_ctrl_disp = value;
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}
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break;
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default :
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/* xgettext:c-format */
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fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
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opindex);
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abort ();
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}
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return length;
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}
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/* Main entry point for printing operands.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `print_insn_normal', but keeping it
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separate makes clear the interface between `print_insn_normal' and each of
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the handlers.
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*/
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void
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i960_cgen_print_operand (od, opindex, info, fields, attrs, pc, length)
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CGEN_OPCODE_DESC od;
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int opindex;
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disassemble_info * info;
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CGEN_FIELDS * fields;
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void const * attrs;
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bfd_vma pc;
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int length;
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{
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switch (opindex)
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{
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case I960_OPERAND_SRC1 :
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print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_src1, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case I960_OPERAND_SRC2 :
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print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_src2, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case I960_OPERAND_DST :
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print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_srcdst, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case I960_OPERAND_LIT1 :
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print_normal (od, info, fields->f_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case I960_OPERAND_LIT2 :
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print_normal (od, info, fields->f_src2, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case I960_OPERAND_ST_SRC :
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print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_srcdst, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case I960_OPERAND_ABASE :
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print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_abase, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case I960_OPERAND_OFFSET :
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print_normal (od, info, fields->f_offset, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case I960_OPERAND_SCALE :
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print_normal (od, info, fields->f_scale, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case I960_OPERAND_INDEX :
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print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_index, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case I960_OPERAND_OPTDISP :
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print_normal (od, info, fields->f_optdisp, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case I960_OPERAND_BR_SRC1 :
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print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_br_src1, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case I960_OPERAND_BR_SRC2 :
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print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_br_src2, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case I960_OPERAND_BR_DISP :
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print_address (od, info, fields->f_br_disp, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case I960_OPERAND_BR_LIT1 :
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print_normal (od, info, fields->f_br_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case I960_OPERAND_CTRL_DISP :
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print_address (od, info, fields->f_ctrl_disp, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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default :
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/* xgettext:c-format */
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fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
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opindex);
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abort ();
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}
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}
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cgen_extract_fn * const i960_cgen_extract_handlers[] =
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{
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0, /* default */
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extract_insn_normal,
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};
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cgen_print_fn * const i960_cgen_print_handlers[] =
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{
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0, /* default */
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print_insn_normal,
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};
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void
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i960_cgen_init_dis (od)
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CGEN_OPCODE_DESC od;
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{
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}
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#if ! CGEN_INT_INSN_P
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/* Subroutine of extract_normal.
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Ensure sufficient bytes are cached in EX_INFO.
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OFFSET is the offset in bytes from the start of the insn of the value.
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BYTES is the length of the needed value.
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Returns 1 for success, 0 for failure. */
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static INLINE int
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fill_cache (od, ex_info, offset, bytes, pc)
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CGEN_OPCODE_DESC od;
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CGEN_EXTRACT_INFO *ex_info;
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int offset, bytes;
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bfd_vma pc;
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{
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/* It's doubtful that the middle part has already been fetched so
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we don't optimize that case. kiss. */
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int mask;
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disassemble_info *info = (disassemble_info *) ex_info->dis_info;
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/* First do a quick check. */
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mask = (1 << bytes) - 1;
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if (((ex_info->valid >> offset) & mask) == mask)
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return 1;
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/* Search for the first byte we need to read. */
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for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
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if (! (mask & ex_info->valid))
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break;
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if (bytes)
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{
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int status;
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pc += offset;
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status = (*info->read_memory_func)
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(pc, ex_info->insn_bytes + offset, bytes, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return 0;
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}
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ex_info->valid |= ((1 << bytes) - 1) << offset;
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}
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return 1;
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}
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/* Subroutine of extract_normal. */
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static INLINE long
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extract_1 (od, ex_info, start, length, word_length, bufp, pc)
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CGEN_OPCODE_DESC od;
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CGEN_EXTRACT_INFO *ex_info;
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int start,length,word_length;
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unsigned char *bufp;
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bfd_vma pc;
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{
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unsigned long x,mask;
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int shift;
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int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG;
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switch (word_length)
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{
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case 8:
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x = *bufp;
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break;
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case 16:
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if (big_p)
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x = bfd_getb16 (bufp);
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else
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x = bfd_getl16 (bufp);
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break;
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case 24:
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/* ??? This may need reworking as these cases don't necessarily
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want the first byte and the last two bytes handled like this. */
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if (big_p)
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x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
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else
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x = bfd_getl16 (bufp) | (bufp[2] << 16);
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break;
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case 32:
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if (big_p)
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x = bfd_getb32 (bufp);
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else
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x = bfd_getl32 (bufp);
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break;
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default :
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abort ();
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}
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/* Written this way to avoid undefined behaviour. */
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mask = (((1L << (length - 1)) - 1) << 1) | 1;
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if (CGEN_INSN_LSB0_P)
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shift = (start + 1) - length;
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else
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shift = (word_length - (start + length));
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return (x >> shift) & mask;
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}
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#endif /* ! CGEN_INT_INSN_P */
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/* Default extraction routine.
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INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order,
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or sometimes less for cases like the m32r where the base insn size is 32
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but some insns are 16 bits.
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ATTRS is a mask of the boolean attributes. We only need `UNSIGNED',
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but for generality we take a bitmask of all of them.
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WORD_OFFSET is the offset in bits from the start of the insn of the value.
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WORD_LENGTH is the length of the word in bits in which the value resides.
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START is the starting bit number in the word, architecture origin.
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LENGTH is the length of VALUE in bits.
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TOTAL_LENGTH is the total length of the insn in bits.
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Returns 1 for success, 0 for failure. */
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/* ??? The return code isn't properly used. wip. */
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/* ??? This doesn't handle bfd_vma's. Create another function when
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necessary. */
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static int
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extract_normal (od, ex_info, insn_value, attrs, word_offset, start, length,
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word_length, total_length, pc, valuep)
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CGEN_OPCODE_DESC od;
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CGEN_EXTRACT_INFO *ex_info;
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CGEN_INSN_INT insn_value;
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unsigned int attrs;
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unsigned int word_offset, start, length, word_length, total_length;
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bfd_vma pc;
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long *valuep;
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{
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CGEN_INSN_INT value;
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/* If LENGTH is zero, this operand doesn't contribute to the value
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so give it a standard value of zero. */
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if (length == 0)
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{
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*valuep = 0;
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return 1;
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}
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if (CGEN_INT_INSN_P
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&& word_offset != 0)
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abort ();
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if (word_length > 32)
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abort ();
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/* For architectures with insns smaller than the insn-base-bitsize,
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word_length may be too big. */
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#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE
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if (word_offset == 0
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&& word_length > total_length)
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word_length = total_length;
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#endif
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/* Does the value reside in INSN_VALUE? */
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if (word_offset == 0)
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{
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/* Written this way to avoid undefined behaviour. */
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CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
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if (CGEN_INSN_LSB0_P)
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value = insn_value >> ((start + 1) - length);
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else
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value = insn_value >> (word_length - (start + length));
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value &= mask;
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/* sign extend? */
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if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
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&& (value & (1L << (length - 1))))
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value |= ~mask;
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}
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#if ! CGEN_INT_INSN_P
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||
|
||
else
|
||
{
|
||
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
|
||
|
||
if (word_length > 32)
|
||
abort ();
|
||
|
||
if (fill_cache (od, ex_info, word_offset / 8, word_length / 8, pc) == 0)
|
||
return 0;
|
||
|
||
value = extract_1 (od, ex_info, start, length, word_length, bufp, pc);
|
||
}
|
||
|
||
#endif /* ! CGEN_INT_INSN_P */
|
||
|
||
*valuep = value;
|
||
|
||
return 1;
|
||
}
|
||
|
||
/* Default print handler. */
|
||
|
||
static void
|
||
print_normal (od, dis_info, value, attrs, pc, length)
|
||
CGEN_OPCODE_DESC od;
|
||
PTR dis_info;
|
||
long value;
|
||
unsigned int attrs;
|
||
bfd_vma pc;
|
||
int length;
|
||
{
|
||
disassemble_info *info = (disassemble_info *) dis_info;
|
||
|
||
#ifdef CGEN_PRINT_NORMAL
|
||
CGEN_PRINT_NORMAL (od, info, value, attrs, pc, length);
|
||
#endif
|
||
|
||
/* Print the operand as directed by the attributes. */
|
||
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
|
||
; /* nothing to do */
|
||
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
|
||
(*info->fprintf_func) (info->stream, "0x%lx", value);
|
||
else
|
||
(*info->fprintf_func) (info->stream, "%ld", value);
|
||
}
|
||
|
||
/* Default address handler. */
|
||
|
||
static void
|
||
print_address (od, dis_info, value, attrs, pc, length)
|
||
CGEN_OPCODE_DESC od;
|
||
PTR dis_info;
|
||
bfd_vma value;
|
||
unsigned int attrs;
|
||
bfd_vma pc;
|
||
int length;
|
||
{
|
||
disassemble_info *info = (disassemble_info *) dis_info;
|
||
|
||
#ifdef CGEN_PRINT_ADDRESS
|
||
CGEN_PRINT_ADDRESS (od, info, value, attrs, pc, length);
|
||
#endif
|
||
|
||
/* Print the operand as directed by the attributes. */
|
||
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
|
||
; /* nothing to do */
|
||
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
|
||
(*info->print_address_func) (value, info);
|
||
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
|
||
(*info->print_address_func) (value, info);
|
||
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
|
||
(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
|
||
else
|
||
(*info->fprintf_func) (info->stream, "%ld", (long) value);
|
||
}
|
||
|
||
/* Keyword print handler. */
|
||
|
||
static void
|
||
print_keyword (od, dis_info, keyword_table, value, attrs)
|
||
CGEN_OPCODE_DESC od;
|
||
PTR dis_info;
|
||
CGEN_KEYWORD *keyword_table;
|
||
long value;
|
||
unsigned int attrs;
|
||
{
|
||
disassemble_info *info = (disassemble_info *) dis_info;
|
||
const CGEN_KEYWORD_ENTRY *ke;
|
||
|
||
ke = cgen_keyword_lookup_value (keyword_table, value);
|
||
if (ke != NULL)
|
||
(*info->fprintf_func) (info->stream, "%s", ke->name);
|
||
else
|
||
(*info->fprintf_func) (info->stream, "???");
|
||
}
|
||
|
||
/* Default insn extractor.
|
||
|
||
INSN_VALUE is the first CGEN_BASE_INSN_SIZE bytes, translated to host order.
|
||
The extracted fields are stored in FIELDS.
|
||
EX_INFO is used to handle reading variable length insns.
|
||
Return the length of the insn in bits, or 0 if no match,
|
||
or -1 if an error occurs fetching data (memory_error_func will have
|
||
been called). */
|
||
|
||
static int
|
||
extract_insn_normal (od, insn, ex_info, insn_value, fields, pc)
|
||
CGEN_OPCODE_DESC od;
|
||
const CGEN_INSN *insn;
|
||
CGEN_EXTRACT_INFO *ex_info;
|
||
CGEN_INSN_INT insn_value;
|
||
CGEN_FIELDS *fields;
|
||
bfd_vma pc;
|
||
{
|
||
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
||
const unsigned char *syn;
|
||
|
||
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
||
|
||
CGEN_INIT_EXTRACT (od);
|
||
|
||
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
||
{
|
||
int length;
|
||
|
||
if (CGEN_SYNTAX_CHAR_P (*syn))
|
||
continue;
|
||
|
||
length = i960_cgen_extract_operand (od, CGEN_SYNTAX_FIELD (*syn),
|
||
ex_info, insn_value, fields, pc);
|
||
if (length <= 0)
|
||
return length;
|
||
}
|
||
|
||
/* We recognized and successfully extracted this insn. */
|
||
return CGEN_INSN_BITSIZE (insn);
|
||
}
|
||
|
||
/* Default insn printer.
|
||
|
||
DIS_INFO is defined as `PTR' so the disassembler needn't know anything
|
||
about disassemble_info. */
|
||
|
||
static void
|
||
print_insn_normal (od, dis_info, insn, fields, pc, length)
|
||
CGEN_OPCODE_DESC od;
|
||
PTR dis_info;
|
||
const CGEN_INSN *insn;
|
||
CGEN_FIELDS *fields;
|
||
bfd_vma pc;
|
||
int length;
|
||
{
|
||
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
||
disassemble_info *info = (disassemble_info *) dis_info;
|
||
const unsigned char *syn;
|
||
|
||
CGEN_INIT_PRINT (od);
|
||
|
||
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
||
{
|
||
if (CGEN_SYNTAX_MNEMONIC_P (*syn))
|
||
{
|
||
(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
|
||
continue;
|
||
}
|
||
if (CGEN_SYNTAX_CHAR_P (*syn))
|
||
{
|
||
(*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
|
||
continue;
|
||
}
|
||
|
||
/* We have an operand. */
|
||
i960_cgen_print_operand (od, CGEN_SYNTAX_FIELD (*syn), info,
|
||
fields, CGEN_INSN_ATTRS (insn), pc, length);
|
||
}
|
||
}
|
||
|
||
/* Utility to print an insn.
|
||
BUF is the base part of the insn, target byte order, BUFLEN bytes long.
|
||
The result is the size of the insn in bytes or zero for an unknown insn
|
||
or -1 if an error occurs fetching data (memory_error_func will have
|
||
been called). */
|
||
|
||
static int
|
||
print_insn (od, pc, info, buf, buflen)
|
||
CGEN_OPCODE_DESC od;
|
||
bfd_vma pc;
|
||
disassemble_info *info;
|
||
char *buf;
|
||
int buflen;
|
||
{
|
||
unsigned long insn_value;
|
||
const CGEN_INSN_LIST *insn_list;
|
||
CGEN_EXTRACT_INFO ex_info;
|
||
|
||
ex_info.dis_info = info;
|
||
ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1;
|
||
ex_info.insn_bytes = buf;
|
||
|
||
switch (buflen)
|
||
{
|
||
case 1:
|
||
insn_value = buf[0];
|
||
break;
|
||
case 2:
|
||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
|
||
break;
|
||
case 4:
|
||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
|
||
/* The instructions are stored in hash lists.
|
||
Pick the first one and keep trying until we find the right one. */
|
||
|
||
insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value);
|
||
while (insn_list != NULL)
|
||
{
|
||
const CGEN_INSN *insn = insn_list->insn;
|
||
CGEN_FIELDS fields;
|
||
int length;
|
||
|
||
#if 0 /* not needed as insn shouldn't be in hash lists if not supported */
|
||
/* Supported by this cpu? */
|
||
if (! i960_cgen_insn_supported (od, insn))
|
||
continue;
|
||
#endif
|
||
|
||
/* Basic bit mask must be correct. */
|
||
/* ??? May wish to allow target to defer this check until the extract
|
||
handler. */
|
||
if ((insn_value & CGEN_INSN_BASE_MASK (insn))
|
||
== CGEN_INSN_BASE_VALUE (insn))
|
||
{
|
||
/* Printing is handled in two passes. The first pass parses the
|
||
machine insn and extracts the fields. The second pass prints
|
||
them. */
|
||
|
||
length = (*CGEN_EXTRACT_FN (insn)) (od, insn, &ex_info, insn_value,
|
||
&fields, pc);
|
||
/* length < 0 -> error */
|
||
if (length < 0)
|
||
return length;
|
||
if (length > 0)
|
||
{
|
||
(*CGEN_PRINT_FN (insn)) (od, info, insn, &fields, pc, length);
|
||
/* length is in bits, result is in bytes */
|
||
return length / 8;
|
||
}
|
||
}
|
||
|
||
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
/* Default value for CGEN_PRINT_INSN.
|
||
The result is the size of the insn in bytes or zero for an unknown insn
|
||
or -1 if an error occured fetching bytes. */
|
||
|
||
#ifndef CGEN_PRINT_INSN
|
||
#define CGEN_PRINT_INSN default_print_insn
|
||
#endif
|
||
|
||
static int
|
||
default_print_insn (od, pc, info)
|
||
CGEN_OPCODE_DESC od;
|
||
bfd_vma pc;
|
||
disassemble_info *info;
|
||
{
|
||
char buf[CGEN_MAX_INSN_SIZE];
|
||
int status;
|
||
|
||
/* Read the base part of the insn. */
|
||
|
||
status = (*info->read_memory_func) (pc, buf, CGEN_BASE_INSN_SIZE, info);
|
||
if (status != 0)
|
||
{
|
||
(*info->memory_error_func) (status, pc, info);
|
||
return -1;
|
||
}
|
||
|
||
return print_insn (od, pc, info, buf, CGEN_BASE_INSN_SIZE);
|
||
}
|
||
|
||
/* Main entry point.
|
||
Print one instruction from PC on INFO->STREAM.
|
||
Return the size of the instruction (in bytes). */
|
||
|
||
int
|
||
print_insn_i960 (pc, info)
|
||
bfd_vma pc;
|
||
disassemble_info *info;
|
||
{
|
||
int length;
|
||
static CGEN_OPCODE_DESC od = 0;
|
||
int mach = info->mach;
|
||
int big_p = info->endian == BFD_ENDIAN_BIG;
|
||
|
||
/* If we haven't initialized yet, initialize the opcode table. */
|
||
if (! od)
|
||
{
|
||
od = i960_cgen_opcode_open (mach,
|
||
big_p ?
|
||
CGEN_ENDIAN_BIG
|
||
: CGEN_ENDIAN_LITTLE);
|
||
i960_cgen_init_dis (od);
|
||
}
|
||
/* If we've switched cpu's, re-initialize. */
|
||
/* ??? Perhaps we should use BFD_ENDIAN. */
|
||
else if (mach != CGEN_OPCODE_MACH (od)
|
||
|| (CGEN_OPCODE_ENDIAN (od)
|
||
!= (big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE)))
|
||
{
|
||
cgen_set_cpu (od, mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
|
||
}
|
||
|
||
/* We try to have as much common code as possible.
|
||
But at this point some targets need to take over. */
|
||
/* ??? Some targets may need a hook elsewhere. Try to avoid this,
|
||
but if not possible try to move this hook elsewhere rather than
|
||
have two hooks. */
|
||
length = CGEN_PRINT_INSN (od, pc, info);
|
||
if (length > 0)
|
||
return length;
|
||
if (length < 0)
|
||
return -1;
|
||
|
||
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
|
||
return CGEN_DEFAULT_INSN_SIZE;
|
||
}
|