9c0c156bb7
The m32r port was using the device framework to handle two devices: the cache and uart registers. Both can be implemented in the newer hardware framework instead which allows us to drop the device logic entirely, as well as delete the tconfig.h file. While creating the new uart device model, I also added support for using stdin to read/write data rather than only supporting sockets. This has been lightly tested as there doesn't appear to be test coverage for the code already. If anyone still cares about this port, then they should (hopefully) file bug reports.
97 lines
2.5 KiB
C
97 lines
2.5 KiB
C
/* Handle cache related addresses.
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Copyright (C) 1996-2015 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions and Mike Frysinger.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "hw-main.h"
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#include "dv-m32r_cache.h"
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struct m32r_cache_hw
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{
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};
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static unsigned
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cris_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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SIM_DESC sd = hw_system (me);
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#if WITH_SCACHE
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/* MSPR support is deprecated but is kept in for upward compatibility
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with existing overlay support. */
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switch (addr)
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{
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case MSPR_ADDR:
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if ((*(const char *) source & MSPR_PURGE) != 0)
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scache_flush (sd);
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break;
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case MCCR_ADDR:
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if ((*(const char *) source & MCCR_CP) != 0)
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scache_flush (sd);
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break;
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}
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#endif
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return nr_bytes;
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}
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static void
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attach_regs (struct hw *me, struct m32r_cache_hw *hw)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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}
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static void
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m32r_cache_finish (struct hw *me)
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{
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struct m32r_cache_hw *hw;
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hw = HW_ZALLOC (me, struct m32r_cache_hw);
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set_hw_data (me, hw);
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set_hw_io_write_buffer (me, cris_io_write_buffer);
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attach_regs (me, hw);
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}
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const struct hw_descriptor dv_m32r_cache_descriptor[] = {
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{ "m32r_cache", m32r_cache_finish, },
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{ NULL },
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};
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