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817 lines
23 KiB
C
817 lines
23 KiB
C
/* Native-dependent code for GNU/Linux on MIPS processors.
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Copyright (C) 2001-2017 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "command.h"
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#include "gdbcmd.h"
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#include "inferior.h"
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#include "mips-tdep.h"
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#include "target.h"
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#include "regcache.h"
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#include "linux-nat.h"
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#include "mips-linux-tdep.h"
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#include "target-descriptions.h"
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#include "gdb_proc_service.h"
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#include "gregset.h"
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#include <sgidefs.h>
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#include "nat/gdb_ptrace.h"
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#include <asm/ptrace.h>
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#include "nat/mips-linux-watch.h"
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#include "features/mips-linux.c"
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#include "features/mips-dsp-linux.c"
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#include "features/mips64-linux.c"
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#include "features/mips64-dsp-linux.c"
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#ifndef PTRACE_GET_THREAD_AREA
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#define PTRACE_GET_THREAD_AREA 25
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#endif
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/* Assume that we have PTRACE_GETREGS et al. support. If we do not,
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we'll clear this and use PTRACE_PEEKUSER instead. */
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static int have_ptrace_regsets = 1;
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/* Saved function pointers to fetch and store a single register using
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PTRACE_PEEKUSER and PTRACE_POKEUSER. */
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static void (*super_fetch_registers) (struct target_ops *,
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struct regcache *, int);
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static void (*super_store_registers) (struct target_ops *,
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struct regcache *, int);
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static void (*super_close) (struct target_ops *);
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/* Map gdb internal register number to ptrace ``address''.
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These ``addresses'' are normally defined in <asm/ptrace.h>.
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ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
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and there's no point in reading or setting MIPS_ZERO_REGNUM.
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We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
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static CORE_ADDR
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mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
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{
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CORE_ADDR regaddr;
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if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
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error (_("Bogon register number %d."), regno);
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if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
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regaddr = regno;
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else if ((regno >= mips_regnum (gdbarch)->fp0)
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&& (regno < mips_regnum (gdbarch)->fp0 + 32))
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regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
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else if (regno == mips_regnum (gdbarch)->pc)
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regaddr = PC;
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else if (regno == mips_regnum (gdbarch)->cause)
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regaddr = store? (CORE_ADDR) -1 : CAUSE;
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else if (regno == mips_regnum (gdbarch)->badvaddr)
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regaddr = store? (CORE_ADDR) -1 : BADVADDR;
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else if (regno == mips_regnum (gdbarch)->lo)
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regaddr = MMLO;
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else if (regno == mips_regnum (gdbarch)->hi)
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regaddr = MMHI;
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else if (regno == mips_regnum (gdbarch)->fp_control_status)
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regaddr = FPC_CSR;
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else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
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regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
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else if (mips_regnum (gdbarch)->dspacc != -1
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&& regno >= mips_regnum (gdbarch)->dspacc
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&& regno < mips_regnum (gdbarch)->dspacc + 6)
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regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
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else if (regno == mips_regnum (gdbarch)->dspctl)
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regaddr = DSP_CONTROL;
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else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
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regaddr = 0;
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else
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regaddr = (CORE_ADDR) -1;
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return regaddr;
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}
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static CORE_ADDR
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mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
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{
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CORE_ADDR regaddr;
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if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
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error (_("Bogon register number %d."), regno);
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if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
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regaddr = regno;
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else if ((regno >= mips_regnum (gdbarch)->fp0)
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&& (regno < mips_regnum (gdbarch)->fp0 + 32))
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regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
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else if (regno == mips_regnum (gdbarch)->pc)
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regaddr = MIPS64_PC;
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else if (regno == mips_regnum (gdbarch)->cause)
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regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
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else if (regno == mips_regnum (gdbarch)->badvaddr)
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regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
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else if (regno == mips_regnum (gdbarch)->lo)
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regaddr = MIPS64_MMLO;
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else if (regno == mips_regnum (gdbarch)->hi)
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regaddr = MIPS64_MMHI;
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else if (regno == mips_regnum (gdbarch)->fp_control_status)
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regaddr = MIPS64_FPC_CSR;
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else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
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regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
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else if (mips_regnum (gdbarch)->dspacc != -1
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&& regno >= mips_regnum (gdbarch)->dspacc
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&& regno < mips_regnum (gdbarch)->dspacc + 6)
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regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
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else if (regno == mips_regnum (gdbarch)->dspctl)
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regaddr = DSP_CONTROL;
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else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
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regaddr = 0;
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else
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regaddr = (CORE_ADDR) -1;
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return regaddr;
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}
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/* Fetch the thread-local storage pointer for libthread_db. */
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ps_err_e
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ps_get_thread_area (struct ps_prochandle *ph,
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lwpid_t lwpid, int idx, void **base)
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{
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if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
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return PS_ERR;
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/* IDX is the bias from the thread pointer to the beginning of the
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thread descriptor. It has to be subtracted due to implementation
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quirks in libthread_db. */
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*base = (void *) ((char *)*base - idx);
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return PS_OK;
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}
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/* Wrapper functions. These are only used by libthread_db. */
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void
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supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
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{
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if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
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mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
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else
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mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
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}
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void
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fill_gregset (const struct regcache *regcache,
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gdb_gregset_t *gregsetp, int regno)
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{
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if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
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mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
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else
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mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
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}
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void
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supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
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{
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if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
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mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp);
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else
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mips64_supply_fpregset (regcache,
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(const mips64_elf_fpregset_t *) fpregsetp);
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}
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void
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fill_fpregset (const struct regcache *regcache,
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gdb_fpregset_t *fpregsetp, int regno)
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{
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if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
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mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno);
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else
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mips64_fill_fpregset (regcache,
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(mips64_elf_fpregset_t *) fpregsetp, regno);
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}
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/* Fetch REGNO (or all registers if REGNO == -1) from the target
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using PTRACE_GETREGS et al. */
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static void
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mips64_linux_regsets_fetch_registers (struct target_ops *ops,
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struct regcache *regcache, int regno)
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{
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struct gdbarch *gdbarch = get_regcache_arch (regcache);
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int is_fp, is_dsp;
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int have_dsp;
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int regi;
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int tid;
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if (regno >= mips_regnum (gdbarch)->fp0
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&& regno <= mips_regnum (gdbarch)->fp0 + 32)
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is_fp = 1;
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else if (regno == mips_regnum (gdbarch)->fp_control_status)
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is_fp = 1;
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else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
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is_fp = 1;
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else
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is_fp = 0;
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/* DSP registers are optional and not a part of any set. */
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have_dsp = mips_regnum (gdbarch)->dspctl != -1;
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if (!have_dsp)
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is_dsp = 0;
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else if (regno >= mips_regnum (gdbarch)->dspacc
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&& regno < mips_regnum (gdbarch)->dspacc + 6)
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is_dsp = 1;
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else if (regno == mips_regnum (gdbarch)->dspctl)
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is_dsp = 1;
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else
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is_dsp = 0;
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tid = ptid_get_lwp (inferior_ptid);
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if (tid == 0)
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tid = ptid_get_pid (inferior_ptid);
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if (regno == -1 || (!is_fp && !is_dsp))
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{
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mips64_elf_gregset_t regs;
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if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
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{
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if (errno == EIO)
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{
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have_ptrace_regsets = 0;
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return;
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}
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perror_with_name (_("Couldn't get registers"));
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}
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mips64_supply_gregset (regcache,
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(const mips64_elf_gregset_t *) ®s);
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}
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if (regno == -1 || is_fp)
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{
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mips64_elf_fpregset_t fp_regs;
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if (ptrace (PTRACE_GETFPREGS, tid, 0L,
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(PTRACE_TYPE_ARG3) &fp_regs) == -1)
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{
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if (errno == EIO)
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{
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have_ptrace_regsets = 0;
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return;
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}
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perror_with_name (_("Couldn't get FP registers"));
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}
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mips64_supply_fpregset (regcache,
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(const mips64_elf_fpregset_t *) &fp_regs);
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}
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if (is_dsp)
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super_fetch_registers (ops, regcache, regno);
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else if (regno == -1 && have_dsp)
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{
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for (regi = mips_regnum (gdbarch)->dspacc;
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regi < mips_regnum (gdbarch)->dspacc + 6;
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regi++)
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super_fetch_registers (ops, regcache, regi);
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super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
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}
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}
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/* Store REGNO (or all registers if REGNO == -1) to the target
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using PTRACE_SETREGS et al. */
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static void
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mips64_linux_regsets_store_registers (struct target_ops *ops,
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struct regcache *regcache, int regno)
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{
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struct gdbarch *gdbarch = get_regcache_arch (regcache);
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int is_fp, is_dsp;
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int have_dsp;
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int regi;
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int tid;
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if (regno >= mips_regnum (gdbarch)->fp0
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&& regno <= mips_regnum (gdbarch)->fp0 + 32)
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is_fp = 1;
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else if (regno == mips_regnum (gdbarch)->fp_control_status)
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is_fp = 1;
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else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
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is_fp = 1;
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else
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is_fp = 0;
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/* DSP registers are optional and not a part of any set. */
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have_dsp = mips_regnum (gdbarch)->dspctl != -1;
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if (!have_dsp)
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is_dsp = 0;
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else if (regno >= mips_regnum (gdbarch)->dspacc
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&& regno < mips_regnum (gdbarch)->dspacc + 6)
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is_dsp = 1;
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else if (regno == mips_regnum (gdbarch)->dspctl)
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is_dsp = 1;
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else
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is_dsp = 0;
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tid = ptid_get_lwp (inferior_ptid);
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if (tid == 0)
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tid = ptid_get_pid (inferior_ptid);
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if (regno == -1 || (!is_fp && !is_dsp))
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{
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mips64_elf_gregset_t regs;
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if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
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perror_with_name (_("Couldn't get registers"));
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mips64_fill_gregset (regcache, ®s, regno);
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if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1)
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perror_with_name (_("Couldn't set registers"));
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}
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if (regno == -1 || is_fp)
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{
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mips64_elf_fpregset_t fp_regs;
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if (ptrace (PTRACE_GETFPREGS, tid, 0L,
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(PTRACE_TYPE_ARG3) &fp_regs) == -1)
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perror_with_name (_("Couldn't get FP registers"));
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mips64_fill_fpregset (regcache, &fp_regs, regno);
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if (ptrace (PTRACE_SETFPREGS, tid, 0L,
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(PTRACE_TYPE_ARG3) &fp_regs) == -1)
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perror_with_name (_("Couldn't set FP registers"));
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}
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if (is_dsp)
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super_store_registers (ops, regcache, regno);
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else if (regno == -1 && have_dsp)
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{
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for (regi = mips_regnum (gdbarch)->dspacc;
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regi < mips_regnum (gdbarch)->dspacc + 6;
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regi++)
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super_store_registers (ops, regcache, regi);
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super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl);
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}
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}
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/* Fetch REGNO (or all registers if REGNO == -1) from the target
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using any working method. */
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static void
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mips64_linux_fetch_registers (struct target_ops *ops,
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struct regcache *regcache, int regnum)
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{
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/* Unless we already know that PTRACE_GETREGS does not work, try it. */
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if (have_ptrace_regsets)
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mips64_linux_regsets_fetch_registers (ops, regcache, regnum);
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/* If we know, or just found out, that PTRACE_GETREGS does not work, fall
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back to PTRACE_PEEKUSER. */
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if (!have_ptrace_regsets)
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super_fetch_registers (ops, regcache, regnum);
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}
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/* Store REGNO (or all registers if REGNO == -1) to the target
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using any working method. */
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static void
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mips64_linux_store_registers (struct target_ops *ops,
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struct regcache *regcache, int regnum)
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{
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/* Unless we already know that PTRACE_GETREGS does not work, try it. */
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if (have_ptrace_regsets)
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mips64_linux_regsets_store_registers (ops, regcache, regnum);
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/* If we know, or just found out, that PTRACE_GETREGS does not work, fall
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back to PTRACE_PEEKUSER. */
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if (!have_ptrace_regsets)
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super_store_registers (ops, regcache, regnum);
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}
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/* Return the address in the core dump or inferior of register
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REGNO. */
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static CORE_ADDR
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mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p)
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{
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if (mips_abi_regsize (gdbarch) == 8)
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return mips64_linux_register_addr (gdbarch, regno, store_p);
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else
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return mips_linux_register_addr (gdbarch, regno, store_p);
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}
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static const struct target_desc *
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mips_linux_read_description (struct target_ops *ops)
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{
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static int have_dsp = -1;
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if (have_dsp < 0)
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{
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int tid;
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tid = ptid_get_lwp (inferior_ptid);
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if (tid == 0)
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tid = ptid_get_pid (inferior_ptid);
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errno = 0;
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ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
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switch (errno)
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{
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case 0:
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have_dsp = 1;
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break;
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case EIO:
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have_dsp = 0;
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break;
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default:
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perror_with_name (_("Couldn't check DSP support"));
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break;
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}
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}
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/* Report that target registers are a size we know for sure
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that we can get from ptrace. */
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if (_MIPS_SIM == _ABIO32)
|
|
return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
|
|
else
|
|
return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
|
|
}
|
|
|
|
/* -1 if the kernel and/or CPU do not support watch registers.
|
|
1 if watch_readback is valid and we can read style, num_valid
|
|
and the masks.
|
|
0 if we need to read the watch_readback. */
|
|
|
|
static int watch_readback_valid;
|
|
|
|
/* Cached watch register read values. */
|
|
|
|
static struct pt_watch_regs watch_readback;
|
|
|
|
static struct mips_watchpoint *current_watches;
|
|
|
|
/* The current set of watch register values for writing the
|
|
registers. */
|
|
|
|
static struct pt_watch_regs watch_mirror;
|
|
|
|
static void
|
|
mips_show_dr (const char *func, CORE_ADDR addr,
|
|
int len, enum target_hw_bp_type type)
|
|
{
|
|
int i;
|
|
|
|
puts_unfiltered (func);
|
|
if (addr || len)
|
|
printf_unfiltered (" (addr=%s, len=%d, type=%s)",
|
|
paddress (target_gdbarch (), addr), len,
|
|
type == hw_write ? "data-write"
|
|
: (type == hw_read ? "data-read"
|
|
: (type == hw_access ? "data-read/write"
|
|
: (type == hw_execute ? "instruction-execute"
|
|
: "??unknown??"))));
|
|
puts_unfiltered (":\n");
|
|
|
|
for (i = 0; i < MAX_DEBUG_REGISTER; i++)
|
|
printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
|
|
paddress (target_gdbarch (),
|
|
mips_linux_watch_get_watchlo (&watch_mirror,
|
|
i)),
|
|
paddress (target_gdbarch (),
|
|
mips_linux_watch_get_watchhi (&watch_mirror,
|
|
i)));
|
|
}
|
|
|
|
/* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
|
|
handle the specified watch type. */
|
|
|
|
static int
|
|
mips_linux_can_use_hw_breakpoint (struct target_ops *self,
|
|
enum bptype type,
|
|
int cnt, int ot)
|
|
{
|
|
int i;
|
|
uint32_t wanted_mask, irw_mask;
|
|
|
|
if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
|
|
&watch_readback,
|
|
&watch_readback_valid, 0))
|
|
return 0;
|
|
|
|
switch (type)
|
|
{
|
|
case bp_hardware_watchpoint:
|
|
wanted_mask = W_MASK;
|
|
break;
|
|
case bp_read_watchpoint:
|
|
wanted_mask = R_MASK;
|
|
break;
|
|
case bp_access_watchpoint:
|
|
wanted_mask = R_MASK | W_MASK;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0;
|
|
i < mips_linux_watch_get_num_valid (&watch_readback) && cnt;
|
|
i++)
|
|
{
|
|
irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i);
|
|
if ((irw_mask & wanted_mask) == wanted_mask)
|
|
cnt--;
|
|
}
|
|
return (cnt == 0) ? 1 : 0;
|
|
}
|
|
|
|
/* Target to_stopped_by_watchpoint implementation. Return 1 if
|
|
stopped by watchpoint. The watchhi R and W bits indicate the watch
|
|
register triggered. */
|
|
|
|
static int
|
|
mips_linux_stopped_by_watchpoint (struct target_ops *ops)
|
|
{
|
|
int n;
|
|
int num_valid;
|
|
|
|
if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
|
|
&watch_readback,
|
|
&watch_readback_valid, 1))
|
|
return 0;
|
|
|
|
num_valid = mips_linux_watch_get_num_valid (&watch_readback);
|
|
|
|
for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
|
|
if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Target to_stopped_data_address implementation. Set the address
|
|
where the watch triggered (if known). Return 1 if the address was
|
|
known. */
|
|
|
|
static int
|
|
mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr)
|
|
{
|
|
/* On mips we don't know the low order 3 bits of the data address,
|
|
so we must return false. */
|
|
return 0;
|
|
}
|
|
|
|
/* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
|
|
the specified region can be covered by the watch registers. */
|
|
|
|
static int
|
|
mips_linux_region_ok_for_hw_watchpoint (struct target_ops *self,
|
|
CORE_ADDR addr, int len)
|
|
{
|
|
struct pt_watch_regs dummy_regs;
|
|
int i;
|
|
|
|
if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
|
|
&watch_readback,
|
|
&watch_readback_valid, 0))
|
|
return 0;
|
|
|
|
dummy_regs = watch_readback;
|
|
/* Clear them out. */
|
|
for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
|
|
mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
|
|
return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
|
|
}
|
|
|
|
/* Write the mirrored watch register values for each thread. */
|
|
|
|
static int
|
|
write_watchpoint_regs (void)
|
|
{
|
|
struct lwp_info *lp;
|
|
int tid;
|
|
|
|
ALL_LWPS (lp)
|
|
{
|
|
tid = ptid_get_lwp (lp->ptid);
|
|
if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
|
|
perror_with_name (_("Couldn't write debug register"));
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* linux_nat new_thread implementation. Write the mirrored watch
|
|
register values for the new thread. */
|
|
|
|
static void
|
|
mips_linux_new_thread (struct lwp_info *lp)
|
|
{
|
|
int tid;
|
|
|
|
if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
|
|
&watch_readback,
|
|
&watch_readback_valid, 0))
|
|
return;
|
|
|
|
tid = ptid_get_lwp (lp->ptid);
|
|
if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
|
|
perror_with_name (_("Couldn't write debug register"));
|
|
}
|
|
|
|
/* Target to_insert_watchpoint implementation. Try to insert a new
|
|
watch. Return zero on success. */
|
|
|
|
static int
|
|
mips_linux_insert_watchpoint (struct target_ops *self,
|
|
CORE_ADDR addr, int len,
|
|
enum target_hw_bp_type type,
|
|
struct expression *cond)
|
|
{
|
|
struct pt_watch_regs regs;
|
|
struct mips_watchpoint *new_watch;
|
|
struct mips_watchpoint **pw;
|
|
|
|
int i;
|
|
int retval;
|
|
|
|
if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
|
|
&watch_readback,
|
|
&watch_readback_valid, 0))
|
|
return -1;
|
|
|
|
if (len <= 0)
|
|
return -1;
|
|
|
|
regs = watch_readback;
|
|
/* Add the current watches. */
|
|
mips_linux_watch_populate_regs (current_watches, ®s);
|
|
|
|
/* Now try to add the new watch. */
|
|
if (!mips_linux_watch_try_one_watch (®s, addr, len,
|
|
mips_linux_watch_type_to_irw (type)))
|
|
return -1;
|
|
|
|
/* It fit. Stick it on the end of the list. */
|
|
new_watch = XNEW (struct mips_watchpoint);
|
|
new_watch->addr = addr;
|
|
new_watch->len = len;
|
|
new_watch->type = type;
|
|
new_watch->next = NULL;
|
|
|
|
pw = ¤t_watches;
|
|
while (*pw != NULL)
|
|
pw = &(*pw)->next;
|
|
*pw = new_watch;
|
|
|
|
watch_mirror = regs;
|
|
retval = write_watchpoint_regs ();
|
|
|
|
if (show_debug_regs)
|
|
mips_show_dr ("insert_watchpoint", addr, len, type);
|
|
|
|
return retval;
|
|
}
|
|
|
|
/* Target to_remove_watchpoint implementation. Try to remove a watch.
|
|
Return zero on success. */
|
|
|
|
static int
|
|
mips_linux_remove_watchpoint (struct target_ops *self,
|
|
CORE_ADDR addr, int len,
|
|
enum target_hw_bp_type type,
|
|
struct expression *cond)
|
|
{
|
|
int retval;
|
|
int deleted_one;
|
|
|
|
struct mips_watchpoint **pw;
|
|
struct mips_watchpoint *w;
|
|
|
|
/* Search for a known watch that matches. Then unlink and free
|
|
it. */
|
|
deleted_one = 0;
|
|
pw = ¤t_watches;
|
|
while ((w = *pw))
|
|
{
|
|
if (w->addr == addr && w->len == len && w->type == type)
|
|
{
|
|
*pw = w->next;
|
|
xfree (w);
|
|
deleted_one = 1;
|
|
break;
|
|
}
|
|
pw = &(w->next);
|
|
}
|
|
|
|
if (!deleted_one)
|
|
return -1; /* We don't know about it, fail doing nothing. */
|
|
|
|
/* At this point watch_readback is known to be valid because we
|
|
could not have added the watch without reading it. */
|
|
gdb_assert (watch_readback_valid == 1);
|
|
|
|
watch_mirror = watch_readback;
|
|
mips_linux_watch_populate_regs (current_watches, &watch_mirror);
|
|
|
|
retval = write_watchpoint_regs ();
|
|
|
|
if (show_debug_regs)
|
|
mips_show_dr ("remove_watchpoint", addr, len, type);
|
|
|
|
return retval;
|
|
}
|
|
|
|
/* Target to_close implementation. Free any watches and call the
|
|
super implementation. */
|
|
|
|
static void
|
|
mips_linux_close (struct target_ops *self)
|
|
{
|
|
struct mips_watchpoint *w;
|
|
struct mips_watchpoint *nw;
|
|
|
|
/* Clean out the current_watches list. */
|
|
w = current_watches;
|
|
while (w)
|
|
{
|
|
nw = w->next;
|
|
xfree (w);
|
|
w = nw;
|
|
}
|
|
current_watches = NULL;
|
|
|
|
if (super_close)
|
|
super_close (self);
|
|
}
|
|
|
|
void _initialize_mips_linux_nat (void);
|
|
|
|
void
|
|
_initialize_mips_linux_nat (void)
|
|
{
|
|
struct target_ops *t;
|
|
|
|
add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
|
|
&show_debug_regs, _("\
|
|
Set whether to show variables that mirror the mips debug registers."), _("\
|
|
Show whether to show variables that mirror the mips debug registers."), _("\
|
|
Use \"on\" to enable, \"off\" to disable.\n\
|
|
If enabled, the debug registers values are shown when GDB inserts\n\
|
|
or removes a hardware breakpoint or watchpoint, and when the inferior\n\
|
|
triggers a breakpoint or watchpoint."),
|
|
NULL,
|
|
NULL,
|
|
&maintenance_set_cmdlist,
|
|
&maintenance_show_cmdlist);
|
|
|
|
t = linux_trad_target (mips_linux_register_u_offset);
|
|
|
|
super_close = t->to_close;
|
|
t->to_close = mips_linux_close;
|
|
|
|
super_fetch_registers = t->to_fetch_registers;
|
|
super_store_registers = t->to_store_registers;
|
|
|
|
t->to_fetch_registers = mips64_linux_fetch_registers;
|
|
t->to_store_registers = mips64_linux_store_registers;
|
|
|
|
t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint;
|
|
t->to_remove_watchpoint = mips_linux_remove_watchpoint;
|
|
t->to_insert_watchpoint = mips_linux_insert_watchpoint;
|
|
t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint;
|
|
t->to_stopped_data_address = mips_linux_stopped_data_address;
|
|
t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint;
|
|
|
|
t->to_read_description = mips_linux_read_description;
|
|
|
|
linux_nat_add_target (t);
|
|
linux_nat_set_new_thread (t, mips_linux_new_thread);
|
|
|
|
/* Initialize the standard target descriptions. */
|
|
initialize_tdesc_mips_linux ();
|
|
initialize_tdesc_mips_dsp_linux ();
|
|
initialize_tdesc_mips64_linux ();
|
|
initialize_tdesc_mips64_dsp_linux ();
|
|
}
|