29 lines
819 B
Plaintext
29 lines
819 B
Plaintext
need to review ASTAT write behavior
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how to model RETE and IVG0 bit in IPEND ...
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model the loop buffer ? this means no ifetches because they're cached.
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see page 4-26 in Blackfin PRM under hardware loops.
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handle DSPID at 0xffe05000
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CEC should handle multiple exceptions at same address. would need
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exception processing to be delayed ? at least needs a stack for
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the CEC to pop things off.
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R0 = [SP++]; gets traced as R0 = [P6++];
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merge dv-bfin_evt with dv-bfin_cec since the EVT regs are part of the CEC
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fix single stepping over debug assert instructions in hardware
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exception in IVG5 causes double fault ?
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add a "file" option to the async banks to back it
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tests:
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- check AN bits with Dreg subtraction
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R0 = R1 - R2;
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- check astat bits with vector add/sub +|+
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- check acc with VIT_MAX and similiar insns
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