d0b04c6a38
* am29k-tdep.c: Update to latest code from AMD. (get_saved_register) don't crap out if no frame. * remote-udi.c: Set/clear inferior_pid as appropriate. (udi_open) call target_preopen, don't close fd 0!!!, clean up error handling. Fixup end-of-debugging messages. (udi_fetch_registers) clean up big time, mainly don't multiply register_valid indices by 4, and use proper Offset when reading gr96-gr127. (udi_store_registers) general cleanup. (fetch_register) cleanup, simplify. (regnum_to_srnum) INT_REGNUM->INTE_REGNUM. * tm-29k.h: Upgrade to latest code from AMD. * 29k-share/udi/udip2soc.c: Get rid of useless errmsg_m macro. (UDIConnect) Clean up error processing (like, don't do exit() if execlp fails), make code restartable, make more attractive. (UDIStop) Use SIGINT instead of SIGUSR1, as isstip won't stop otherwise.
303 lines
7.8 KiB
C
303 lines
7.8 KiB
C
/* Instruction printing code for the AMD 29000
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Copyright (C) 1990 Free Software Foundation, Inc.
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Contributed by Cygnus Support. Written by Jim Kingdon.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdio.h>
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#include "defs.h"
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#include "target.h"
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#include "opcode/a29k.h"
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/* Print a symbolic representation of a general-purpose
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register number NUM on STREAM.
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NUM is a number as found in the instruction, not as found in
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debugging symbols; it must be in the range 0-255. */
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static void
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print_general (num, stream)
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int num;
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FILE *stream;
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{
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if (num < 128)
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fprintf_filtered (stream, "gr%d", num);
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else
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fprintf_filtered (stream, "lr%d", num - 128);
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}
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/* Like print_general but a special-purpose register.
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The mnemonics used by the AMD assembler are not quite the same
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as the ones in the User's Manual. We use the ones that the
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assembler uses. */
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static void
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print_special (num, stream)
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int num;
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FILE *stream;
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{
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/* Register names of registers 0-SPEC0_NUM-1. */
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static char *spec0_names[] = {
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"vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
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"pc0", "pc1", "pc2", "mmu", "lru"
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};
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#define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0]))
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/* Register names of registers 128-128+SPEC128_NUM-1. */
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static char *spec128_names[] = {
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"ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
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};
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#define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0]))
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/* Register names of registers 160-160+SPEC160_NUM-1. */
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static char *spec160_names[] = {
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"fpe", "inte", "fps", "sr163", "exop"
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};
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#define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0]))
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if (num < SPEC0_NUM)
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fprintf_filtered (stream, spec0_names[num]);
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else if (num >= 128 && num < 128 + SPEC128_NUM)
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fprintf_filtered (stream, spec128_names[num-128]);
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else if (num >= 160 && num < 160 + SPEC160_NUM)
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fprintf_filtered (stream, spec160_names[num-160]);
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else
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fprintf_filtered (stream, "sr%d", num);
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}
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/* Is an instruction with OPCODE a delayed branch? */
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static int
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is_delayed_branch (opcode)
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int opcode;
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{
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return (opcode == 0xa8 || opcode == 0xa9 || opcode == 0xa0 || opcode == 0xa1
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|| opcode == 0xa4 || opcode == 0xa5
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|| opcode == 0xb4 || opcode == 0xb5
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|| opcode == 0xc4 || opcode == 0xc0
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|| opcode == 0xac || opcode == 0xad
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|| opcode == 0xcc);
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}
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/* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}.
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Note that the amd can be set up as either
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big or little-endian (the tm file says which) and we can't assume
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the host machine is the same. */
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static void
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find_bytes (insn, insn0, insn8, insn16, insn24)
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char *insn;
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unsigned char *insn0;
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unsigned char *insn8;
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unsigned char *insn16;
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unsigned char *insn24;
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{
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#if TARGET_BYTE_ORDER == BIG_ENDIAN
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*insn24 = insn[0];
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*insn16 = insn[1];
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*insn8 = insn[2];
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*insn0 = insn[3];
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#else /* Little-endian. */
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*insn24 = insn[3];
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*insn16 = insn[2];
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*insn8 = insn[1];
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*insn0 = insn[0];
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#endif /* Little-endian. */
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}
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/* Print one instruction from MEMADDR on STREAM.
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Return the size of the instruction (always 4 on am29k). */
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int
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print_insn (memaddr, stream)
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CORE_ADDR memaddr;
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FILE *stream;
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{
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/* The raw instruction. */
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char insn[4];
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/* The four bytes of the instruction. */
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unsigned char insn24, insn16, insn8, insn0;
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struct a29k_opcode *opcode;
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read_memory (memaddr, &insn[0], 4);
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find_bytes (insn, &insn0, &insn8, &insn16, &insn24);
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/* Handle the nop (aseq 0x40,gr1,gr1) specially */
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if ((insn24==0x70) && (insn16==0x40) && (insn8==0x01) && (insn0==0x01)) {
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fprintf_filtered (stream,"nop");
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return 4;
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}
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/* The opcode is always in insn24. */
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for (opcode = &a29k_opcodes[0];
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opcode < &a29k_opcodes[num_opcodes];
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++opcode)
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{
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if ((insn24<<24) == opcode->opcode)
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{
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char *s;
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fprintf_filtered (stream, "%s ", opcode->name);
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for (s = opcode->args; *s != '\0'; ++s)
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{
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switch (*s)
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{
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case 'a':
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print_general (insn8, stream);
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break;
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case 'b':
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print_general (insn0, stream);
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break;
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case 'c':
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print_general (insn16, stream);
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break;
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case 'i':
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fprintf_filtered (stream, "%d", insn0);
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break;
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case 'x':
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fprintf_filtered (stream, "%d", (insn16 << 8) + insn0);
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break;
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case 'h':
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fprintf_filtered (stream, "0x%x",
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(insn16 << 24) + (insn0 << 16));
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break;
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case 'X':
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fprintf_filtered (stream, "%d",
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((insn16 << 8) + insn0) | 0xffff0000);
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break;
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case 'P':
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/* This output looks just like absolute addressing, but
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maybe that's OK (it's what the GDB 68k and EBMON
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29k disassemblers do). */
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/* All the shifting is to sign-extend it. p*/
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print_address
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(memaddr +
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(((int)((insn16 << 10) + (insn0 << 2)) << 14) >> 14),
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stream);
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break;
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case 'A':
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print_address ((insn16 << 10) + (insn0 << 2), stream);
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break;
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case 'e':
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fprintf_filtered (stream, "%d", insn16 >> 7);
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break;
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case 'n':
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fprintf_filtered (stream, "0x%x", insn16 & 0x7f);
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break;
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case 'v':
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fprintf_filtered (stream, "0x%x", insn16);
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break;
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case 's':
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print_special (insn8, stream);
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break;
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case 'u':
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fprintf_filtered (stream, "%d", insn0 >> 7);
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break;
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case 'r':
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fprintf_filtered (stream, "%d", (insn0 >> 4) & 7);
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break;
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case 'd':
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fprintf_filtered (stream, "%d", (insn0 >> 2) & 3);
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break;
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case 'f':
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fprintf_filtered (stream, "%d", insn0 & 3);
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break;
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case 'F':
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fprintf_filtered (stream, "%d", (insn16 >> 2) & 15);
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break;
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case 'C':
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fprintf_filtered (stream, "%d", insn16 & 3);
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break;
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default:
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fprintf_filtered (stream, "%c", *s);
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}
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}
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/* Now we look for a const,consth pair of instructions,
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in which case we try to print the symbolic address. */
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if (insn24 == 2) /* consth */
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{
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int errcode;
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char prev_insn[4];
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unsigned char prev_insn0, prev_insn8, prev_insn16, prev_insn24;
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errcode = target_read_memory (memaddr - 4,
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&prev_insn[0],
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4);
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if (errcode == 0)
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{
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/* If it is a delayed branch, we need to look at the
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instruction before the delayed brach to handle
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things like
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const _foo
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call _printf
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consth _foo
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*/
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find_bytes (prev_insn, &prev_insn0, &prev_insn8,
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&prev_insn16, &prev_insn24);
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if (is_delayed_branch (prev_insn24))
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{
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errcode = target_read_memory
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(memaddr - 8, &prev_insn[0], 4);
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find_bytes (prev_insn, &prev_insn0, &prev_insn8,
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&prev_insn16, &prev_insn24);
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}
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}
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/* If there was a problem reading memory, then assume
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the previous instruction was not const. */
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if (errcode == 0)
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{
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/* Is it const to the same register? */
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if (prev_insn24 == 3
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&& prev_insn8 == insn8)
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{
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fprintf_filtered (stream, "\t; ");
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print_address (((insn16 << 24) + (insn0 << 16)
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+ (prev_insn16 << 8) + (prev_insn0)),
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stream);
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}
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}
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}
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return 4;
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}
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}
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fprintf_filtered (stream, ".word 0x%8x",
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(insn24 << 24) + (insn16 << 16) + (insn8 << 8) + insn0);
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return 4;
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}
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