289 lines
8.7 KiB
C
289 lines
8.7 KiB
C
/* d30v.h -- Header file for D30V opcode table
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Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010
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Free Software Foundation, Inc.
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Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version 3,
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or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING3. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef D30V_H
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#define D30V_H
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#define NOP 0x00F00000
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/* Structure to hold information about predefined registers. */
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struct pd_reg
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{
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char *name; /* name to recognize */
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char *pname; /* name to print for this register */
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int value;
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};
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extern const struct pd_reg pre_defined_registers[];
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int reg_name_cnt (void);
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/* the number of control registers */
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#define MAX_CONTROL_REG 64
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/* define the format specifiers */
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#define FM00 0
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#define FM01 0x80000000
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#define FM10 0x8000000000000000LL
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#define FM11 0x8000000080000000LL
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/* define the opcode classes */
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#define BRA 0
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#define LOGIC 1
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#define IMEM 2
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#define IALU1 4
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#define IALU2 5
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/* define the execution condition codes */
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#define ECC_AL 0 /* ALways (default) */
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#define ECC_TX 1 /* F0=True, F1=Don't care */
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#define ECC_FX 2 /* F0=False, F1=Don't care */
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#define ECC_XT 3 /* F0=Don't care, F1=True */
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#define ECC_XF 4 /* F0=Don't care, F1=False */
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#define ECC_TT 5 /* F0=True, F1=True */
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#define ECC_TF 6 /* F0=True, F1=False */
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#define ECC_RESERVED 7 /* reserved */
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#define ECC_MAX ECC_RESERVED
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extern const char *d30v_ecc_names[];
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/* condition code table for CMP and CMPU */
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extern const char *d30v_cc_names[];
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/* The opcode table is an array of struct d30v_opcode. */
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struct d30v_opcode
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{
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/* The opcode name. */
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const char *name;
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/* the opcode */
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int op1; /* first part, "IALU1" for example */
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int op2; /* the rest of the opcode */
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/* opcode format(s). These numbers correspond to entries */
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/* in the d30v_format_table */
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unsigned char format[4];
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#define SHORT_M 1
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#define SHORT_M2 5 /* for ld2w and st2w */
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#define SHORT_A 9
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#define SHORT_B1 11
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#define SHORT_B2 12
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#define SHORT_B2r 13
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#define SHORT_B3 14
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#define SHORT_B3r 16
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#define SHORT_B3b 18
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#define SHORT_B3br 20
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#define SHORT_D1r 22
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#define SHORT_D2 24
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#define SHORT_D2r 26
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#define SHORT_D2Br 28
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#define SHORT_U 30 /* unary SHORT_A. ABS for example */
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#define SHORT_F 31 /* SHORT_A with flag registers */
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#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */
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#define SHORT_T 35 /* for trap instruction */
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#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */
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#define SHORT_CMP 38 /* special form for CMPcc */
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#define SHORT_CMPU 40 /* special form for CMPUcc */
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#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */
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#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */
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#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */
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#define SHORT_MODINC 48
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#define SHORT_MODDEC 49
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#define SHORT_C1 50
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#define SHORT_C2 51
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#define SHORT_UF 52
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#define SHORT_A2 53
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#define SHORT_NONE 55 /* no operands */
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#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */
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#define LONG 57
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#define LONG_U 58 /* unary LONG */
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#define LONG_Ur 59 /* LONG pc-relative */
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#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */
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#define LONG_M 61 /* Memory long for ldb, stb */
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#define LONG_M2 62 /* Memory long for ld2w, st2w */
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#define LONG_2 63 /* LONG with 2 operands; jmptnz */
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#define LONG_2r 64 /* LONG with 2 operands; bratnz */
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#define LONG_2b 65 /* LONG_2 with modifier of 3 */
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#define LONG_2br 66 /* LONG_2r with modifier of 3 */
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#define LONG_D 67 /* for DJMPI */
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#define LONG_Dr 68 /* for DBRAI */
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#define LONG_Dbr 69 /* for repeati */
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/* the execution unit(s) used */
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int unit;
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#define EITHER 0
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#define IU 1
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#define MU 2
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#define EITHER_BUT_PREFER_MU 3
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/* this field is used to decide if two instructions */
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/* can be executed in parallel */
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long flags_used;
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long flags_set;
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#define FLAG_0 (1L<<0)
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#define FLAG_1 (1L<<1)
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#define FLAG_2 (1L<<2)
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#define FLAG_3 (1L<<3)
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#define FLAG_4 (1L<<4) /* S (saturation) */
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#define FLAG_5 (1L<<5) /* V (overflow) */
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#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */
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#define FLAG_7 (1L<<7) /* C (carry/borrow) */
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#define FLAG_SM (1L<<8) /* SM (stack mode) */
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#define FLAG_RP (1L<<9) /* RP (repeat enable) */
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#define FLAG_CONTROL (1L<<10) /* control registers */
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#define FLAG_A0 (1L<<11) /* A0 */
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#define FLAG_A1 (1L<<12) /* A1 */
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#define FLAG_JMP (1L<<13) /* instruction is a branch */
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#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */
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#define FLAG_MEM (1L<<15) /* reads/writes memory */
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#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation
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New meaning: operation cannot be
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combined in parallel with ADD/SUBppp. */
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#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */
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#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */
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#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */
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#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */
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#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */
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#define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7)
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#define FLAG_C FLAG_7
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#define FLAG_ALL (FLAG_0 | \
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FLAG_1 | \
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FLAG_2 | \
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FLAG_3 | \
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FLAG_4 | \
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FLAG_5 | \
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FLAG_6 | \
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FLAG_7 | \
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FLAG_SM | \
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FLAG_RP | \
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FLAG_CONTROL)
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int reloc_flag;
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#define RELOC_PCREL 1
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#define RELOC_ABS 2
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};
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extern const struct d30v_opcode d30v_opcode_table[];
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extern const int d30v_num_opcodes;
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/* The operands table is an array of struct d30v_operand. */
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struct d30v_operand
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{
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/* the length of the field */
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int length;
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/* The number of significant bits in the operand. */
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int bits;
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/* position relative to Ra */
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int position;
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/* syntax flags. */
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long flags;
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};
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extern const struct d30v_operand d30v_operand_table[];
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/* Values defined for the flags field of a struct d30v_operand. */
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/* this is the destination register; it will be modified */
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/* this is used by the optimizer */
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#define OPERAND_DEST (1)
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/* number or symbol */
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#define OPERAND_NUM (2)
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/* address or label */
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#define OPERAND_ADDR (4)
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/* register */
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#define OPERAND_REG (8)
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/* postincrement + */
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#define OPERAND_PLUS (0x10)
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/* postdecrement - */
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#define OPERAND_MINUS (0x20)
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/* signed number */
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#define OPERAND_SIGNED (0x40)
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/* this operand must be shifted left by 3 */
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#define OPERAND_SHIFT (0x80)
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/* flag register */
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#define OPERAND_FLAG (0x100)
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/* control register */
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#define OPERAND_CONTROL (0x200)
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/* accumulator */
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#define OPERAND_ACC (0x400)
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/* @ */
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#define OPERAND_ATSIGN (0x800)
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/* @( */
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#define OPERAND_ATPAR (0x1000)
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/* predecrement mode '@-sp' */
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#define OPERAND_ATMINUS (0x2000)
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/* this operand changes the instruction name */
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/* for example, CPMcc, CMPUcc */
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#define OPERAND_NAME (0x4000)
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/* fake operand for mvtsys and mvfsys */
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#define OPERAND_SPECIAL (0x8000)
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/* let the optimizer know that two registers are affected */
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#define OPERAND_2REG (0x10000)
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/* This operand is pc-relative. Note that repeati can have two immediate
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operands, one of which is pcrel, the other (the IMM6U one) is not. */
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#define OPERAND_PCREL (0x20000)
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/* The format table is an array of struct d30v_format. */
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struct d30v_format
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{
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int form; /* SHORT_A, LONG, etc */
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int modifier; /* two bit modifier following opcode */
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unsigned char operands[5];
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};
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extern const struct d30v_format d30v_format_table[];
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/* an instruction is defined by an opcode and a format */
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/* for example, "add" has one opcode, but three different */
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/* formats, 2 SHORT_A forms and a LONG form. */
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struct d30v_insn
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{
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struct d30v_opcode *op; /* pointer to an entry in the opcode table */
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struct d30v_format *form; /* pointer to an entry in the format table */
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int ecc; /* execution condition code */
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};
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/* an expressionS only has one register type, so we fake it */
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/* by setting high bits to indicate type */
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#define REGISTER_MASK 0xFF
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#endif /* D30V_H */
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