358 lines
14 KiB
Plaintext
358 lines
14 KiB
Plaintext
@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000
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@c Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node MIPS-Dependent
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@chapter MIPS Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter MIPS Dependent Features
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@end ifclear
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@cindex MIPS processor
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@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
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different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
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and MIPS64. For information about the @sc{mips} instruction set, see
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@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
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For an overview of @sc{mips} assembly conventions, see ``Appendix D:
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Assembly Language Programming'' in the same work.
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@menu
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* MIPS Opts:: Assembler options
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* MIPS Object:: ECOFF object code
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* MIPS Stabs:: Directives for debugging information
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* MIPS ISA:: Directives to override the ISA level
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* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
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* MIPS insn:: Directive to mark data as an instruction
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* MIPS option stack:: Directives to save and restore options
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* MIPS ASE instruction generation overrides:: Directives to control
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generation of MIPS ASE instructions
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@end menu
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@node MIPS Opts
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@section Assembler options
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The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
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special options:
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@table @code
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@cindex @code{-G} option (MIPS)
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@item -G @var{num}
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This option sets the largest size of an object that can be referenced
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implicitly with the @code{gp} register. It is only accepted for targets
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that use @sc{ecoff} format. The default value is 8.
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@cindex @code{-EB} option (MIPS)
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@cindex @code{-EL} option (MIPS)
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@cindex MIPS big-endian output
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@cindex MIPS little-endian output
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@cindex big-endian output, MIPS
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@cindex little-endian output, MIPS
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@item -EB
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@itemx -EL
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Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
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little-endian output at run time (unlike the other @sc{gnu} development
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tools, which must be configured for one or the other). Use @samp{-EB}
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to select big-endian output, and @samp{-EL} for little-endian.
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@cindex MIPS architecture options
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@item -mips1
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@itemx -mips2
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@itemx -mips3
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@itemx -mips4
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@itemx -mips5
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@itemx -mips32
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@itemx -mips64
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Generate code for a particular MIPS Instruction Set Architecture level.
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@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
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@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
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@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
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@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, and
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@samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, and
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@sc{MIPS64} ISA processors, respectively. You can also switch
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instruction sets during the assembly; see @ref{MIPS ISA, Directives to
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override the ISA level}.
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@item -mgp32
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@itemx -mfp32
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Some macros have different expansions for 32-bit and 64-bit registers.
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The register sizes are normally inferred from the ISA and ABI, but these
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flags force a certain group of registers to be treated as 32 bits wide at
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all times. @samp{-mgp32} controls the size of general-purpose registers
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and @samp{-mfp32} controls the size of floating-point registers.
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On some MIPS variants there is a 32-bit mode flag; when this flag is
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set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
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save the 32-bit registers on a context switch, so it is essential never
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to use the 64-bit registers.
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@item -mgp64
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Assume that 64-bit general purpose registers are available. This is
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provided in the interests of symmetry with -gp32.
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@item -mips16
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@itemx -no-mips16
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Generate code for the MIPS 16 processor. This is equivalent to putting
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@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
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turns off this option.
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@item -mips3d
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@itemx -no-mips3d
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Generate code for the MIPS-3D Application Specific Extension.
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This tells the assembler to accept MIPS-3D instructions.
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@samp{-no-mips3d} turns off this option.
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@item -mdmx
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@itemx -no-mdmx
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Generate code for the MDMX Application Specific Extension.
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This tells the assembler to accept MDMX instructions.
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@samp{-no-mdmx} turns off this option.
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@item -mfix7000
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@itemx -mno-fix7000
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Cause nops to be inserted if the read of the destination register
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of an mfhi or mflo instruction occurs in the following two instructions.
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@item -m4010
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@itemx -no-m4010
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Generate code for the LSI @sc{r4010} chip. This tells the assembler to
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accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
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etc.), and to not schedule @samp{nop} instructions around accesses to
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the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
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option.
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@item -m4650
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@itemx -no-m4650
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Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
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the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
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instructions around accesses to the @samp{HI} and @samp{LO} registers.
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@samp{-no-m4650} turns off this option.
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@itemx -m3900
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@itemx -no-m3900
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@itemx -m4100
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@itemx -no-m4100
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For each option @samp{-m@var{nnnn}}, generate code for the MIPS
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@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
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specific to that chip, and to schedule for that chip's hazards.
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@item -march=@var{cpu}
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Generate code for a particular MIPS cpu. It is exactly equivalent to
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@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
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understood. Valid @var{cpu} value are:
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@quotation
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2000,
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3000,
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3900,
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4000,
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4010,
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4100,
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4111,
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4300,
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4400,
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4600,
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4650,
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5000,
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rm5200,
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rm5230,
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rm5231,
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rm5261,
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rm5721,
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6000,
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rm7000,
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8000,
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10000,
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12000,
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mips32-4k,
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sb1
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@end quotation
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@item -mtune=@var{cpu}
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Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
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identical to @samp{-march=@var{cpu}}.
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@item -mabi=@var{abi}
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Record which ABI the source code uses. The recognized arguments
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are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
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@cindex @code{-nocpp} ignored (MIPS)
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@item -nocpp
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This option is ignored. It is accepted for command-line compatibility with
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other assemblers, which use it to turn off C style preprocessing. With
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@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
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@sc{gnu} assembler itself never runs the C preprocessor.
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@item --construct-floats
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@itemx --no-construct-floats
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@cindex --construct-floats
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@cindex --no-construct-floats
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The @code{--no-construct-floats} option disables the construction of
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double width floating point constants by loading the two halves of the
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value into the two single width floating point registers that make up
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the double width register. This feature is useful if the processor
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support the FR bit in its status register, and this bit is known (by
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the programmer) to be set. This bit prevents the aliasing of the double
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width register by the single width registers.
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By default @code{--construct-floats} is selected, allowing construction
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of these floating point constants.
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@item --trap
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@itemx --no-break
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@c FIXME! (1) reflect these options (next item too) in option summaries;
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@c (2) stop teasing, say _which_ instructions expanded _how_.
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@code{@value{AS}} automatically macro expands certain division and
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multiplication instructions to check for overflow and division by zero. This
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option causes @code{@value{AS}} to generate code to take a trap exception
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rather than a break exception when an error is detected. The trap instructions
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are only supported at Instruction Set Architecture level 2 and higher.
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@item --break
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@itemx --no-trap
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Generate code to take a break exception rather than a trap exception when an
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error is detected. This is the default.
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@item -n
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When this option is used, @code{@value{AS}} will issue a warning every
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time it generates a nop instruction from a macro.
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@end table
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@node MIPS Object
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@section MIPS ECOFF object code
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@cindex ECOFF sections
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@cindex MIPS ECOFF sections
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Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
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besides the usual @code{.text}, @code{.data} and @code{.bss}. The
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additional sections are @code{.rdata}, used for read-only data,
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@code{.sdata}, used for small data, and @code{.sbss}, used for small
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common objects.
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@cindex small objects, MIPS ECOFF
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@cindex @code{gp} register, MIPS
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When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
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register to form the address of a ``small object''. Any object in the
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@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
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For external objects, or for objects in the @code{.bss} section, you can use
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the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
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@code{$gp}; the default value is 8, meaning that a reference to any object
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eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
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@code{@value{AS}} prevents it from using the @code{$gp} register on the basis
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of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
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or @code{sbss} in any case). The size of an object in the @code{.bss} section
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is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
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size of an external object may be set with the @code{.extern} directive. For
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example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
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in length, whie leaving @code{sym} otherwise undefined.
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Using small @sc{ecoff} objects requires linker support, and assumes that the
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@code{$gp} register is correctly initialized (normally done automatically by
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the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
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@code{$gp} register.
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@node MIPS Stabs
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@section Directives for debugging information
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@cindex MIPS debugging directives
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@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
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generating debugging information which are not support by traditional @sc{mips}
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assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
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@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
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@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
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generated by the three @code{.stab} directives can only be read by @sc{gdb},
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not by traditional @sc{mips} debuggers (this enhancement is required to fully
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support C++ debugging). These directives are primarily used by compilers, not
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assembly language programmers!
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@node MIPS ISA
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@section Directives to override the ISA level
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@cindex MIPS ISA override
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@kindex @code{.set mips@var{n}}
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@sc{gnu} @code{@value{AS}} supports an additional directive to change
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the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
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mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64.
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The values 1 to 5, 32, and 64 make the assembler accept instructions
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for the corresponding @sc{isa} level, from that point on in the
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assembly. @code{.set mips@var{n}} affects not only which instructions
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are permitted, but also how certain macros are expanded. @code{.set
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mips0} restores the @sc{isa} level to its original level: either the
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level you selected with command line options, or the default for your
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configuration. You can use this feature to permit specific @sc{r4000}
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instructions while assembling in 32 bit mode. Use this directive with
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care!
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The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
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in which it will assemble instructions for the MIPS 16 processor. Use
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@samp{.set nomips16} to return to normal 32 bit mode.
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Traditional @sc{mips} assemblers do not support this directive.
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@node MIPS autoextend
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@section Directives for extending MIPS 16 bit instructions
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@kindex @code{.set autoextend}
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@kindex @code{.set noautoextend}
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By default, MIPS 16 instructions are automatically extended to 32 bits
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when necessary. The directive @samp{.set noautoextend} will turn this
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off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
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must be explicitly extended with the @samp{.e} modifier (e.g.,
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@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
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to once again automatically extend instructions when necessary.
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This directive is only meaningful when in MIPS 16 mode. Traditional
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@sc{mips} assemblers do not support this directive.
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@node MIPS insn
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@section Directive to mark data as an instruction
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@kindex @code{.insn}
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The @code{.insn} directive tells @code{@value{AS}} that the following
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data is actually instructions. This makes a difference in MIPS 16 mode:
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when loading the address of a label which precedes instructions,
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@code{@value{AS}} automatically adds 1 to the value, so that jumping to
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the loaded address will do the right thing.
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@node MIPS option stack
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@section Directives to save and restore options
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@cindex MIPS option stack
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@kindex @code{.set push}
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@kindex @code{.set pop}
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The directives @code{.set push} and @code{.set pop} may be used to save
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and restore the current settings for all the options which are
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controlled by @code{.set}. The @code{.set push} directive saves the
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current settings on a stack. The @code{.set pop} directive pops the
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stack and restores the settings.
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These directives can be useful inside an macro which must change an
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option such as the ISA level or instruction reordering but does not want
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to change the state of the code which invoked the macro.
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Traditional @sc{mips} assemblers do not support these directives.
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@node MIPS ASE instruction generation overrides
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@section Directives to control generation of MIPS ASE instructions
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@cindex MIPS MIPS-3D instruction generation override
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@kindex @code{.set mips3d}
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@kindex @code{.set nomips3d}
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The directive @code{.set mips3d} makes the assembler accept instructions
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from the MIPS-3D Application Specific Extension from that point on
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in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
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instructions from being accepted.
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@cindex MIPS MDMX instruction generation override
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@kindex @code{.set mdmx}
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@kindex @code{.set nomdmx}
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The directive @code{.set mdmx} makes the assembler accept instructions
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from the MDMX Application Specific Extension from that point on
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in the assembly. The @code{.set nomdmx} directive prevents MDMX
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instructions from being accepted.
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Traditional @sc{mips} assemblers do not support these directives.
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