419 lines
12 KiB
Plaintext
419 lines
12 KiB
Plaintext
@c Copyright (C) 2002-2016 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node MSP430-Dependent
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@chapter MSP 430 Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter MSP 430 Dependent Features
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@end ifclear
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@cindex MSP 430 support
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@cindex 430 support
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@menu
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* MSP430 Options:: Options
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* MSP430 Syntax:: Syntax
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* MSP430 Floating Point:: Floating Point
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* MSP430 Directives:: MSP 430 Machine Directives
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* MSP430 Opcodes:: Opcodes
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* MSP430 Profiling Capability:: Profiling Capability
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@end menu
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@node MSP430 Options
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@section Options
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@cindex MSP 430 options (none)
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@cindex options for MSP430 (none)
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@table @code
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@item -mmcu
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selects the mcu architecture. If the architecture is 430Xv2 then this
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also enables NOP generation unless the @option{-mN} is also specified.
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@item -mcpu
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selects the cpu architecture. If the architecture is 430Xv2 then this
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also enables NOP generation unless the @option{-mN} is also specified.
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@item -msilicon-errata=@var{name}[,@var{name}@dots{}]
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Implements a fixup for named silicon errata. Multiple silicon errata
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can be specified by multiple uses of the @option{-msilicon-errata}
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option and/or by including the errata names, separated by commas, on
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an individual @option{-msilicon-errata} option. Errata names
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currently recognised by the assembler are:
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@table @code
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@item cpu4
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@code{PUSH #4} and @option{PUSH #8} need longer encodings on the
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MSP430. This option is enabled by default, and cannot be disabled.
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@item cpu8
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Do not set the @code{SP} to an odd value.
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@item cpu11
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Do not update the @code{SR} and the @code{PC} in the same instruction.
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@item cpu12
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Do not use the @code{PC} in a @code{CMP} or @code{BIT} instruction.
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@item cpu13
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Do not use an arithmetic instruction to modify the @code{SR}.
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@item cpu19
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Insert @code{NOP} after @code{CPUOFF}.
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@end table
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@item -msilicon-errata-warn=@var{name}[,@var{name}@dots{}]
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Like the @option{-msilicon-errata} option except that instead of
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fixing the specified errata, a warning message is issued instead.
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This option can be used alongside @option{-msilicon-errata} to
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generate messages whenever a problem is fixed, or on its own in order
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to inspect code for potential problems.
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@item -mP
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enables polymorph instructions handler.
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@item -mQ
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enables relaxation at assembly time. DANGEROUS!
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@item -ml
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indicates that the input uses the large code model.
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@item -mn
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enables the generation of a NOP instruction following any instruction
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that might change the interrupts enabled/disabled state. The
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pipelined nature of the MSP430 core means that any instruction that
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changes the interrupt state (@code{EINT}, @code{DINT}, @code{BIC #8,
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SR}, @code{BIS #8, SR} or @code{MOV.W <>, SR}) must be
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followed by a NOP instruction in order to ensure the correct
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processing of interrupts. By default it is up to the programmer to
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supply these NOP instructions, but this command line option enables
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the automatic insertion by the assembler, if they are missing.
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@item -mN
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disables the generation of a NOP instruction following any instruction
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that might change the interrupts enabled/disabled state. This is the
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default behaviour.
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@item -my
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tells the assembler to generate a warning message if a NOP does not
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immediately forllow an instruction that enables or disables
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interrupts. This is the default.
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Note that this option can be stacked with the @option{-mn} option so
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that the assembler will both warn about missing NOP instructions and
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then insert them automatically.
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@item -mY
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disables warnings about missing NOP instructions.
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@item -md
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mark the object file as one that requires data to copied from ROM to
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RAM at execution startup. Disabled by default.
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@end table
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@node MSP430 Syntax
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@section Syntax
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@menu
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* MSP430-Macros:: Macros
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* MSP430-Chars:: Special Characters
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* MSP430-Regs:: Register Names
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* MSP430-Ext:: Assembler Extensions
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@end menu
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@node MSP430-Macros
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@subsection Macros
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@cindex Macros, MSP 430
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@cindex MSP 430 macros
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The macro syntax used on the MSP 430 is like that described in the MSP
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430 Family Assembler Specification. Normal @code{@value{AS}}
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macros should still work.
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Additional built-in macros are:
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@table @code
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@item llo(exp)
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Extracts least significant word from 32-bit expression 'exp'.
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@item lhi(exp)
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Extracts most significant word from 32-bit expression 'exp'.
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@item hlo(exp)
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Extracts 3rd word from 64-bit expression 'exp'.
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@item hhi(exp)
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Extracts 4rd word from 64-bit expression 'exp'.
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@end table
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They normally being used as an immediate source operand.
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@smallexample
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mov #llo(1), r10 ; == mov #1, r10
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mov #lhi(1), r10 ; == mov #0, r10
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@end smallexample
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@node MSP430-Chars
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@subsection Special Characters
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@cindex line comment character, MSP 430
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@cindex MSP 430 line comment character
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A semicolon (@samp{;}) appearing anywhere on a line starts a comment
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that extends to the end of that line.
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If a @samp{#} appears as the first character of a line then the whole
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line is treated as a comment, but it can also be a logical line number
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directive (@pxref{Comments}) or a preprocessor control command
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(@pxref{Preprocessing}).
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@cindex line separator, MSP 430
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@cindex statement separator, MSP 430
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@cindex MSP 430 line separator
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Multiple statements can appear on the same line provided that they are
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separated by the @samp{@{} character.
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@cindex identifiers, MSP 430
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@cindex MSP 430 identifiers
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The character @samp{$} in jump instructions indicates current location and
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implemented only for TI syntax compatibility.
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@node MSP430-Regs
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@subsection Register Names
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@cindex MSP 430 register names
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@cindex register names, MSP 430
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General-purpose registers are represented by predefined symbols of the
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form @samp{r@var{N}} (for global registers), where @var{N} represents
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a number between @code{0} and @code{15}. The leading
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letters may be in either upper or lower case; for example, @samp{r13}
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and @samp{R7} are both valid register names.
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@cindex special purpose registers, MSP 430
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Register names @samp{PC}, @samp{SP} and @samp{SR} cannot be used as register names
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and will be treated as variables. Use @samp{r0}, @samp{r1}, and @samp{r2} instead.
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@node MSP430-Ext
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@subsection Assembler Extensions
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@cindex MSP430 Assembler Extensions
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@table @code
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@item @@rN
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As destination operand being treated as @samp{0(rn)}
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@item 0(rN)
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As source operand being treated as @samp{@@rn}
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@item jCOND +N
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Skips next N bytes followed by jump instruction and equivalent to
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@samp{jCOND $+N+2}
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@end table
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Also, there are some instructions, which cannot be found in other assemblers.
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These are branch instructions, which has different opcodes upon jump distance.
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They all got PC relative addressing mode.
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@table @code
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@item beq label
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A polymorph instruction which is @samp{jeq label} in case if jump distance
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within allowed range for cpu's jump instruction. If not, this unrolls into
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a sequence of
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@smallexample
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jne $+6
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br label
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@end smallexample
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@item bne label
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A polymorph instruction which is @samp{jne label} or @samp{jeq +4; br label}
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@item blt label
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A polymorph instruction which is @samp{jl label} or @samp{jge +4; br label}
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@item bltn label
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A polymorph instruction which is @samp{jn label} or @samp{jn +2; jmp +4; br label}
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@item bltu label
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A polymorph instruction which is @samp{jlo label} or @samp{jhs +2; br label}
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@item bge label
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A polymorph instruction which is @samp{jge label} or @samp{jl +4; br label}
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@item bgeu label
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A polymorph instruction which is @samp{jhs label} or @samp{jlo +4; br label}
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@item bgt label
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A polymorph instruction which is @samp{jeq +2; jge label} or @samp{jeq +6; jl +4; br label}
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@item bgtu label
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A polymorph instruction which is @samp{jeq +2; jhs label} or @samp{jeq +6; jlo +4; br label}
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@item bleu label
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A polymorph instruction which is @samp{jeq label; jlo label} or @samp{jeq +2; jhs +4; br label}
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@item ble label
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A polymorph instruction which is @samp{jeq label; jl label} or @samp{jeq +2; jge +4; br label}
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@item jump label
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A polymorph instruction which is @samp{jmp label} or @samp{br label}
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@end table
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@node MSP430 Floating Point
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@section Floating Point
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@cindex floating point, MSP 430 (@sc{ieee})
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@cindex MSP 430 floating point (@sc{ieee})
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The MSP 430 family uses @sc{ieee} 32-bit floating-point numbers.
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@node MSP430 Directives
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@section MSP 430 Machine Directives
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@cindex machine directives, MSP 430
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@cindex MSP 430 machine directives
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@table @code
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@cindex @code{file} directive, MSP 430
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@item .file
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This directive is ignored; it is accepted for compatibility with other
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MSP 430 assemblers.
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@quotation
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@emph{Warning:} in other versions of the @sc{gnu} assembler, @code{.file} is
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used for the directive called @code{.app-file} in the MSP 430 support.
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@end quotation
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@cindex @code{line} directive, MSP 430
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@item .line
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This directive is ignored; it is accepted for compatibility with other
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MSP 430 assemblers.
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@cindex @code{arch} directive, MSP 430
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@item .arch
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Sets the target microcontroller in the same way as the @option{-mmcu}
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command line option.
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@cindex @code{cpu} directive, MSP 430
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@item .cpu
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Sets the target architecture in the same way as the @option{-mcpu}
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command line option.
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@cindex @code{profiler} directive, MSP 430
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@item .profiler
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This directive instructs assembler to add new profile entry to the object file.
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@cindex @code{refsym} directive, MSP 430
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@item .refsym
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This directive instructs assembler to add an undefined reference to
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the symbol following the directive. The maximum symbol name length is
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1023 characters. No relocation is created for this symbol; it will
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exist purely for pulling in object files from archives. Note that
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this reloc is not sufficient to prevent garbage collection; use a
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KEEP() directive in the linker file to preserve such objects.
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@end table
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@node MSP430 Opcodes
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@section Opcodes
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@cindex MSP 430 opcodes
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@cindex opcodes for MSP 430
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@code{@value{AS}} implements all the standard MSP 430 opcodes. No
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additional pseudo-instructions are needed on this family.
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For information on the 430 machine instruction set, see @cite{MSP430
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User's Manual, document slau049d}, Texas Instrument, Inc.
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@node MSP430 Profiling Capability
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@section Profiling Capability
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@cindex MSP 430 profiling capability
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@cindex profiling capability for MSP 430
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It is a performance hit to use gcc's profiling approach for this tiny target.
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Even more -- jtag hardware facility does not perform any profiling functions.
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However we've got gdb's built-in simulator where we can do anything.
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We define new section @samp{.profiler} which holds all profiling information.
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We define new pseudo operation @samp{.profiler} which will instruct assembler to
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add new profile entry to the object file. Profile should take place at the
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present address.
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Pseudo operation format:
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@samp{.profiler flags,function_to_profile [, cycle_corrector, extra]}
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where:
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@table @code
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@table @code
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@samp{flags} is a combination of the following characters:
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@item s
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function entry
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@item x
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function exit
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@item i
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function is in init section
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@item f
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function is in fini section
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@item l
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library call
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@item c
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libc standard call
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@item d
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stack value demand
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@item I
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interrupt service routine
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@item P
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prologue start
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@item p
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prologue end
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@item E
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epilogue start
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@item e
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epilogue end
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@item j
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long jump / sjlj unwind
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@item a
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an arbitrary code fragment
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@item t
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extra parameter saved (a constant value like frame size)
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@end table
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@item function_to_profile
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a function address
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@item cycle_corrector
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a value which should be added to the cycle counter, zero if omitted.
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@item extra
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any extra parameter, zero if omitted.
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@end table
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For example:
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@smallexample
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.global fxx
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.type fxx,@@function
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fxx:
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.LFrameOffset_fxx=0x08
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.profiler "scdP", fxx ; function entry.
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; we also demand stack value to be saved
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push r11
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push r10
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push r9
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push r8
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.profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point
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; (this is a prologue end)
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; note, that spare var filled with
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; the farme size
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mov r15,r8
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...
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.profiler cdE,fxx ; check stack
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pop r8
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pop r9
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pop r10
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pop r11
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.profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
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ret ; cause 'ret' insn takes 3 cycles
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@end smallexample
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