1206 lines
34 KiB
C
1206 lines
34 KiB
C
/* Instruction building/extraction support for m32r. -*- C -*-
|
||
|
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THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
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- the resultant file is machine generated, cgen-ibld.in isn't
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Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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Keep that in mind. */
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#include "sysdep.h"
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#include <ctype.h>
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#include <stdio.h>
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#include "ansidecl.h"
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#include "dis-asm.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "m32r-desc.h"
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#include "m32r-opc.h"
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#include "opintl.h"
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#undef min
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#define min(a,b) ((a) < (b) ? (a) : (b))
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#undef max
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#define max(a,b) ((a) > (b) ? (a) : (b))
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/* Used by the ifield rtx function. */
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#define FLD(f) (fields->f)
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static const char * insert_normal
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PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
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static const char * insert_insn_normal
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PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
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CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
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static int extract_normal
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PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
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unsigned int, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, bfd_vma, long *));
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static int extract_insn_normal
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PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
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CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
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/* Operand insertion. */
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#if ! CGEN_INT_INSN_P
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/* Subroutine of insert_normal. */
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static CGEN_INLINE void
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insert_1 (cd, value, start, length, word_length, bufp)
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CGEN_CPU_DESC cd;
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unsigned long value;
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int start,length,word_length;
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unsigned char *bufp;
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{
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unsigned long x,mask;
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int shift;
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int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
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switch (word_length)
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{
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case 8:
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x = *bufp;
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break;
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case 16:
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if (big_p)
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x = bfd_getb16 (bufp);
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else
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x = bfd_getl16 (bufp);
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break;
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case 24:
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/* ??? This may need reworking as these cases don't necessarily
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want the first byte and the last two bytes handled like this. */
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if (big_p)
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x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
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else
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x = bfd_getl16 (bufp) | (bufp[2] << 16);
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break;
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case 32:
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if (big_p)
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x = bfd_getb32 (bufp);
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else
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x = bfd_getl32 (bufp);
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break;
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default :
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abort ();
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}
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/* Written this way to avoid undefined behaviour. */
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mask = (((1L << (length - 1)) - 1) << 1) | 1;
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if (CGEN_INSN_LSB0_P)
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shift = (start + 1) - length;
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else
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shift = (word_length - (start + length));
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x = (x & ~(mask << shift)) | ((value & mask) << shift);
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switch (word_length)
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{
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case 8:
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*bufp = x;
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break;
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case 16:
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if (big_p)
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bfd_putb16 (x, bufp);
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else
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bfd_putl16 (x, bufp);
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break;
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case 24:
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/* ??? This may need reworking as these cases don't necessarily
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want the first byte and the last two bytes handled like this. */
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if (big_p)
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{
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bufp[0] = x >> 16;
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bfd_putb16 (x, bufp + 1);
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}
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else
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{
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bfd_putl16 (x, bufp);
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bufp[2] = x >> 16;
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}
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break;
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case 32:
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if (big_p)
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bfd_putb32 (x, bufp);
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else
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bfd_putl32 (x, bufp);
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break;
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default :
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abort ();
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}
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}
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#endif /* ! CGEN_INT_INSN_P */
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/* Default insertion routine.
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ATTRS is a mask of the boolean attributes.
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WORD_OFFSET is the offset in bits from the start of the insn of the value.
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WORD_LENGTH is the length of the word in bits in which the value resides.
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START is the starting bit number in the word, architecture origin.
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LENGTH is the length of VALUE in bits.
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TOTAL_LENGTH is the total length of the insn in bits.
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The result is an error message or NULL if success. */
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/* ??? This duplicates functionality with bfd's howto table and
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bfd_install_relocation. */
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/* ??? This doesn't handle bfd_vma's. Create another function when
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necessary. */
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static const char *
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insert_normal (cd, value, attrs, word_offset, start, length, word_length,
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total_length, buffer)
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CGEN_CPU_DESC cd;
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long value;
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unsigned int attrs;
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unsigned int word_offset, start, length, word_length, total_length;
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CGEN_INSN_BYTES_PTR buffer;
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{
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static char errbuf[100];
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/* Written this way to avoid undefined behaviour. */
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unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
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/* If LENGTH is zero, this operand doesn't contribute to the value. */
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if (length == 0)
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return NULL;
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if (CGEN_INT_INSN_P
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&& word_offset != 0)
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abort ();
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if (word_length > 32)
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abort ();
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/* For architectures with insns smaller than the base-insn-bitsize,
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word_length may be too big. */
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if (cd->min_insn_bitsize < cd->base_insn_bitsize)
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{
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if (word_offset == 0
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&& word_length > total_length)
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word_length = total_length;
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}
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/* Ensure VALUE will fit. */
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if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
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{
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unsigned long maxval = mask;
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if ((unsigned long) value > maxval)
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{
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/* xgettext:c-format */
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sprintf (errbuf,
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_("operand out of range (%lu not between 0 and %lu)"),
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value, maxval);
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return errbuf;
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}
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}
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else
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{
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if (! cgen_signed_overflow_ok_p (cd))
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{
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long minval = - (1L << (length - 1));
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long maxval = (1L << (length - 1)) - 1;
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if (value < minval || value > maxval)
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{
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sprintf
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/* xgettext:c-format */
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(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
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value, minval, maxval);
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return errbuf;
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||
}
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||
}
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||
}
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#if CGEN_INT_INSN_P
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{
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int shift;
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if (CGEN_INSN_LSB0_P)
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shift = (start + 1) - length;
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else
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shift = word_length - (start + length);
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*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
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}
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#else /* ! CGEN_INT_INSN_P */
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{
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unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
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insert_1 (cd, value, start, length, word_length, bufp);
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}
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#endif /* ! CGEN_INT_INSN_P */
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return NULL;
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}
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/* Default insn builder (insert handler).
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The instruction is recorded in CGEN_INT_INSN_P byte order
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(meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is
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recorded in host byte order, otherwise BUFFER is an array of bytes and the
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value is recorded in target byte order).
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The result is an error message or NULL if success. */
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static const char *
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insert_insn_normal (cd, insn, fields, buffer, pc)
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CGEN_CPU_DESC cd;
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const CGEN_INSN * insn;
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CGEN_FIELDS * fields;
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CGEN_INSN_BYTES_PTR buffer;
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bfd_vma pc;
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{
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const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
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unsigned long value;
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const unsigned char * syn;
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CGEN_INIT_INSERT (cd);
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value = CGEN_INSN_BASE_VALUE (insn);
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/* If we're recording insns as numbers (rather than a string of bytes),
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||
target byte order handling is deferred until later. */
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||
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#if CGEN_INT_INSN_P
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*buffer = value;
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#else
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cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
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CGEN_FIELDS_BITSIZE (fields)),
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value);
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#endif /* ! CGEN_INT_INSN_P */
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/* ??? It would be better to scan the format's fields.
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Still need to be able to insert a value based on the operand though;
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e.g. storing a branch displacement that got resolved later.
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Needs more thought first. */
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for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn)
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{
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const char *errmsg;
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if (CGEN_SYNTAX_CHAR_P (* syn))
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continue;
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errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
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fields, buffer, pc);
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if (errmsg)
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return errmsg;
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}
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return NULL;
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}
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/* Operand extraction. */
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#if ! CGEN_INT_INSN_P
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/* Subroutine of extract_normal.
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Ensure sufficient bytes are cached in EX_INFO.
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OFFSET is the offset in bytes from the start of the insn of the value.
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BYTES is the length of the needed value.
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Returns 1 for success, 0 for failure. */
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static CGEN_INLINE int
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fill_cache (cd, ex_info, offset, bytes, pc)
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CGEN_CPU_DESC cd;
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||
CGEN_EXTRACT_INFO *ex_info;
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int offset, bytes;
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||
bfd_vma pc;
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{
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||
/* It's doubtful that the middle part has already been fetched so
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||
we don't optimize that case. kiss. */
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||
int mask;
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disassemble_info *info = (disassemble_info *) ex_info->dis_info;
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||
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/* First do a quick check. */
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mask = (1 << bytes) - 1;
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if (((ex_info->valid >> offset) & mask) == mask)
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return 1;
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||
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/* Search for the first byte we need to read. */
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for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
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if (! (mask & ex_info->valid))
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break;
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if (bytes)
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{
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||
int status;
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pc += offset;
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status = (*info->read_memory_func)
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(pc, ex_info->insn_bytes + offset, bytes, info);
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||
|
||
if (status != 0)
|
||
{
|
||
(*info->memory_error_func) (status, pc, info);
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||
return 0;
|
||
}
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||
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||
ex_info->valid |= ((1 << bytes) - 1) << offset;
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||
}
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||
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return 1;
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||
}
|
||
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||
/* Subroutine of extract_normal. */
|
||
|
||
static CGEN_INLINE long
|
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extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
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||
CGEN_CPU_DESC cd;
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||
CGEN_EXTRACT_INFO *ex_info;
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||
int start,length,word_length;
|
||
unsigned char *bufp;
|
||
bfd_vma pc;
|
||
{
|
||
unsigned long x,mask;
|
||
int shift;
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||
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
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||
|
||
switch (word_length)
|
||
{
|
||
case 8:
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||
x = *bufp;
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||
break;
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||
case 16:
|
||
if (big_p)
|
||
x = bfd_getb16 (bufp);
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||
else
|
||
x = bfd_getl16 (bufp);
|
||
break;
|
||
case 24:
|
||
/* ??? This may need reworking as these cases don't necessarily
|
||
want the first byte and the last two bytes handled like this. */
|
||
if (big_p)
|
||
x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
|
||
else
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||
x = bfd_getl16 (bufp) | (bufp[2] << 16);
|
||
break;
|
||
case 32:
|
||
if (big_p)
|
||
x = bfd_getb32 (bufp);
|
||
else
|
||
x = bfd_getl32 (bufp);
|
||
break;
|
||
default :
|
||
abort ();
|
||
}
|
||
|
||
/* Written this way to avoid undefined behaviour. */
|
||
mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
||
if (CGEN_INSN_LSB0_P)
|
||
shift = (start + 1) - length;
|
||
else
|
||
shift = (word_length - (start + length));
|
||
return (x >> shift) & mask;
|
||
}
|
||
|
||
#endif /* ! CGEN_INT_INSN_P */
|
||
|
||
/* Default extraction routine.
|
||
|
||
INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
|
||
or sometimes less for cases like the m32r where the base insn size is 32
|
||
but some insns are 16 bits.
|
||
ATTRS is a mask of the boolean attributes. We only need `SIGNED',
|
||
but for generality we take a bitmask of all of them.
|
||
WORD_OFFSET is the offset in bits from the start of the insn of the value.
|
||
WORD_LENGTH is the length of the word in bits in which the value resides.
|
||
START is the starting bit number in the word, architecture origin.
|
||
LENGTH is the length of VALUE in bits.
|
||
TOTAL_LENGTH is the total length of the insn in bits.
|
||
|
||
Returns 1 for success, 0 for failure. */
|
||
|
||
/* ??? The return code isn't properly used. wip. */
|
||
|
||
/* ??? This doesn't handle bfd_vma's. Create another function when
|
||
necessary. */
|
||
|
||
static int
|
||
extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
|
||
word_length, total_length, pc, valuep)
|
||
CGEN_CPU_DESC cd;
|
||
CGEN_EXTRACT_INFO *ex_info;
|
||
CGEN_INSN_INT insn_value;
|
||
unsigned int attrs;
|
||
unsigned int word_offset, start, length, word_length, total_length;
|
||
bfd_vma pc;
|
||
long *valuep;
|
||
{
|
||
CGEN_INSN_INT value;
|
||
|
||
/* If LENGTH is zero, this operand doesn't contribute to the value
|
||
so give it a standard value of zero. */
|
||
if (length == 0)
|
||
{
|
||
*valuep = 0;
|
||
return 1;
|
||
}
|
||
|
||
if (CGEN_INT_INSN_P
|
||
&& word_offset != 0)
|
||
abort ();
|
||
|
||
if (word_length > 32)
|
||
abort ();
|
||
|
||
/* For architectures with insns smaller than the insn-base-bitsize,
|
||
word_length may be too big. */
|
||
if (cd->min_insn_bitsize < cd->base_insn_bitsize)
|
||
{
|
||
if (word_offset == 0
|
||
&& word_length > total_length)
|
||
word_length = total_length;
|
||
}
|
||
|
||
/* Does the value reside in INSN_VALUE? */
|
||
|
||
if (word_offset == 0)
|
||
{
|
||
/* Written this way to avoid undefined behaviour. */
|
||
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
||
|
||
if (CGEN_INSN_LSB0_P)
|
||
value = insn_value >> ((start + 1) - length);
|
||
else
|
||
value = insn_value >> (word_length - (start + length));
|
||
value &= mask;
|
||
/* sign extend? */
|
||
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
|
||
&& (value & (1L << (length - 1))))
|
||
value |= ~mask;
|
||
}
|
||
|
||
#if ! CGEN_INT_INSN_P
|
||
|
||
else
|
||
{
|
||
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
|
||
|
||
if (word_length > 32)
|
||
abort ();
|
||
|
||
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
|
||
return 0;
|
||
|
||
value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
|
||
}
|
||
|
||
#endif /* ! CGEN_INT_INSN_P */
|
||
|
||
*valuep = value;
|
||
|
||
return 1;
|
||
}
|
||
|
||
/* Default insn extractor.
|
||
|
||
INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
|
||
The extracted fields are stored in FIELDS.
|
||
EX_INFO is used to handle reading variable length insns.
|
||
Return the length of the insn in bits, or 0 if no match,
|
||
or -1 if an error occurs fetching data (memory_error_func will have
|
||
been called). */
|
||
|
||
static int
|
||
extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
|
||
CGEN_CPU_DESC cd;
|
||
const CGEN_INSN *insn;
|
||
CGEN_EXTRACT_INFO *ex_info;
|
||
CGEN_INSN_INT insn_value;
|
||
CGEN_FIELDS *fields;
|
||
bfd_vma pc;
|
||
{
|
||
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
||
const unsigned char *syn;
|
||
|
||
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
||
|
||
CGEN_INIT_EXTRACT (cd);
|
||
|
||
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
||
{
|
||
int length;
|
||
|
||
if (CGEN_SYNTAX_CHAR_P (*syn))
|
||
continue;
|
||
|
||
length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
|
||
ex_info, insn_value, fields, pc);
|
||
if (length <= 0)
|
||
return length;
|
||
}
|
||
|
||
/* We recognized and successfully extracted this insn. */
|
||
return CGEN_INSN_BITSIZE (insn);
|
||
}
|
||
|
||
/* machine generated code added here */
|
||
|
||
/* Main entry point for operand insertion.
|
||
|
||
This function is basically just a big switch statement. Earlier versions
|
||
used tables to look up the function to use, but
|
||
- if the table contains both assembler and disassembler functions then
|
||
the disassembler contains much of the assembler and vice-versa,
|
||
- there's a lot of inlining possibilities as things grow,
|
||
- using a switch statement avoids the function call overhead.
|
||
|
||
This function could be moved into `parse_insn_normal', but keeping it
|
||
separate makes clear the interface between `parse_insn_normal' and each of
|
||
the handlers. It's also needed by GAS to insert operands that couldn't be
|
||
resolved during parsing.
|
||
*/
|
||
|
||
const char *
|
||
m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
|
||
CGEN_CPU_DESC cd;
|
||
int opindex;
|
||
CGEN_FIELDS * fields;
|
||
CGEN_INSN_BYTES_PTR buffer;
|
||
bfd_vma pc;
|
||
{
|
||
const char * errmsg = NULL;
|
||
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
|
||
|
||
switch (opindex)
|
||
{
|
||
case M32R_OPERAND_ACC :
|
||
errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_ACCD :
|
||
errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_ACCS :
|
||
errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_DCR :
|
||
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_DISP16 :
|
||
{
|
||
long value = fields->f_disp16;
|
||
value = ((int) (((value) - (pc))) >> (2));
|
||
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
|
||
}
|
||
break;
|
||
case M32R_OPERAND_DISP24 :
|
||
{
|
||
long value = fields->f_disp24;
|
||
value = ((int) (((value) - (pc))) >> (2));
|
||
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
|
||
}
|
||
break;
|
||
case M32R_OPERAND_DISP8 :
|
||
{
|
||
long value = fields->f_disp8;
|
||
value = ((int) (((value) - (((pc) & (-4))))) >> (2));
|
||
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
|
||
}
|
||
break;
|
||
case M32R_OPERAND_DR :
|
||
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_HASH :
|
||
break;
|
||
case M32R_OPERAND_HI16 :
|
||
errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_IMM1 :
|
||
{
|
||
long value = fields->f_imm1;
|
||
value = ((value) - (1));
|
||
errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
|
||
}
|
||
break;
|
||
case M32R_OPERAND_SCR :
|
||
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_SIMM16 :
|
||
errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_SIMM8 :
|
||
errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_SLO16 :
|
||
errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_SR :
|
||
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_SRC1 :
|
||
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_SRC2 :
|
||
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_UIMM16 :
|
||
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_UIMM24 :
|
||
errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_UIMM4 :
|
||
errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_UIMM5 :
|
||
errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
|
||
break;
|
||
case M32R_OPERAND_ULO16 :
|
||
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
|
||
break;
|
||
|
||
default :
|
||
/* xgettext:c-format */
|
||
fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
|
||
opindex);
|
||
abort ();
|
||
}
|
||
|
||
return errmsg;
|
||
}
|
||
|
||
/* Main entry point for operand extraction.
|
||
The result is <= 0 for error, >0 for success.
|
||
??? Actual values aren't well defined right now.
|
||
|
||
This function is basically just a big switch statement. Earlier versions
|
||
used tables to look up the function to use, but
|
||
- if the table contains both assembler and disassembler functions then
|
||
the disassembler contains much of the assembler and vice-versa,
|
||
- there's a lot of inlining possibilities as things grow,
|
||
- using a switch statement avoids the function call overhead.
|
||
|
||
This function could be moved into `print_insn_normal', but keeping it
|
||
separate makes clear the interface between `print_insn_normal' and each of
|
||
the handlers.
|
||
*/
|
||
|
||
int
|
||
m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
|
||
CGEN_CPU_DESC cd;
|
||
int opindex;
|
||
CGEN_EXTRACT_INFO *ex_info;
|
||
CGEN_INSN_INT insn_value;
|
||
CGEN_FIELDS * fields;
|
||
bfd_vma pc;
|
||
{
|
||
/* Assume success (for those operands that are nops). */
|
||
int length = 1;
|
||
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
|
||
|
||
switch (opindex)
|
||
{
|
||
case M32R_OPERAND_ACC :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
|
||
break;
|
||
case M32R_OPERAND_ACCD :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
|
||
break;
|
||
case M32R_OPERAND_ACCS :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
|
||
break;
|
||
case M32R_OPERAND_DCR :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
|
||
break;
|
||
case M32R_OPERAND_DISP16 :
|
||
{
|
||
long value;
|
||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
|
||
value = ((((value) << (2))) + (pc));
|
||
fields->f_disp16 = value;
|
||
}
|
||
break;
|
||
case M32R_OPERAND_DISP24 :
|
||
{
|
||
long value;
|
||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
|
||
value = ((((value) << (2))) + (pc));
|
||
fields->f_disp24 = value;
|
||
}
|
||
break;
|
||
case M32R_OPERAND_DISP8 :
|
||
{
|
||
long value;
|
||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
|
||
value = ((((value) << (2))) + (((pc) & (-4))));
|
||
fields->f_disp8 = value;
|
||
}
|
||
break;
|
||
case M32R_OPERAND_DR :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
|
||
break;
|
||
case M32R_OPERAND_HASH :
|
||
break;
|
||
case M32R_OPERAND_HI16 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
|
||
break;
|
||
case M32R_OPERAND_IMM1 :
|
||
{
|
||
long value;
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
|
||
value = ((value) + (1));
|
||
fields->f_imm1 = value;
|
||
}
|
||
break;
|
||
case M32R_OPERAND_SCR :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
|
||
break;
|
||
case M32R_OPERAND_SIMM16 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
|
||
break;
|
||
case M32R_OPERAND_SIMM8 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
|
||
break;
|
||
case M32R_OPERAND_SLO16 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
|
||
break;
|
||
case M32R_OPERAND_SR :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
|
||
break;
|
||
case M32R_OPERAND_SRC1 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
|
||
break;
|
||
case M32R_OPERAND_SRC2 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
|
||
break;
|
||
case M32R_OPERAND_UIMM16 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
|
||
break;
|
||
case M32R_OPERAND_UIMM24 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
|
||
break;
|
||
case M32R_OPERAND_UIMM4 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
|
||
break;
|
||
case M32R_OPERAND_UIMM5 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
|
||
break;
|
||
case M32R_OPERAND_ULO16 :
|
||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
|
||
break;
|
||
|
||
default :
|
||
/* xgettext:c-format */
|
||
fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
|
||
opindex);
|
||
abort ();
|
||
}
|
||
|
||
return length;
|
||
}
|
||
|
||
cgen_insert_fn * const m32r_cgen_insert_handlers[] =
|
||
{
|
||
insert_insn_normal,
|
||
};
|
||
|
||
cgen_extract_fn * const m32r_cgen_extract_handlers[] =
|
||
{
|
||
extract_insn_normal,
|
||
};
|
||
|
||
/* Getting values from cgen_fields is handled by a collection of functions.
|
||
They are distinguished by the type of the VALUE argument they return.
|
||
TODO: floating point, inlining support, remove cases where result type
|
||
not appropriate. */
|
||
|
||
int
|
||
m32r_cgen_get_int_operand (cd, opindex, fields)
|
||
CGEN_CPU_DESC cd;
|
||
int opindex;
|
||
const CGEN_FIELDS * fields;
|
||
{
|
||
int value;
|
||
|
||
switch (opindex)
|
||
{
|
||
case M32R_OPERAND_ACC :
|
||
value = fields->f_acc;
|
||
break;
|
||
case M32R_OPERAND_ACCD :
|
||
value = fields->f_accd;
|
||
break;
|
||
case M32R_OPERAND_ACCS :
|
||
value = fields->f_accs;
|
||
break;
|
||
case M32R_OPERAND_DCR :
|
||
value = fields->f_r1;
|
||
break;
|
||
case M32R_OPERAND_DISP16 :
|
||
value = fields->f_disp16;
|
||
break;
|
||
case M32R_OPERAND_DISP24 :
|
||
value = fields->f_disp24;
|
||
break;
|
||
case M32R_OPERAND_DISP8 :
|
||
value = fields->f_disp8;
|
||
break;
|
||
case M32R_OPERAND_DR :
|
||
value = fields->f_r1;
|
||
break;
|
||
case M32R_OPERAND_HASH :
|
||
value = 0;
|
||
break;
|
||
case M32R_OPERAND_HI16 :
|
||
value = fields->f_hi16;
|
||
break;
|
||
case M32R_OPERAND_IMM1 :
|
||
value = fields->f_imm1;
|
||
break;
|
||
case M32R_OPERAND_SCR :
|
||
value = fields->f_r2;
|
||
break;
|
||
case M32R_OPERAND_SIMM16 :
|
||
value = fields->f_simm16;
|
||
break;
|
||
case M32R_OPERAND_SIMM8 :
|
||
value = fields->f_simm8;
|
||
break;
|
||
case M32R_OPERAND_SLO16 :
|
||
value = fields->f_simm16;
|
||
break;
|
||
case M32R_OPERAND_SR :
|
||
value = fields->f_r2;
|
||
break;
|
||
case M32R_OPERAND_SRC1 :
|
||
value = fields->f_r1;
|
||
break;
|
||
case M32R_OPERAND_SRC2 :
|
||
value = fields->f_r2;
|
||
break;
|
||
case M32R_OPERAND_UIMM16 :
|
||
value = fields->f_uimm16;
|
||
break;
|
||
case M32R_OPERAND_UIMM24 :
|
||
value = fields->f_uimm24;
|
||
break;
|
||
case M32R_OPERAND_UIMM4 :
|
||
value = fields->f_uimm4;
|
||
break;
|
||
case M32R_OPERAND_UIMM5 :
|
||
value = fields->f_uimm5;
|
||
break;
|
||
case M32R_OPERAND_ULO16 :
|
||
value = fields->f_uimm16;
|
||
break;
|
||
|
||
default :
|
||
/* xgettext:c-format */
|
||
fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
|
||
opindex);
|
||
abort ();
|
||
}
|
||
|
||
return value;
|
||
}
|
||
|
||
bfd_vma
|
||
m32r_cgen_get_vma_operand (cd, opindex, fields)
|
||
CGEN_CPU_DESC cd;
|
||
int opindex;
|
||
const CGEN_FIELDS * fields;
|
||
{
|
||
bfd_vma value;
|
||
|
||
switch (opindex)
|
||
{
|
||
case M32R_OPERAND_ACC :
|
||
value = fields->f_acc;
|
||
break;
|
||
case M32R_OPERAND_ACCD :
|
||
value = fields->f_accd;
|
||
break;
|
||
case M32R_OPERAND_ACCS :
|
||
value = fields->f_accs;
|
||
break;
|
||
case M32R_OPERAND_DCR :
|
||
value = fields->f_r1;
|
||
break;
|
||
case M32R_OPERAND_DISP16 :
|
||
value = fields->f_disp16;
|
||
break;
|
||
case M32R_OPERAND_DISP24 :
|
||
value = fields->f_disp24;
|
||
break;
|
||
case M32R_OPERAND_DISP8 :
|
||
value = fields->f_disp8;
|
||
break;
|
||
case M32R_OPERAND_DR :
|
||
value = fields->f_r1;
|
||
break;
|
||
case M32R_OPERAND_HASH :
|
||
value = 0;
|
||
break;
|
||
case M32R_OPERAND_HI16 :
|
||
value = fields->f_hi16;
|
||
break;
|
||
case M32R_OPERAND_IMM1 :
|
||
value = fields->f_imm1;
|
||
break;
|
||
case M32R_OPERAND_SCR :
|
||
value = fields->f_r2;
|
||
break;
|
||
case M32R_OPERAND_SIMM16 :
|
||
value = fields->f_simm16;
|
||
break;
|
||
case M32R_OPERAND_SIMM8 :
|
||
value = fields->f_simm8;
|
||
break;
|
||
case M32R_OPERAND_SLO16 :
|
||
value = fields->f_simm16;
|
||
break;
|
||
case M32R_OPERAND_SR :
|
||
value = fields->f_r2;
|
||
break;
|
||
case M32R_OPERAND_SRC1 :
|
||
value = fields->f_r1;
|
||
break;
|
||
case M32R_OPERAND_SRC2 :
|
||
value = fields->f_r2;
|
||
break;
|
||
case M32R_OPERAND_UIMM16 :
|
||
value = fields->f_uimm16;
|
||
break;
|
||
case M32R_OPERAND_UIMM24 :
|
||
value = fields->f_uimm24;
|
||
break;
|
||
case M32R_OPERAND_UIMM4 :
|
||
value = fields->f_uimm4;
|
||
break;
|
||
case M32R_OPERAND_UIMM5 :
|
||
value = fields->f_uimm5;
|
||
break;
|
||
case M32R_OPERAND_ULO16 :
|
||
value = fields->f_uimm16;
|
||
break;
|
||
|
||
default :
|
||
/* xgettext:c-format */
|
||
fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
|
||
opindex);
|
||
abort ();
|
||
}
|
||
|
||
return value;
|
||
}
|
||
|
||
/* Stuffing values in cgen_fields is handled by a collection of functions.
|
||
They are distinguished by the type of the VALUE argument they accept.
|
||
TODO: floating point, inlining support, remove cases where argument type
|
||
not appropriate. */
|
||
|
||
void
|
||
m32r_cgen_set_int_operand (cd, opindex, fields, value)
|
||
CGEN_CPU_DESC cd;
|
||
int opindex;
|
||
CGEN_FIELDS * fields;
|
||
int value;
|
||
{
|
||
switch (opindex)
|
||
{
|
||
case M32R_OPERAND_ACC :
|
||
fields->f_acc = value;
|
||
break;
|
||
case M32R_OPERAND_ACCD :
|
||
fields->f_accd = value;
|
||
break;
|
||
case M32R_OPERAND_ACCS :
|
||
fields->f_accs = value;
|
||
break;
|
||
case M32R_OPERAND_DCR :
|
||
fields->f_r1 = value;
|
||
break;
|
||
case M32R_OPERAND_DISP16 :
|
||
fields->f_disp16 = value;
|
||
break;
|
||
case M32R_OPERAND_DISP24 :
|
||
fields->f_disp24 = value;
|
||
break;
|
||
case M32R_OPERAND_DISP8 :
|
||
fields->f_disp8 = value;
|
||
break;
|
||
case M32R_OPERAND_DR :
|
||
fields->f_r1 = value;
|
||
break;
|
||
case M32R_OPERAND_HASH :
|
||
break;
|
||
case M32R_OPERAND_HI16 :
|
||
fields->f_hi16 = value;
|
||
break;
|
||
case M32R_OPERAND_IMM1 :
|
||
fields->f_imm1 = value;
|
||
break;
|
||
case M32R_OPERAND_SCR :
|
||
fields->f_r2 = value;
|
||
break;
|
||
case M32R_OPERAND_SIMM16 :
|
||
fields->f_simm16 = value;
|
||
break;
|
||
case M32R_OPERAND_SIMM8 :
|
||
fields->f_simm8 = value;
|
||
break;
|
||
case M32R_OPERAND_SLO16 :
|
||
fields->f_simm16 = value;
|
||
break;
|
||
case M32R_OPERAND_SR :
|
||
fields->f_r2 = value;
|
||
break;
|
||
case M32R_OPERAND_SRC1 :
|
||
fields->f_r1 = value;
|
||
break;
|
||
case M32R_OPERAND_SRC2 :
|
||
fields->f_r2 = value;
|
||
break;
|
||
case M32R_OPERAND_UIMM16 :
|
||
fields->f_uimm16 = value;
|
||
break;
|
||
case M32R_OPERAND_UIMM24 :
|
||
fields->f_uimm24 = value;
|
||
break;
|
||
case M32R_OPERAND_UIMM4 :
|
||
fields->f_uimm4 = value;
|
||
break;
|
||
case M32R_OPERAND_UIMM5 :
|
||
fields->f_uimm5 = value;
|
||
break;
|
||
case M32R_OPERAND_ULO16 :
|
||
fields->f_uimm16 = value;
|
||
break;
|
||
|
||
default :
|
||
/* xgettext:c-format */
|
||
fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
|
||
opindex);
|
||
abort ();
|
||
}
|
||
}
|
||
|
||
void
|
||
m32r_cgen_set_vma_operand (cd, opindex, fields, value)
|
||
CGEN_CPU_DESC cd;
|
||
int opindex;
|
||
CGEN_FIELDS * fields;
|
||
bfd_vma value;
|
||
{
|
||
switch (opindex)
|
||
{
|
||
case M32R_OPERAND_ACC :
|
||
fields->f_acc = value;
|
||
break;
|
||
case M32R_OPERAND_ACCD :
|
||
fields->f_accd = value;
|
||
break;
|
||
case M32R_OPERAND_ACCS :
|
||
fields->f_accs = value;
|
||
break;
|
||
case M32R_OPERAND_DCR :
|
||
fields->f_r1 = value;
|
||
break;
|
||
case M32R_OPERAND_DISP16 :
|
||
fields->f_disp16 = value;
|
||
break;
|
||
case M32R_OPERAND_DISP24 :
|
||
fields->f_disp24 = value;
|
||
break;
|
||
case M32R_OPERAND_DISP8 :
|
||
fields->f_disp8 = value;
|
||
break;
|
||
case M32R_OPERAND_DR :
|
||
fields->f_r1 = value;
|
||
break;
|
||
case M32R_OPERAND_HASH :
|
||
break;
|
||
case M32R_OPERAND_HI16 :
|
||
fields->f_hi16 = value;
|
||
break;
|
||
case M32R_OPERAND_IMM1 :
|
||
fields->f_imm1 = value;
|
||
break;
|
||
case M32R_OPERAND_SCR :
|
||
fields->f_r2 = value;
|
||
break;
|
||
case M32R_OPERAND_SIMM16 :
|
||
fields->f_simm16 = value;
|
||
break;
|
||
case M32R_OPERAND_SIMM8 :
|
||
fields->f_simm8 = value;
|
||
break;
|
||
case M32R_OPERAND_SLO16 :
|
||
fields->f_simm16 = value;
|
||
break;
|
||
case M32R_OPERAND_SR :
|
||
fields->f_r2 = value;
|
||
break;
|
||
case M32R_OPERAND_SRC1 :
|
||
fields->f_r1 = value;
|
||
break;
|
||
case M32R_OPERAND_SRC2 :
|
||
fields->f_r2 = value;
|
||
break;
|
||
case M32R_OPERAND_UIMM16 :
|
||
fields->f_uimm16 = value;
|
||
break;
|
||
case M32R_OPERAND_UIMM24 :
|
||
fields->f_uimm24 = value;
|
||
break;
|
||
case M32R_OPERAND_UIMM4 :
|
||
fields->f_uimm4 = value;
|
||
break;
|
||
case M32R_OPERAND_UIMM5 :
|
||
fields->f_uimm5 = value;
|
||
break;
|
||
case M32R_OPERAND_ULO16 :
|
||
fields->f_uimm16 = value;
|
||
break;
|
||
|
||
default :
|
||
/* xgettext:c-format */
|
||
fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
|
||
opindex);
|
||
abort ();
|
||
}
|
||
}
|
||
|
||
/* Function to call before using the instruction builder tables. */
|
||
|
||
void
|
||
m32r_cgen_init_ibld_table (cd)
|
||
CGEN_CPU_DESC cd;
|
||
{
|
||
cd->insert_handlers = & m32r_cgen_insert_handlers[0];
|
||
cd->extract_handlers = & m32r_cgen_extract_handlers[0];
|
||
|
||
cd->insert_operand = m32r_cgen_insert_operand;
|
||
cd->extract_operand = m32r_cgen_extract_operand;
|
||
|
||
cd->get_int_operand = m32r_cgen_get_int_operand;
|
||
cd->set_int_operand = m32r_cgen_set_int_operand;
|
||
cd->get_vma_operand = m32r_cgen_get_vma_operand;
|
||
cd->set_vma_operand = m32r_cgen_set_vma_operand;
|
||
}
|