519 lines
23 KiB
C
519 lines
23 KiB
C
/* d30v-opc.c -- D30V opcode list
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Copyright 1997, 1998, 1999, 2000, 2005, 2007 Free Software Foundation, Inc.
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Written by Martin Hunt, Cygnus Support
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include <stdio.h>
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#include "sysdep.h"
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#include "opcode/d30v.h"
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/* This table is sorted.
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If you add anything, it MUST be in alphabetical order.
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The first field is the name the assembler uses when looking
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up orcodes. The second field is the name the disassembler will use.
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This allows the assembler to assemble references to r63 (for example)
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or "sp". The disassembler will always use the preferred form (sp). */
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const struct pd_reg pre_defined_registers[] =
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{
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{ "a0", NULL, OPERAND_ACC + 0 },
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{ "a1", NULL, OPERAND_ACC + 1 },
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{ "bpc", NULL, OPERAND_CONTROL + 3 },
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{ "bpsw", NULL, OPERAND_CONTROL + 1 },
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{ "c", "c", OPERAND_FLAG + 7 },
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{ "cr0", "psw", OPERAND_CONTROL },
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{ "cr1", "bpsw", OPERAND_CONTROL + 1 },
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{ "cr10", "mod_s", OPERAND_CONTROL + 10 },
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{ "cr11", "mod_e", OPERAND_CONTROL + 11 },
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{ "cr12", NULL, OPERAND_CONTROL + 12 },
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{ "cr13", NULL, OPERAND_CONTROL + 13 },
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{ "cr14", "iba", OPERAND_CONTROL + 14 },
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{ "cr15", "eit_vb", OPERAND_CONTROL + 15 },
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{ "cr16", "int_s", OPERAND_CONTROL + 16 },
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{ "cr17", "int_m", OPERAND_CONTROL + 17 },
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{ "cr18", NULL, OPERAND_CONTROL + 18 },
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{ "cr19", NULL, OPERAND_CONTROL + 19 },
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{ "cr2", "pc", OPERAND_CONTROL + 2 },
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{ "cr20", NULL, OPERAND_CONTROL + 20 },
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{ "cr21", NULL, OPERAND_CONTROL + 21 },
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{ "cr22", NULL, OPERAND_CONTROL + 22 },
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{ "cr23", NULL, OPERAND_CONTROL + 23 },
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{ "cr24", NULL, OPERAND_CONTROL + 24 },
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{ "cr25", NULL, OPERAND_CONTROL + 25 },
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{ "cr26", NULL, OPERAND_CONTROL + 26 },
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{ "cr27", NULL, OPERAND_CONTROL + 27 },
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{ "cr28", NULL, OPERAND_CONTROL + 28 },
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{ "cr29", NULL, OPERAND_CONTROL + 29 },
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{ "cr3", "bpc", OPERAND_CONTROL + 3 },
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{ "cr30", NULL, OPERAND_CONTROL + 30 },
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{ "cr31", NULL, OPERAND_CONTROL + 31 },
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{ "cr32", NULL, OPERAND_CONTROL + 32 },
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{ "cr33", NULL, OPERAND_CONTROL + 33 },
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{ "cr34", NULL, OPERAND_CONTROL + 34 },
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{ "cr35", NULL, OPERAND_CONTROL + 35 },
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{ "cr36", NULL, OPERAND_CONTROL + 36 },
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{ "cr37", NULL, OPERAND_CONTROL + 37 },
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{ "cr38", NULL, OPERAND_CONTROL + 38 },
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{ "cr39", NULL, OPERAND_CONTROL + 39 },
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{ "cr4", "dpsw", OPERAND_CONTROL + 4 },
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{ "cr40", NULL, OPERAND_CONTROL + 40 },
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{ "cr41", NULL, OPERAND_CONTROL + 41 },
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{ "cr42", NULL, OPERAND_CONTROL + 42 },
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{ "cr43", NULL, OPERAND_CONTROL + 43 },
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{ "cr44", NULL, OPERAND_CONTROL + 44 },
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{ "cr45", NULL, OPERAND_CONTROL + 45 },
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{ "cr46", NULL, OPERAND_CONTROL + 46 },
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{ "cr47", NULL, OPERAND_CONTROL + 47 },
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{ "cr48", NULL, OPERAND_CONTROL + 48 },
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{ "cr49", NULL, OPERAND_CONTROL + 49 },
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{ "cr5","dpc", OPERAND_CONTROL + 5 },
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{ "cr50", NULL, OPERAND_CONTROL + 50 },
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{ "cr51", NULL, OPERAND_CONTROL + 51 },
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{ "cr52", NULL, OPERAND_CONTROL + 52 },
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{ "cr53", NULL, OPERAND_CONTROL + 53 },
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{ "cr54", NULL, OPERAND_CONTROL + 54 },
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{ "cr55", NULL, OPERAND_CONTROL + 55 },
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{ "cr56", NULL, OPERAND_CONTROL + 56 },
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{ "cr57", NULL, OPERAND_CONTROL + 57 },
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{ "cr58", NULL, OPERAND_CONTROL + 58 },
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{ "cr59", NULL, OPERAND_CONTROL + 59 },
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{ "cr6", NULL, OPERAND_CONTROL + 6 },
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{ "cr60", NULL, OPERAND_CONTROL + 60 },
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{ "cr61", NULL, OPERAND_CONTROL + 61 },
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{ "cr62", NULL, OPERAND_CONTROL + 62 },
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{ "cr63", NULL, OPERAND_CONTROL + 63 },
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{ "cr7", "rpt_c", OPERAND_CONTROL + 7 },
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{ "cr8", "rpt_s", OPERAND_CONTROL + 8 },
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{ "cr9", "rpt_e", OPERAND_CONTROL + 9 },
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{ "dpc", NULL, OPERAND_CONTROL + 5 },
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{ "dpsw", NULL, OPERAND_CONTROL + 4 },
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{ "eit_vb", NULL, OPERAND_CONTROL + 15 },
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{ "f0", NULL, OPERAND_FLAG + 0 },
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{ "f1", NULL, OPERAND_FLAG + 1 },
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{ "f2", NULL, OPERAND_FLAG + 2 },
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{ "f3", NULL, OPERAND_FLAG + 3 },
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{ "f4", "s", OPERAND_FLAG + 4 },
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{ "f5", "v", OPERAND_FLAG + 5 },
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{ "f6", "va", OPERAND_FLAG + 6 },
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{ "f7", "c", OPERAND_FLAG + 7 },
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{ "iba", NULL, OPERAND_CONTROL + 14 },
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{ "int_m", NULL, OPERAND_CONTROL + 17 },
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{ "int_s", NULL, OPERAND_CONTROL + 16 },
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{ "link", "r62", 62 },
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{ "mod_e", NULL, OPERAND_CONTROL + 11 },
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{ "mod_s", NULL, OPERAND_CONTROL + 10 },
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{ "pc", NULL, OPERAND_CONTROL + 2 },
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{ "psw", NULL, OPERAND_CONTROL },
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{ "pswh", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 2 },
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{ "pswl", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 1 },
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{ "r0", NULL, 0 },
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{ "r1", NULL, 1 },
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{ "r10", NULL, 10 },
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{ "r11", NULL, 11 },
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{ "r12", NULL, 12 },
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{ "r13", NULL, 13 },
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{ "r14", NULL, 14 },
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{ "r15", NULL, 15 },
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{ "r16", NULL, 16 },
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{ "r17", NULL, 17 },
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{ "r18", NULL, 18 },
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{ "r19", NULL, 19 },
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{ "r2", NULL, 2 },
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{ "r20", NULL, 20 },
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{ "r21", NULL, 21 },
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{ "r22", NULL, 22 },
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{ "r23", NULL, 23 },
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{ "r24", NULL, 24 },
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{ "r25", NULL, 25 },
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{ "r26", NULL, 26 },
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{ "r27", NULL, 27 },
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{ "r28", NULL, 28 },
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{ "r29", NULL, 29 },
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{ "r3", NULL, 3 },
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{ "r30", NULL, 30 },
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{ "r31", NULL, 31 },
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{ "r32", NULL, 32 },
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{ "r33", NULL, 33 },
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{ "r34", NULL, 34 },
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{ "r35", NULL, 35 },
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{ "r36", NULL, 36 },
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{ "r37", NULL, 37 },
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{ "r38", NULL, 38 },
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{ "r39", NULL, 39 },
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{ "r4", NULL, 4 },
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{ "r40", NULL, 40 },
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{ "r41", NULL, 41 },
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{ "r42", NULL, 42 },
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{ "r43", NULL, 43 },
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{ "r44", NULL, 44 },
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{ "r45", NULL, 45 },
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{ "r46", NULL, 46 },
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{ "r47", NULL, 47 },
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{ "r48", NULL, 48 },
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{ "r49", NULL, 49 },
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{ "r5", NULL, 5 },
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{ "r50", NULL, 50 },
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{ "r51", NULL, 51 },
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{ "r52", NULL, 52 },
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{ "r53", NULL, 53 },
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{ "r54", NULL, 54 },
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{ "r55", NULL, 55 },
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{ "r56", NULL, 56 },
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{ "r57", NULL, 57 },
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{ "r58", NULL, 58 },
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{ "r59", NULL, 59 },
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{ "r6", NULL, 6 },
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{ "r60", NULL, 60 },
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{ "r61", NULL, 61 },
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{ "r62", "link", 62 },
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{ "r63", "sp", 63 },
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{ "r7", NULL, 7 },
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{ "r8", NULL, 8 },
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{ "r9", NULL, 9 },
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{ "rpt_c", NULL, OPERAND_CONTROL + 7 },
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{ "rpt_e", NULL, OPERAND_CONTROL + 9 },
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{ "rpt_s", NULL, OPERAND_CONTROL + 8 },
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{ "s", NULL, OPERAND_FLAG + 4 },
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{ "sp", NULL, 63 },
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{ "v", NULL, OPERAND_FLAG + 5 },
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{ "va", NULL, OPERAND_FLAG + 6 },
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};
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int
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reg_name_cnt (void)
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{
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return sizeof (pre_defined_registers) / sizeof (struct pd_reg);
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}
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/* OPCODE TABLE.
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The format of this table is defined in opcode/d30v.h. */
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const struct d30v_opcode d30v_opcode_table[] =
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{
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{ "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 },
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{ "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
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{ "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 },
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{ "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
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{ "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
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{ "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
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{ "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
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{ "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
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{ "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
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{ "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
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{ "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
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{ "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 },
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{ "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
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{ "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
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{ "bra", BRA, 0, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bratnz", BRA, 0x4, { SHORT_B3br, LONG_2br }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bratzr", BRA, 0x4, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP, 0, RELOC_PCREL },
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{ "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
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{ "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtnz", BRA, 0x6, { SHORT_B3br, LONG_2br }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtzr", BRA, 0x6, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
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{ "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
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{ "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 },
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{ "dbra", BRA, 0x10, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbrai", BRA, 0x14, { SHORT_D2r, LONG_Dr }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbsr", BRA, 0x12, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbsri", BRA, 0x16, { SHORT_D2r, LONG_Dr }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
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{ "dbt", BRA, 0xb, { SHORT_NONE }, MU, FLAG_JSR, FLAG_LKR, 0 },
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{ "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
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{ "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
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{ "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS },
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{ "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS },
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{ "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS },
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{ "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS },
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{ "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS },
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{ "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS },
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{ "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS },
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{ "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS },
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{ "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
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{ "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 },
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{ "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 },
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{ "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
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{ "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "mac0", IALU2, 0x14, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
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{ "mac1", IALU2, 0x14, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
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{ "macs0", IALU2, 0x15, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
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{ "macs1", IALU2, 0x15, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
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{ "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 },
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{ "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 },
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{ "msub0", IALU2, 0x16, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
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{ "msub1", IALU2, 0x16, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
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{ "msubs0", IALU2, 0x17, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
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{ "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
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{ "mul", IALU2, 0x10, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
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{ "mul2h", IALU2, 0, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
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{ "mulhxll", IALU2, 0x4, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
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{ "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
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{ "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
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{ "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
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{ "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
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{ "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL16, 0, 0 },
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{ "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
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{ "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 },
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{ "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 },
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{ "mvtacc", IALU2, 0xf, { SHORT_AR }, IU, 0, 0, 0 },
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{ "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 },
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{ "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 },
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{ "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 },
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{ "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 },
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{ "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
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{ "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM | FLAG_JMP, FLAG_SM | FLAG_LKR, 0 },
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{ "repeat", BRA, 0x18, { SHORT_D1r, LONG_2r }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
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{ "repeati", BRA, 0x1a, { SHORT_D2Br, LONG_Dbr }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
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{ "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "rtd", BRA, 0xa, { SHORT_NONE }, MU, FLAG_JMP, FLAG_LKR, 0 },
|
|
{ "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 },
|
|
{ "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 },
|
|
{ "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },
|
|
{ "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },
|
|
{ "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 },
|
|
{ "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 },
|
|
{ "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
|
|
{ "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 },
|
|
{ "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 },
|
|
{ "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 },
|
|
{ "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 },
|
|
{ "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
|
|
{ "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 },
|
|
{ "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
|
|
{ "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 },
|
|
{ "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
|
|
{ "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
|
|
{ "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
|
|
{ "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
|
|
{ "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
|
|
{ "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
|
|
{ "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
|
|
{ "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
|
|
{ "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
|
|
{ "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 },
|
|
{ "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
|
|
{ "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
|
|
{ "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
|
|
{ "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
|
|
{ "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
|
|
{ "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
|
|
{ "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
|
|
{ "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
|
|
{ "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, FLAG_JSR, FLAG_SM | FLAG_LKR, 0 },
|
|
{ "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
|
|
{ "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 },
|
|
{ NULL, 0, 0, { 0 }, 0, 0, 0, 0 },
|
|
};
|
|
|
|
|
|
/* Now define the operand types.
|
|
Format is length, bits, position, flags. */
|
|
|
|
const struct d30v_operand d30v_operand_table[] =
|
|
{
|
|
#define UNUSED (0)
|
|
{ 0, 0, 0, 0 },
|
|
#define Ra (UNUSED + 1)
|
|
{ 6, 6, 0, OPERAND_REG | OPERAND_DEST },
|
|
#define Ra2 (Ra + 1)
|
|
{ 6, 6, 0, OPERAND_REG | OPERAND_DEST | OPERAND_2REG },
|
|
#define Ra3 (Ra2 + 1)
|
|
{ 6, 6, 0, OPERAND_REG },
|
|
#define Rb (Ra3 + 1)
|
|
{ 6, 6, 6, OPERAND_REG },
|
|
#define Rb2 (Rb + 1)
|
|
{ 6, 6, 6, OPERAND_REG | OPERAND_DEST },
|
|
#define Rc (Rb2 + 1)
|
|
{ 6, 6, 12, OPERAND_REG },
|
|
#define Aa (Rc + 1)
|
|
{ 6, 1, 0, OPERAND_ACC | OPERAND_REG | OPERAND_DEST },
|
|
#define Ab (Aa + 1)
|
|
{ 6, 1, 6, OPERAND_ACC | OPERAND_REG },
|
|
#define IMM5 (Ab + 1)
|
|
{ 6, 5, 12, OPERAND_NUM },
|
|
#define IMM5U (IMM5 + 1)
|
|
{ 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */
|
|
#define IMM5S3 (IMM5U + 1)
|
|
{ 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */
|
|
#define IMM6 (IMM5S3 + 1)
|
|
{ 6, 6, 12, OPERAND_NUM | OPERAND_SIGNED },
|
|
#define IMM6U (IMM6 + 1)
|
|
{ 6, 6, 0, OPERAND_NUM },
|
|
#define IMM6U2 (IMM6U + 1)
|
|
{ 6, 6, 12, OPERAND_NUM },
|
|
#define REL6S3 (IMM6U2 + 1)
|
|
{ 6, 6, 0, OPERAND_NUM | OPERAND_SHIFT | OPERAND_PCREL },
|
|
#define REL12S3 (REL6S3 + 1)
|
|
{ 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
|
|
#define IMM12S3 (REL12S3 + 1)
|
|
{ 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
|
|
#define REL18S3 (IMM12S3 + 1)
|
|
{ 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
|
|
#define IMM18S3 (REL18S3 + 1)
|
|
{ 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
|
|
#define REL32 (IMM18S3 + 1)
|
|
{ 32, 32, 0, OPERAND_NUM | OPERAND_PCREL },
|
|
#define IMM32 (REL32 + 1)
|
|
{ 32, 32, 0, OPERAND_NUM },
|
|
#define Fa (IMM32 + 1)
|
|
{ 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST },
|
|
#define Fb (Fa + 1)
|
|
{ 6, 3, 6, OPERAND_REG | OPERAND_FLAG },
|
|
#define Fc (Fb + 1)
|
|
{ 6, 3, 12, OPERAND_REG | OPERAND_FLAG },
|
|
#define ATSIGN (Fc + 1)
|
|
{ 0, 0, 0, OPERAND_ATSIGN},
|
|
#define ATPAR (ATSIGN + 1) /* "@(" */
|
|
{ 0, 0, 0, OPERAND_ATPAR},
|
|
#define PLUS (ATPAR + 1) /* Postincrement. */
|
|
{ 0, 0, 0, OPERAND_PLUS},
|
|
#define MINUS (PLUS + 1) /* Postdecrement. */
|
|
{ 0, 0, 0, OPERAND_MINUS},
|
|
#define ATMINUS (MINUS + 1) /* Predecrement. */
|
|
{ 0, 0, 0, OPERAND_ATMINUS},
|
|
#define Ca (ATMINUS + 1) /* Control register. */
|
|
{ 6, 6, 0, OPERAND_REG | OPERAND_CONTROL | OPERAND_DEST},
|
|
#define Cb (Ca + 1) /* Control register. */
|
|
{ 6, 6, 6, OPERAND_REG | OPERAND_CONTROL},
|
|
#define CC (Cb + 1) /* Condition code (CMPcc and CMPUcc). */
|
|
{ 3, 3, -3, OPERAND_NAME},
|
|
#define Fa2 (CC + 1) /* Flag register (CMPcc and CMPUcc). */
|
|
{ 3, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST},
|
|
#define Fake (Fa2 + 1) /* Place holder for "id" field in mvfsys and mvtsys. */
|
|
{ 6, 2, 12, OPERAND_SPECIAL},
|
|
};
|
|
|
|
/* Now we need to define the instruction formats. */
|
|
|
|
const struct d30v_format d30v_format_table[] =
|
|
{
|
|
{ 0, 0, { 0 } },
|
|
{ SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
|
|
{ SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
|
|
{ SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
|
|
{ SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
|
|
{ SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
|
|
{ SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } },/* Ra,@(Rb+,Rc) */
|
|
{ SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
|
|
{ SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } },/* Ra,@(Rb-,Rc) */
|
|
{ SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
|
|
{ SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */
|
|
{ SHORT_B1, 0, { Rc } }, /* Rc */
|
|
{ SHORT_B2, 2, { IMM18S3 } }, /* imm18 */
|
|
{ SHORT_B2r, 2, { REL18S3 } }, /* rel18 */
|
|
{ SHORT_B3, 0, { Ra3, Rc } }, /* Ra,Rc */
|
|
{ SHORT_B3, 2, { Ra3, IMM12S3 } }, /* Ra,imm12 */
|
|
{ SHORT_B3r, 0, { Ra3, Rc } }, /* Ra,Rc */
|
|
{ SHORT_B3r, 2, { Ra3, REL12S3 } }, /* Ra,rel12 */
|
|
{ SHORT_B3b, 1, { Ra3, Rc } }, /* Ra,Rc */
|
|
{ SHORT_B3b, 3, { Ra3, IMM12S3 } }, /* Ra,imm12 */
|
|
{ SHORT_B3br, 1, { Ra3, Rc } }, /* Ra,Rc */
|
|
{ SHORT_B3br, 3, { Ra3, REL12S3 } }, /* Ra,rel12 */
|
|
{ SHORT_D1r, 0, { Ra, Rc } }, /* Ra,Rc */
|
|
{ SHORT_D1r, 2, { Ra, REL12S3 } }, /* Ra,rel12s3 */
|
|
{ SHORT_D2, 0, { REL6S3, Rc } }, /* rel6s3,Rc */
|
|
{ SHORT_D2, 2, { REL6S3, IMM12S3 } }, /* rel6s3,imm12s3 */
|
|
{ SHORT_D2r, 0, { REL6S3, Rc } }, /* rel6s3,Rc */
|
|
{ SHORT_D2r, 2, { REL6S3, REL12S3 } }, /* rel6s3,rel12s3 */
|
|
{ SHORT_D2Br, 0, { IMM6U, Rc } }, /* imm6u,Rc */
|
|
{ SHORT_D2Br, 2, { IMM6U, REL12S3 } }, /* imm6u,rel12s3 */
|
|
{ SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */
|
|
{ SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */
|
|
{ SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */
|
|
{ SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */
|
|
{ SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */
|
|
{ SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */
|
|
{ SHORT_A5, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
|
|
{ SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
|
|
{ SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */
|
|
{ SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */
|
|
{ SHORT_CMPU, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */
|
|
{ SHORT_CMPU, 2, { CC, Fa2, Rb, IMM6U2} }, /* CC Fa2,Rb,imm6 */
|
|
{ SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */
|
|
{ SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */
|
|
{ SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
|
|
{ SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */
|
|
{ SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */
|
|
{ SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */
|
|
{ SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */
|
|
{ SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */
|
|
{ SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */
|
|
{ SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */
|
|
{ SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */
|
|
{ SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */
|
|
{ SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */
|
|
{ SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */
|
|
{ SHORT_AR, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
|
|
{ LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */
|
|
{ LONG_U, 2, { IMM32 } }, /* imm32 */
|
|
{ LONG_Ur, 2, { REL32 } }, /* rel32 */
|
|
{ LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */
|
|
{ LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
|
|
{ LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
|
|
{ LONG_2, 2, { Ra3, IMM32 } }, /* Ra,imm32 */
|
|
{ LONG_2r, 2, { Ra3, REL32 } }, /* Ra,rel32 */
|
|
{ LONG_2b, 3, { Ra3, IMM32 } }, /* Ra,imm32 */
|
|
{ LONG_2br, 3, { Ra3, REL32 } }, /* Ra,rel32 */
|
|
{ LONG_D, 2, { REL6S3, IMM32 } }, /* rel6s3,imm32 */
|
|
{ LONG_Dr, 2, { REL6S3, REL32 } }, /* rel6s3,rel32 */
|
|
{ LONG_Dbr, 2, { IMM6U, REL32 } }, /* imm6,rel32 */
|
|
{ 0, 0, { 0 } },
|
|
};
|
|
|
|
const char *d30v_ecc_names[] =
|
|
{
|
|
"al",
|
|
"tx",
|
|
"fx",
|
|
"xt",
|
|
"xf",
|
|
"tt",
|
|
"tf",
|
|
"res"
|
|
};
|
|
|
|
const char *d30v_cc_names[] =
|
|
{
|
|
"eq",
|
|
"ne",
|
|
"gt",
|
|
"ge",
|
|
"lt",
|
|
"le",
|
|
"ps",
|
|
"ng",
|
|
NULL
|
|
};
|