61baf725ec
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355 lines
9.3 KiB
C
355 lines
9.3 KiB
C
/* CPU family header for lm32bf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright 1996-2017 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_LM32BF_H
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#define CPU_LM32BF_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 1
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 1
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/* The size of an "int" needed to hold an instruction word.
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This is usually 32 bits, but some architectures needs 64 bits. */
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typedef CGEN_INSN_INT CGEN_INSN_WORD;
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#include "cgen-engine.h"
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* Program counter */
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USI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) (CPU (h_pc) = (x))
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/* General purpose registers */
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SI h_gr[32];
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#define GET_H_GR(a1) CPU (h_gr)[a1]
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#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
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/* Control and status registers */
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SI h_csr[32];
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#define GET_H_CSR(a1) CPU (h_csr)[a1]
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#define SET_H_CSR(a1, x) (CPU (h_csr)[a1] = (x))
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} hardware;
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#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
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} LM32BF_CPU_DATA;
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/* Cover fns for register access. */
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USI lm32bf_h_pc_get (SIM_CPU *);
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void lm32bf_h_pc_set (SIM_CPU *, USI);
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SI lm32bf_h_gr_get (SIM_CPU *, UINT);
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void lm32bf_h_gr_set (SIM_CPU *, UINT, SI);
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SI lm32bf_h_csr_get (SIM_CPU *, UINT);
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void lm32bf_h_csr_set (SIM_CPU *, UINT, SI);
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/* These must be hand-written. */
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extern CPUREG_FETCH_FN lm32bf_fetch_register;
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extern CPUREG_STORE_FN lm32bf_store_register;
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typedef struct {
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int empty;
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} MODEL_LM32_DATA;
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/* Instruction argument buffer. */
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union sem_fields {
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struct { /* no operands */
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int empty;
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} sfmt_empty;
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struct { /* */
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IADDR i_call;
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} sfmt_bi;
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struct { /* */
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UINT f_csr;
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UINT f_r1;
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} sfmt_wcsr;
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struct { /* */
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UINT f_csr;
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UINT f_r2;
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} sfmt_rcsr;
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struct { /* */
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IADDR i_branch;
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UINT f_r0;
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UINT f_r1;
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} sfmt_be;
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struct { /* */
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UINT f_r0;
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UINT f_r1;
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UINT f_uimm;
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} sfmt_andi;
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struct { /* */
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INT f_imm;
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UINT f_r0;
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UINT f_r1;
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} sfmt_addi;
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struct { /* */
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UINT f_r0;
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UINT f_r1;
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UINT f_r2;
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UINT f_user;
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} sfmt_user;
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#if WITH_SCACHE_PBB
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/* Writeback handler. */
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struct {
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/* Pointer to argbuf entry for insn whose results need writing back. */
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const struct argbuf *abuf;
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} write;
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/* x-before handler */
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struct {
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/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
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int first_p;
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} before;
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/* x-after handler */
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struct {
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int empty;
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} after;
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/* This entry is used to terminate each pbb. */
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struct {
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/* Number of insns in pbb. */
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int insn_count;
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/* Next pbb to execute. */
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SCACHE *next;
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SCACHE *branch_target;
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} chain;
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#endif
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};
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/* The ARGBUF struct. */
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struct argbuf {
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/* These are the baseclass definitions. */
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IADDR addr;
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const IDESC *idesc;
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char trace_p;
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char profile_p;
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/* ??? Temporary hack for skip insns. */
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char skip_count;
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char unused;
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/* cpu specific data follows */
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union sem semantic;
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int written;
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union sem_fields fields;
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};
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/* A cached insn.
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??? SCACHE used to contain more than just argbuf. We could delete the
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type entirely and always just use ARGBUF, but for future concerns and as
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a level of abstraction it is left in. */
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struct scache {
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struct argbuf argbuf;
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};
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/* Macros to simplify extraction, reading and semantic code.
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These define and assign the local vars that contain the insn's fields. */
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#define EXTRACT_IFMT_EMPTY_VARS \
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unsigned int length;
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#define EXTRACT_IFMT_EMPTY_CODE \
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length = 0; \
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#define EXTRACT_IFMT_ADD_VARS \
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UINT f_opcode; \
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UINT f_r0; \
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UINT f_r1; \
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UINT f_r2; \
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UINT f_resv0; \
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unsigned int length;
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#define EXTRACT_IFMT_ADD_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
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#define EXTRACT_IFMT_ADDI_VARS \
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UINT f_opcode; \
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UINT f_r0; \
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UINT f_r1; \
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INT f_imm; \
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unsigned int length;
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#define EXTRACT_IFMT_ADDI_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
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#define EXTRACT_IFMT_ANDI_VARS \
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UINT f_opcode; \
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UINT f_r0; \
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UINT f_r1; \
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UINT f_uimm; \
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unsigned int length;
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#define EXTRACT_IFMT_ANDI_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
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#define EXTRACT_IFMT_ANDHII_VARS \
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UINT f_opcode; \
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UINT f_r0; \
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UINT f_r1; \
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UINT f_uimm; \
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unsigned int length;
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#define EXTRACT_IFMT_ANDHII_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
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#define EXTRACT_IFMT_B_VARS \
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UINT f_opcode; \
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UINT f_r0; \
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UINT f_r1; \
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UINT f_r2; \
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UINT f_resv0; \
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unsigned int length;
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#define EXTRACT_IFMT_B_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
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#define EXTRACT_IFMT_BI_VARS \
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UINT f_opcode; \
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SI f_call; \
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unsigned int length;
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#define EXTRACT_IFMT_BI_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4)))); \
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#define EXTRACT_IFMT_BE_VARS \
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UINT f_opcode; \
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UINT f_r0; \
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UINT f_r1; \
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SI f_branch; \
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unsigned int length;
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#define EXTRACT_IFMT_BE_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_branch = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (16))) >> (14)))); \
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#define EXTRACT_IFMT_ORI_VARS \
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UINT f_opcode; \
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UINT f_r0; \
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UINT f_r1; \
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UINT f_uimm; \
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unsigned int length;
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#define EXTRACT_IFMT_ORI_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
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#define EXTRACT_IFMT_RCSR_VARS \
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UINT f_opcode; \
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UINT f_csr; \
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UINT f_r1; \
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UINT f_r2; \
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UINT f_resv0; \
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unsigned int length;
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#define EXTRACT_IFMT_RCSR_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
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#define EXTRACT_IFMT_SEXTB_VARS \
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UINT f_opcode; \
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UINT f_r0; \
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UINT f_r1; \
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UINT f_r2; \
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UINT f_resv0; \
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unsigned int length;
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#define EXTRACT_IFMT_SEXTB_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
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#define EXTRACT_IFMT_USER_VARS \
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UINT f_opcode; \
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UINT f_r0; \
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UINT f_r1; \
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UINT f_r2; \
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UINT f_user; \
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unsigned int length;
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#define EXTRACT_IFMT_USER_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_user = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
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#define EXTRACT_IFMT_WCSR_VARS \
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UINT f_opcode; \
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UINT f_csr; \
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UINT f_r1; \
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UINT f_r2; \
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UINT f_resv0; \
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unsigned int length;
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#define EXTRACT_IFMT_WCSR_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
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f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
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f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
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f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
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#define EXTRACT_IFMT_BREAK_VARS \
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UINT f_opcode; \
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UINT f_exception; \
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unsigned int length;
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#define EXTRACT_IFMT_BREAK_CODE \
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length = 4; \
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f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
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f_exception = EXTRACT_LSB0_UINT (insn, 32, 25, 26); \
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/* Collection of various things for the trace handler to use. */
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typedef struct trace_record {
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IADDR pc;
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/* FIXME:wip */
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} TRACE_RECORD;
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#endif /* CPU_LM32BF_H */
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