34 lines
515 B
ArmAsm
34 lines
515 B
ArmAsm
.include "t-macros.i"
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start
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PSW_BITS = PSW_DM
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;;; Blat our DMAP registers so that they point at on-chip imem
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ldi r2, MAP_INSN | 0xf
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st r2, @(DMAP_REG,r0)
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ldi r2, MAP_INSN
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st r2, @(IMAP1_REG,r0)
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;;; Patch the interrupt vector's dbt entry with a jmp to success
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ldi r4, #trap
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ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE
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ld2w r2, @(0,r4)
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st2w r2, @(0,r5)
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ld2w r2, @(4,r4)
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st2w r2, @(4,r5)
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test_dbt:
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dbt -> nop
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exit47
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success:
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checkpsw2 1 PSW_BITS
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exit0
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.data
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trap: ldi r1, success@word
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jmp r1
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