788 lines
16 KiB
C
788 lines
16 KiB
C
/* Disassemble MSP430 instructions.
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Copyright (C) 2002, 2004, 2005, 2007, 2009, 2010, 2012
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Free Software Foundation, Inc.
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Contributed by Dmitry Diky <diwil@mail.ru>
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include <ctype.h>
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#include <sys/types.h>
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#include "dis-asm.h"
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#include "opintl.h"
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#include "libiberty.h"
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#define DASM_SECTION
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#include "opcode/msp430.h"
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#undef DASM_SECTION
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#define PS(x) (0xffff & (x))
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static unsigned short
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msp430dis_opcode (bfd_vma addr, disassemble_info *info)
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{
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bfd_byte buffer[2];
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int status;
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status = info->read_memory_func (addr, buffer, 2, info);
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if (status != 0)
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{
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info->memory_error_func (status, addr, info);
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return -1;
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}
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return bfd_getl16 (buffer);
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}
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static int
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msp430_nooperands (struct msp430_opcode_s *opcode,
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bfd_vma addr ATTRIBUTE_UNUSED,
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unsigned short insn ATTRIBUTE_UNUSED,
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char *comm,
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int *cycles)
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{
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/* Pop with constant. */
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if (insn == 0x43b2)
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return 0;
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if (insn == opcode->bin_opcode)
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return 2;
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if (opcode->fmt == 0)
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{
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if ((insn & 0x0f00) != 3 || (insn & 0x0f00) != 2)
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return 0;
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strcpy (comm, "emulated...");
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*cycles = 1;
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}
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else
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{
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strcpy (comm, "return from interupt");
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*cycles = 5;
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}
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return 2;
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}
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static int
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msp430_singleoperand (disassemble_info *info,
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struct msp430_opcode_s *opcode,
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bfd_vma addr,
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unsigned short insn,
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char *op,
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char *comm,
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int *cycles)
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{
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int regs = 0, regd = 0;
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int ad = 0, as = 0;
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int where = 0;
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int cmd_len = 2;
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short dst = 0;
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regd = insn & 0x0f;
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regs = (insn & 0x0f00) >> 8;
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as = (insn & 0x0030) >> 4;
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ad = (insn & 0x0080) >> 7;
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switch (opcode->fmt)
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{
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case 0: /* Emulated work with dst register. */
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if (regs != 2 && regs != 3 && regs != 1)
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return 0;
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/* Check if not clr insn. */
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if (opcode->bin_opcode == 0x4300 && (ad || as))
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return 0;
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/* Check if really inc, incd insns. */
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if ((opcode->bin_opcode & 0xff00) == 0x5300 && as == 3)
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return 0;
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if (ad == 0)
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{
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*cycles = 1;
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/* Register. */
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if (regd == 0)
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{
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*cycles += 1;
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sprintf (op, "r0");
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}
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else if (regd == 1)
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sprintf (op, "r1");
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else if (regd == 2)
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sprintf (op, "r2");
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else
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sprintf (op, "r%d", regd);
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}
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else /* ad == 1 msp430dis_opcode. */
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{
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if (regd == 0)
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{
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/* PC relative. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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*cycles = 4;
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sprintf (op, "0x%04x", dst);
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sprintf (comm, "PC rel. abs addr 0x%04x",
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PS ((short) (addr + 2) + dst));
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}
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else if (regd == 2)
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{
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/* Absolute. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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*cycles = 4;
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sprintf (op, "&0x%04x", PS (dst));
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}
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else
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{
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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*cycles = 4;
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sprintf (op, "%d(r%d)", dst, regd);
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}
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}
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break;
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case 2: /* rrc, push, call, swpb, rra, sxt, push, call, reti etc... */
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if (as == 0)
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{
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if (regd == 3)
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{
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/* Constsnts. */
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sprintf (op, "#0");
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sprintf (comm, "r3 As==00");
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}
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else
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{
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/* Register. */
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sprintf (op, "r%d", regd);
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}
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*cycles = 1;
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}
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else if (as == 2)
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{
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*cycles = 1;
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if (regd == 2)
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{
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sprintf (op, "#4");
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sprintf (comm, "r2 As==10");
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}
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else if (regd == 3)
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{
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sprintf (op, "#2");
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sprintf (comm, "r3 As==10");
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}
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else
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{
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*cycles = 3;
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/* Indexed register mode @Rn. */
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sprintf (op, "@r%d", regd);
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}
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}
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else if (as == 3)
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{
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*cycles = 1;
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if (regd == 2)
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{
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sprintf (op, "#8");
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sprintf (comm, "r2 As==11");
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}
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else if (regd == 3)
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{
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sprintf (op, "#-1");
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sprintf (comm, "r3 As==11");
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}
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else if (regd == 0)
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{
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*cycles = 3;
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/* absolute. @pc+ */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op, "#%d", dst);
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sprintf (comm, "#0x%04x", PS (dst));
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}
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else
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{
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*cycles = 3;
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sprintf (op, "@r%d+", regd);
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}
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}
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else if (as == 1)
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{
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*cycles = 4;
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if (regd == 0)
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{
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/* PC relative. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op, "0x%04x", PS (dst));
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sprintf (comm, "PC rel. 0x%04x",
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PS ((short) addr + 2 + dst));
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}
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else if (regd == 2)
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{
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/* Absolute. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op, "&0x%04x", PS (dst));
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}
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else if (regd == 3)
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{
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*cycles = 1;
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sprintf (op, "#1");
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sprintf (comm, "r3 As==01");
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}
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else
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{
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/* Indexd. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op, "%d(r%d)", dst, regd);
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}
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}
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break;
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case 3: /* Jumps. */
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where = insn & 0x03ff;
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if (where & 0x200)
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where |= ~0x03ff;
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if (where > 512 || where < -511)
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return 0;
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where *= 2;
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sprintf (op, "$%+-8d", where + 2);
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sprintf (comm, "abs 0x%x", PS ((short) (addr) + 2 + where));
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*cycles = 2;
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return 2;
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break;
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default:
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cmd_len = 0;
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}
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return cmd_len;
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}
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static int
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msp430_doubleoperand (disassemble_info *info,
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struct msp430_opcode_s *opcode,
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bfd_vma addr,
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unsigned short insn,
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char *op1,
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char *op2,
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char *comm1,
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char *comm2,
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int *cycles)
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{
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int regs = 0, regd = 0;
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int ad = 0, as = 0;
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int cmd_len = 2;
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short dst = 0;
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regd = insn & 0x0f;
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regs = (insn & 0x0f00) >> 8;
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as = (insn & 0x0030) >> 4;
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ad = (insn & 0x0080) >> 7;
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if (opcode->fmt == 0)
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{
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/* Special case: rla and rlc are the only 2 emulated instructions that
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fall into two operand instructions. */
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/* With dst, there are only:
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Rm Register,
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x(Rm) Indexed,
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0xXXXX Relative,
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&0xXXXX Absolute
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emulated_ins dst
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basic_ins dst, dst. */
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if (regd != regs || as != ad)
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return 0; /* May be 'data' section. */
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if (ad == 0)
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{
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/* Register mode. */
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if (regd == 3)
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{
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strcpy (comm1, _("Illegal as emulation instr"));
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return -1;
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}
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sprintf (op1, "r%d", regd);
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*cycles = 1;
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}
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else /* ad == 1 */
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{
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if (regd == 0)
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{
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/* PC relative, Symbolic. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 4;
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*cycles = 6;
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sprintf (op1, "0x%04x", PS (dst));
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sprintf (comm1, "PC rel. 0x%04x",
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PS ((short) addr + 2 + dst));
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}
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else if (regd == 2)
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{
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/* Absolute. */
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dst = msp430dis_opcode (addr + 2, info);
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/* If the 'src' field is not the same as the dst
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then this is not an rla instruction. */
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if (dst != msp430dis_opcode (addr + 4, info))
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return 0;
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cmd_len += 4;
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*cycles = 6;
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sprintf (op1, "&0x%04x", PS (dst));
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}
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else
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{
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/* Indexed. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 4;
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*cycles = 6;
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sprintf (op1, "%d(r%d)", dst, regd);
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}
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}
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*op2 = 0;
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*comm2 = 0;
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return cmd_len;
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}
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/* Two operands exactly. */
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if (ad == 0 && regd == 3)
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{
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/* R2/R3 are illegal as dest: may be data section. */
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strcpy (comm1, _("Illegal as 2-op instr"));
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return -1;
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}
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/* Source. */
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if (as == 0)
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{
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*cycles = 1;
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if (regs == 3)
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{
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/* Constsnts. */
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sprintf (op1, "#0");
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sprintf (comm1, "r3 As==00");
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}
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else
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{
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/* Register. */
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sprintf (op1, "r%d", regs);
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}
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}
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else if (as == 2)
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{
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*cycles = 1;
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if (regs == 2)
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{
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sprintf (op1, "#4");
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sprintf (comm1, "r2 As==10");
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}
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else if (regs == 3)
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{
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sprintf (op1, "#2");
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sprintf (comm1, "r3 As==10");
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}
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else
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{
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*cycles = 2;
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/* Indexed register mode @Rn. */
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sprintf (op1, "@r%d", regs);
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}
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if (!regs)
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*cycles = 3;
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}
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else if (as == 3)
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{
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if (regs == 2)
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{
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sprintf (op1, "#8");
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sprintf (comm1, "r2 As==11");
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*cycles = 1;
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}
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else if (regs == 3)
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{
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sprintf (op1, "#-1");
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sprintf (comm1, "r3 As==11");
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*cycles = 1;
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}
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else if (regs == 0)
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{
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*cycles = 3;
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/* Absolute. @pc+. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op1, "#%d", dst);
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sprintf (comm1, "#0x%04x", PS (dst));
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}
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else
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{
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*cycles = 2;
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sprintf (op1, "@r%d+", regs);
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}
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}
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else if (as == 1)
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{
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if (regs == 0)
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{
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*cycles = 4;
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/* PC relative. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op1, "0x%04x", PS (dst));
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sprintf (comm1, "PC rel. 0x%04x",
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PS ((short) addr + 2 + dst));
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}
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else if (regs == 2)
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{
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*cycles = 2;
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/* Absolute. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op1, "&0x%04x", PS (dst));
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sprintf (comm1, "0x%04x", PS (dst));
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}
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else if (regs == 3)
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{
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*cycles = 1;
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sprintf (op1, "#1");
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sprintf (comm1, "r3 As==01");
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}
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else
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{
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*cycles = 3;
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/* Indexed. */
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dst = msp430dis_opcode (addr + 2, info);
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cmd_len += 2;
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sprintf (op1, "%d(r%d)", dst, regs);
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}
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}
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/* Destination. Special care needed on addr + XXXX. */
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if (ad == 0)
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{
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/* Register. */
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if (regd == 0)
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{
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*cycles += 1;
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sprintf (op2, "r0");
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}
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else if (regd == 1)
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sprintf (op2, "r1");
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else if (regd == 2)
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sprintf (op2, "r2");
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else
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sprintf (op2, "r%d", regd);
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}
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else /* ad == 1. */
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{
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* cycles += 3;
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if (regd == 0)
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{
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/* PC relative. */
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*cycles += 1;
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dst = msp430dis_opcode (addr + cmd_len, info);
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sprintf (op2, "0x%04x", PS (dst));
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sprintf (comm2, "PC rel. 0x%04x",
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PS ((short) addr + cmd_len + dst));
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cmd_len += 2;
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}
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else if (regd == 2)
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{
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/* Absolute. */
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dst = msp430dis_opcode (addr + cmd_len, info);
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cmd_len += 2;
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sprintf (op2, "&0x%04x", PS (dst));
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}
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else
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{
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dst = msp430dis_opcode (addr + cmd_len, info);
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cmd_len += 2;
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sprintf (op2, "%d(r%d)", dst, regd);
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}
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}
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return cmd_len;
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}
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|
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static int
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msp430_branchinstr (disassemble_info *info,
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struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED,
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bfd_vma addr ATTRIBUTE_UNUSED,
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unsigned short insn,
|
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char *op1,
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char *comm1,
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int *cycles)
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{
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int regs = 0, regd = 0;
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int as = 0;
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int cmd_len = 2;
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short dst = 0;
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regd = insn & 0x0f;
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regs = (insn & 0x0f00) >> 8;
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as = (insn & 0x0030) >> 4;
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if (regd != 0) /* Destination register is not a PC. */
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return 0;
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/* dst is a source register. */
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if (as == 0)
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{
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/* Constants. */
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if (regs == 3)
|
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{
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*cycles = 1;
|
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sprintf (op1, "#0");
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sprintf (comm1, "r3 As==00");
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}
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else
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{
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/* Register. */
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*cycles = 1;
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sprintf (op1, "r%d", regs);
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}
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}
|
|
else if (as == 2)
|
|
{
|
|
if (regs == 2)
|
|
{
|
|
*cycles = 2;
|
|
sprintf (op1, "#4");
|
|
sprintf (comm1, "r2 As==10");
|
|
}
|
|
else if (regs == 3)
|
|
{
|
|
*cycles = 1;
|
|
sprintf (op1, "#2");
|
|
sprintf (comm1, "r3 As==10");
|
|
}
|
|
else
|
|
{
|
|
/* Indexed register mode @Rn. */
|
|
*cycles = 2;
|
|
sprintf (op1, "@r%d", regs);
|
|
}
|
|
}
|
|
else if (as == 3)
|
|
{
|
|
if (regs == 2)
|
|
{
|
|
*cycles = 1;
|
|
sprintf (op1, "#8");
|
|
sprintf (comm1, "r2 As==11");
|
|
}
|
|
else if (regs == 3)
|
|
{
|
|
*cycles = 1;
|
|
sprintf (op1, "#-1");
|
|
sprintf (comm1, "r3 As==11");
|
|
}
|
|
else if (regs == 0)
|
|
{
|
|
/* Absolute. @pc+ */
|
|
*cycles = 3;
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
sprintf (op1, "#0x%04x", PS (dst));
|
|
}
|
|
else
|
|
{
|
|
*cycles = 2;
|
|
sprintf (op1, "@r%d+", regs);
|
|
}
|
|
}
|
|
else if (as == 1)
|
|
{
|
|
* cycles = 3;
|
|
|
|
if (regs == 0)
|
|
{
|
|
/* PC relative. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
(*cycles)++;
|
|
sprintf (op1, "0x%04x", PS (dst));
|
|
sprintf (comm1, "PC rel. 0x%04x",
|
|
PS ((short) addr + 2 + dst));
|
|
}
|
|
else if (regs == 2)
|
|
{
|
|
/* Absolute. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
sprintf (op1, "&0x%04x", PS (dst));
|
|
}
|
|
else if (regs == 3)
|
|
{
|
|
(*cycles)--;
|
|
sprintf (op1, "#1");
|
|
sprintf (comm1, "r3 As==01");
|
|
}
|
|
else
|
|
{
|
|
/* Indexd. */
|
|
dst = msp430dis_opcode (addr + 2, info);
|
|
cmd_len += 2;
|
|
sprintf (op1, "%d(r%d)", dst, regs);
|
|
}
|
|
}
|
|
|
|
return cmd_len;
|
|
}
|
|
|
|
int
|
|
print_insn_msp430 (bfd_vma addr, disassemble_info *info)
|
|
{
|
|
void *stream = info->stream;
|
|
fprintf_ftype prin = info->fprintf_func;
|
|
struct msp430_opcode_s *opcode;
|
|
char op1[32], op2[32], comm1[64], comm2[64];
|
|
int cmd_len = 0;
|
|
unsigned short insn;
|
|
int cycles = 0;
|
|
char *bc = "";
|
|
char dinfo[32]; /* Debug purposes. */
|
|
|
|
insn = msp430dis_opcode (addr, info);
|
|
sprintf (dinfo, "0x%04x", insn);
|
|
|
|
if (((int) addr & 0xffff) > 0xffdf)
|
|
{
|
|
(*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn);
|
|
return 2;
|
|
}
|
|
|
|
*comm1 = 0;
|
|
*comm2 = 0;
|
|
|
|
for (opcode = msp430_opcodes; opcode->name; opcode++)
|
|
{
|
|
if ((insn & opcode->bin_mask) == opcode->bin_opcode
|
|
&& opcode->bin_opcode != 0x9300)
|
|
{
|
|
*op1 = 0;
|
|
*op2 = 0;
|
|
*comm1 = 0;
|
|
*comm2 = 0;
|
|
|
|
/* r0 as destination. Ad should be zero. */
|
|
if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0
|
|
&& (0x0080 & insn) == 0)
|
|
{
|
|
cmd_len =
|
|
msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
|
|
&cycles);
|
|
if (cmd_len)
|
|
break;
|
|
}
|
|
|
|
switch (opcode->insn_opnumb)
|
|
{
|
|
case 0:
|
|
cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
|
|
break;
|
|
case 2:
|
|
cmd_len =
|
|
msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
|
|
comm1, comm2, &cycles);
|
|
if (insn & BYTE_OPERATION)
|
|
bc = ".b";
|
|
break;
|
|
case 1:
|
|
cmd_len =
|
|
msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
|
|
&cycles);
|
|
if (insn & BYTE_OPERATION && opcode->fmt != 3)
|
|
bc = ".b";
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (cmd_len)
|
|
break;
|
|
}
|
|
|
|
dinfo[5] = 0;
|
|
|
|
if (cmd_len < 1)
|
|
{
|
|
/* Unknown opcode, or invalid combination of operands. */
|
|
(*prin) (stream, ".word 0x%04x; ????", PS (insn));
|
|
return 2;
|
|
}
|
|
|
|
(*prin) (stream, "%s%s", opcode->name, bc);
|
|
|
|
if (*op1)
|
|
(*prin) (stream, "\t%s", op1);
|
|
if (*op2)
|
|
(*prin) (stream, ",");
|
|
|
|
if (strlen (op1) < 7)
|
|
(*prin) (stream, "\t");
|
|
if (!strlen (op1))
|
|
(*prin) (stream, "\t");
|
|
|
|
if (*op2)
|
|
(*prin) (stream, "%s", op2);
|
|
if (strlen (op2) < 8)
|
|
(*prin) (stream, "\t");
|
|
|
|
if (*comm1 || *comm2)
|
|
(*prin) (stream, ";");
|
|
else if (cycles)
|
|
{
|
|
if (*op2)
|
|
(*prin) (stream, ";");
|
|
else
|
|
{
|
|
if (strlen (op1) < 7)
|
|
(*prin) (stream, ";");
|
|
else
|
|
(*prin) (stream, "\t;");
|
|
}
|
|
}
|
|
if (*comm1)
|
|
(*prin) (stream, "%s", comm1);
|
|
if (*comm1 && *comm2)
|
|
(*prin) (stream, ",");
|
|
if (*comm2)
|
|
(*prin) (stream, " %s", comm2);
|
|
return cmd_len;
|
|
}
|