159 lines
4.7 KiB
C
159 lines
4.7 KiB
C
/* Common Blackfin device stuff.
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Copyright (C) 2010-2020 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef DEVICES_H
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#define DEVICES_H
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#include "hw-base.h"
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#include "hw-main.h"
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#include "hw-device.h"
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#include "hw-tree.h"
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/* We keep the same inital structure layout with DMA enabled devices. */
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struct dv_bfin {
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bu32 base;
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struct hw *dma_master;
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bool acked;
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};
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#define BFIN_MMR_16(mmr) mmr, __pad_##mmr
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/* Most peripherals have either one interrupt or these three. */
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#define DV_PORT_TX 0
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#define DV_PORT_RX 1
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#define DV_PORT_STAT 2
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unsigned int dv_get_bus_num (struct hw *);
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static inline bu8 dv_load_1 (const void *ptr)
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{
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const unsigned char *c = ptr;
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return c[0];
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}
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static inline void dv_store_1 (void *ptr, bu8 val)
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{
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unsigned char *c = ptr;
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c[0] = val;
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}
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static inline bu16 dv_load_2 (const void *ptr)
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{
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const unsigned char *c = ptr;
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return (c[1] << 8) | dv_load_1 (ptr);
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}
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static inline void dv_store_2 (void *ptr, bu16 val)
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{
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unsigned char *c = ptr;
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c[1] = val >> 8;
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dv_store_1 (ptr, val);
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}
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static inline bu32 dv_load_4 (const void *ptr)
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{
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const unsigned char *c = ptr;
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return (c[3] << 24) | (c[2] << 16) | dv_load_2 (ptr);
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}
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static inline void dv_store_4 (void *ptr, bu32 val)
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{
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unsigned char *c = ptr;
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c[3] = val >> 24;
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c[2] = val >> 16;
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dv_store_2 (ptr, val);
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}
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/* Helpers for MMRs where only the specified bits are W1C. The
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rest are left unmodified. */
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#define dv_w1c(ptr, val, bits) (*(ptr) &= ~((val) & (bits)))
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static inline void dv_w1c_2 (bu16 *ptr, bu16 val, bu16 bits)
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{
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dv_w1c (ptr, val, bits);
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}
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static inline void dv_w1c_4 (bu32 *ptr, bu32 val, bu32 bits)
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{
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dv_w1c (ptr, val, bits);
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}
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/* Helpers for MMRs where all bits are RW except for the specified
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bits -- those ones are W1C. */
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#define dv_w1c_partial(ptr, val, bits) \
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(*(ptr) = ((val) | (*(ptr) & (bits))) & ~((val) & (bits)))
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static inline void dv_w1c_2_partial (bu16 *ptr, bu16 val, bu16 bits)
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{
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dv_w1c_partial (ptr, val, bits);
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}
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static inline void dv_w1c_4_partial (bu32 *ptr, bu32 val, bu32 bits)
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{
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dv_w1c_partial (ptr, val, bits);
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}
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/* XXX: Grubbing around in device internals is probably wrong, but
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until someone shows me what's right ... */
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static inline struct hw *
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dv_get_device (SIM_CPU *cpu, const char *device_name)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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void *root = STATE_HW (sd);
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return hw_tree_find_device (root, device_name);
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}
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static inline void *
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dv_get_state (SIM_CPU *cpu, const char *device_name)
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{
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return hw_data (dv_get_device (cpu, device_name));
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}
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#define DV_STATE(cpu, dv) dv_get_state (cpu, "/core/bfin_"#dv)
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#define DV_STATE_CACHED(cpu, dv) \
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({ \
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struct bfin_##dv *__##dv = BFIN_CPU_STATE.dv##_cache; \
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if (!__##dv) \
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BFIN_CPU_STATE.dv##_cache = __##dv = dv_get_state (cpu, "/core/bfin_"#dv); \
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__##dv; \
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})
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void dv_bfin_mmr_invalid (struct hw *, address_word, unsigned nr_bytes, bool write);
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bool dv_bfin_mmr_require (struct hw *, address_word, unsigned nr_bytes, unsigned size, bool write);
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/* For 32-bit memory mapped registers that allow 16-bit or 32-bit access. */
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bool dv_bfin_mmr_require_16_32 (struct hw *, address_word, unsigned nr_bytes, bool write);
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/* For 32-bit memory mapped registers that only allow 16-bit access. */
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#define dv_bfin_mmr_require_16(hw, addr, nr_bytes, write) dv_bfin_mmr_require (hw, addr, nr_bytes, 2, write)
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/* For 32-bit memory mapped registers that only allow 32-bit access. */
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#define dv_bfin_mmr_require_32(hw, addr, nr_bytes, write) dv_bfin_mmr_require (hw, addr, nr_bytes, 4, write)
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#define HW_TRACE_WRITE() \
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HW_TRACE ((me, "write 0x%08lx (%s) length %u with 0x%x", \
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(unsigned long) addr, mmr_name (mmr_off), nr_bytes, value))
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#define HW_TRACE_READ() \
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HW_TRACE ((me, "read 0x%08lx (%s) length %u", \
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(unsigned long) addr, mmr_name (mmr_off), nr_bytes))
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#define HW_TRACE_DMA_WRITE() \
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HW_TRACE ((me, "dma write 0x%08lx length %u", \
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(unsigned long) addr, nr_bytes))
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#define HW_TRACE_DMA_READ() \
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HW_TRACE ((me, "dma read 0x%08lx length %u", \
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(unsigned long) addr, nr_bytes))
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#endif
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