d747e0af3d
* All GDB files that #include defs.h: Removed stdio.h. (defs.h): #include stdio.h. This has been tested by building GDBs for all targets hosted on Sun4. None of the build problems were related to stdio.h inclusion. (n.b. many configurations don't build for other reasons.)
862 lines
19 KiB
C
862 lines
19 KiB
C
/* i80960 instruction disassembler for GDB.
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Copyright (C) 1990-1991 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "defs.h"
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#include "frame.h"
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#include "inferior.h"
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extern char *reg_names[];
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static FILE *stream; /* Output goes here */
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static void print_addr();
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static void ctrl();
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static void cobr();
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static void reg();
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static int mem();
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static void ea();
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static void dstop();
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static void regop();
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static void invalid();
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static int pinsn();
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static void put_abs();
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/* Print the i960 instruction at address 'memaddr' in debugged memory,
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on stream 's'. Returns length of the instruction, in bytes. */
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int
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print_insn( memaddr, s )
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CORE_ADDR memaddr;
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FILE *s;
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{
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unsigned int word1, word2;
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stream = s;
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word1 = read_memory_integer( memaddr, 4 );
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word2 = read_memory_integer( memaddr+4, 4 );
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return pinsn( memaddr, word1, word2 );
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}
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/* Read the i960 instruction at 'memaddr' and return the address of
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the next instruction after that, or 0 if 'memaddr' is not the
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address of a valid instruction. The first word of the instruction
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is stored at 'pword1', and the second word, if any, is stored at
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'pword2'. */
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CORE_ADDR
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next_insn (memaddr, pword1, pword2)
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unsigned long *pword1, *pword2;
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CORE_ADDR memaddr;
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{
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int len;
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unsigned long buf[2];
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/* Read the two (potential) words of the instruction at once,
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to eliminate the overhead of two calls to read_memory ().
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TODO: read more instructions at once and cache them. */
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read_memory (memaddr, buf, sizeof (buf));
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*pword1 = buf[0];
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SWAP_TARGET_AND_HOST (pword1, sizeof (long));
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*pword2 = buf[1];
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SWAP_TARGET_AND_HOST (pword2, sizeof (long));
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/* Divide instruction set into classes based on high 4 bits of opcode*/
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switch ((*pword1 >> 28) & 0xf)
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{
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case 0x0:
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case 0x1: /* ctrl */
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case 0x2:
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case 0x3: /* cobr */
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case 0x5:
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case 0x6:
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case 0x7: /* reg */
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len = 4;
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break;
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case 0x8:
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case 0x9:
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case 0xa:
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case 0xb:
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case 0xc:
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len = mem (memaddr, *pword1, *pword2, 1);
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break;
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default: /* invalid instruction */
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len = 0;
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break;
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}
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if (len)
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return memaddr + len;
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else
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return 0;
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}
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#define IN_GDB
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/*****************************************************************************
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* All code below this point should be identical with that of
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* the disassembler in gdmp960.
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*****************************************************************************/
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struct tabent {
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char *name;
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char numops;
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};
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static int
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pinsn( memaddr, word1, word2 )
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unsigned long memaddr;
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unsigned long word1, word2;
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{
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int instr_len;
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instr_len = 4;
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put_abs( word1, word2 );
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/* Divide instruction set into classes based on high 4 bits of opcode*/
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switch ( (word1 >> 28) & 0xf ){
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case 0x0:
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case 0x1:
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ctrl( memaddr, word1, word2 );
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break;
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case 0x2:
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case 0x3:
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cobr( memaddr, word1, word2 );
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break;
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case 0x5:
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case 0x6:
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case 0x7:
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reg( word1 );
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break;
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case 0x8:
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case 0x9:
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case 0xa:
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case 0xb:
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case 0xc:
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instr_len = mem( memaddr, word1, word2, 0 );
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break;
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default:
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/* invalid instruction, print as data word */
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invalid( word1 );
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break;
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}
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return instr_len;
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}
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/****************************************/
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/* CTRL format */
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/****************************************/
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static void
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ctrl( memaddr, word1, word2 )
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unsigned long memaddr;
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unsigned long word1, word2;
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{
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int i;
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static struct tabent ctrl_tab[] = {
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NULL, 0, /* 0x00 */
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NULL, 0, /* 0x01 */
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NULL, 0, /* 0x02 */
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NULL, 0, /* 0x03 */
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NULL, 0, /* 0x04 */
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NULL, 0, /* 0x05 */
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NULL, 0, /* 0x06 */
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NULL, 0, /* 0x07 */
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"b", 1, /* 0x08 */
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"call", 1, /* 0x09 */
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"ret", 0, /* 0x0a */
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"bal", 1, /* 0x0b */
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NULL, 0, /* 0x0c */
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NULL, 0, /* 0x0d */
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NULL, 0, /* 0x0e */
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NULL, 0, /* 0x0f */
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"bno", 1, /* 0x10 */
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"bg", 1, /* 0x11 */
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"be", 1, /* 0x12 */
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"bge", 1, /* 0x13 */
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"bl", 1, /* 0x14 */
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"bne", 1, /* 0x15 */
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"ble", 1, /* 0x16 */
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"bo", 1, /* 0x17 */
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"faultno", 0, /* 0x18 */
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"faultg", 0, /* 0x19 */
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"faulte", 0, /* 0x1a */
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"faultge", 0, /* 0x1b */
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"faultl", 0, /* 0x1c */
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"faultne", 0, /* 0x1d */
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"faultle", 0, /* 0x1e */
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"faulto", 0, /* 0x1f */
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};
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i = (word1 >> 24) & 0xff;
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if ( (ctrl_tab[i].name == NULL) || ((word1 & 1) != 0) ){
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invalid( word1 );
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return;
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}
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fputs( ctrl_tab[i].name, stream );
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if ( word1 & 2 ){ /* Predicts branch not taken */
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fputs( ".f", stream );
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}
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if ( ctrl_tab[i].numops == 1 ){
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/* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
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word1 &= 0x00ffffff;
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if ( word1 & 0x00800000 ){ /* Sign bit is set */
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word1 |= (-1 & ~0xffffff); /* Sign extend */
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}
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putc( '\t', stream );
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print_addr( word1 + memaddr );
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}
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}
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/****************************************/
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/* COBR format */
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/****************************************/
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static void
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cobr( memaddr, word1, word2 )
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unsigned long memaddr;
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unsigned long word1, word2;
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{
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int src1;
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int src2;
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int i;
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static struct tabent cobr_tab[] = {
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"testno", 1, /* 0x20 */
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"testg", 1, /* 0x21 */
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"teste", 1, /* 0x22 */
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"testge", 1, /* 0x23 */
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"testl", 1, /* 0x24 */
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"testne", 1, /* 0x25 */
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"testle", 1, /* 0x26 */
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"testo", 1, /* 0x27 */
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NULL, 0, /* 0x28 */
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NULL, 0, /* 0x29 */
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NULL, 0, /* 0x2a */
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NULL, 0, /* 0x2b */
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NULL, 0, /* 0x2c */
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NULL, 0, /* 0x2d */
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NULL, 0, /* 0x2e */
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NULL, 0, /* 0x2f */
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"bbc", 3, /* 0x30 */
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"cmpobg", 3, /* 0x31 */
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"cmpobe", 3, /* 0x32 */
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"cmpobge", 3, /* 0x33 */
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"cmpobl", 3, /* 0x34 */
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"cmpobne", 3, /* 0x35 */
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"cmpoble", 3, /* 0x36 */
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"bbs", 3, /* 0x37 */
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"cmpibno", 3, /* 0x38 */
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"cmpibg", 3, /* 0x39 */
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"cmpibe", 3, /* 0x3a */
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"cmpibge", 3, /* 0x3b */
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"cmpibl", 3, /* 0x3c */
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"cmpibne", 3, /* 0x3d */
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"cmpible", 3, /* 0x3e */
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"cmpibo", 3, /* 0x3f */
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};
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i = ((word1 >> 24) & 0xff) - 0x20;
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if ( cobr_tab[i].name == NULL ){
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invalid( word1 );
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return;
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}
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fputs( cobr_tab[i].name, stream );
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if ( word1 & 2 ){ /* Predicts branch not taken */
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fputs( ".f", stream );
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}
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putc( '\t', stream );
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src1 = (word1 >> 19) & 0x1f;
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src2 = (word1 >> 14) & 0x1f;
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if ( word1 & 0x02000 ){ /* M1 is 1 */
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fprintf( stream, "%d", src1 );
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} else { /* M1 is 0 */
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fputs( reg_names[src1], stream );
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}
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if ( cobr_tab[i].numops > 1 ){
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if ( word1 & 1 ){ /* S2 is 1 */
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fprintf( stream, ",sf%d,", src2 );
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} else { /* S1 is 0 */
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fprintf( stream, ",%s,", reg_names[src2] );
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}
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/* Extract displacement and convert to address
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*/
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word1 &= 0x00001ffc;
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if ( word1 & 0x00001000 ){ /* Negative displacement */
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word1 |= (-1 & ~0x1fff); /* Sign extend */
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}
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print_addr( memaddr + word1 );
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}
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}
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/****************************************/
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/* MEM format */
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/****************************************/
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static int /* returns instruction length: 4 or 8 */
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mem( memaddr, word1, word2, noprint )
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unsigned long memaddr;
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unsigned long word1, word2;
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int noprint; /* If TRUE, return instruction length, but
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don't output any text. */
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{
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int i, j;
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int len;
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int mode;
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int offset;
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char *reg1, *reg2, *reg3;
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/* This lookup table is too sparse to make it worth typing in, but not
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* so large as to make a sparse array necessary. We allocate the
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* table at runtime, initialize all entries to empty, and copy the
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* real ones in from an initialization table.
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*
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* NOTE: In this table, the meaning of 'numops' is:
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* 1: single operand
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* 2: 2 operands, load instruction
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* -2: 2 operands, store instruction
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*/
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static struct tabent *mem_tab = NULL;
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static struct { int opcode; char *name; char numops; } mem_init[] = {
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#define MEM_MIN 0x80
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0x80, "ldob", 2,
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0x82, "stob", -2,
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0x84, "bx", 1,
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0x85, "balx", 2,
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0x86, "callx", 1,
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0x88, "ldos", 2,
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0x8a, "stos", -2,
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0x8c, "lda", 2,
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0x90, "ld", 2,
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0x92, "st", -2,
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0x98, "ldl", 2,
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0x9a, "stl", -2,
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0xa0, "ldt", 2,
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0xa2, "stt", -2,
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0xb0, "ldq", 2,
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0xb2, "stq", -2,
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0xc0, "ldib", 2,
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0xc2, "stib", -2,
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0xc8, "ldis", 2,
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0xca, "stis", -2,
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#define MEM_MAX 0xca
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#define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
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0, NULL, 0
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};
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if ( mem_tab == NULL ){
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mem_tab = (struct tabent *) xmalloc( MEM_SIZ );
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bzero( mem_tab, MEM_SIZ );
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for ( i = 0; mem_init[i].opcode != 0; i++ ){
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j = mem_init[i].opcode - MEM_MIN;
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mem_tab[j].name = mem_init[i].name;
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mem_tab[j].numops = mem_init[i].numops;
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}
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}
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i = ((word1 >> 24) & 0xff) - MEM_MIN;
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mode = (word1 >> 10) & 0xf;
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if ( (mem_tab[i].name != NULL) /* Valid instruction */
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&& ((mode == 5) || (mode >=12)) ){ /* With 32-bit displacement */
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len = 8;
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} else {
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len = 4;
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}
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if ( noprint ){
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return len;
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}
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if ( (mem_tab[i].name == NULL) || (mode == 6) ){
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invalid( word1 );
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return len;
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}
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fprintf( stream, "%s\t", mem_tab[i].name );
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reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */
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reg2 = reg_names[ (word1 >> 14) & 0x1f ];
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reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */
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offset = word1 & 0xfff; /* MEMA only */
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switch ( mem_tab[i].numops ){
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case 2: /* LOAD INSTRUCTION */
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if ( mode & 4 ){ /* MEMB FORMAT */
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ea( memaddr, mode, reg2, reg3, word1, word2 );
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fprintf( stream, ",%s", reg1 );
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} else { /* MEMA FORMAT */
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fprintf( stream, "0x%x", offset );
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if (mode & 8) {
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fprintf( stream, "(%s)", reg2 );
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}
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fprintf( stream, ",%s", reg1 );
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}
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break;
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case -2: /* STORE INSTRUCTION */
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if ( mode & 4 ){ /* MEMB FORMAT */
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fprintf( stream, "%s,", reg1 );
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ea( memaddr, mode, reg2, reg3, word1, word2 );
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} else { /* MEMA FORMAT */
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fprintf( stream, "%s,0x%x", reg1, offset );
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if (mode & 8) {
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fprintf( stream, "(%s)", reg2 );
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}
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}
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break;
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case 1: /* BX/CALLX INSTRUCTION */
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if ( mode & 4 ){ /* MEMB FORMAT */
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ea( memaddr, mode, reg2, reg3, word1, word2 );
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} else { /* MEMA FORMAT */
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fprintf( stream, "0x%x", offset );
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if (mode & 8) {
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fprintf( stream, "(%s)", reg2 );
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}
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}
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break;
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}
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return len;
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}
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/****************************************/
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/* REG format */
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/****************************************/
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static void
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reg( word1 )
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unsigned long word1;
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{
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int i, j;
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int opcode;
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int fp;
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int m1, m2, m3;
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int s1, s2;
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int src, src2, dst;
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char *mnemp;
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/* This lookup table is too sparse to make it worth typing in, but not
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* so large as to make a sparse array necessary. We allocate the
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* table at runtime, initialize all entries to empty, and copy the
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* real ones in from an initialization table.
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*
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* NOTE: In this table, the meaning of 'numops' is:
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* 1: single operand, which is NOT a destination.
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* -1: single operand, which IS a destination.
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* 2: 2 operands, the 2nd of which is NOT a destination.
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* -2: 2 operands, the 2nd of which IS a destination.
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* 3: 3 operands
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*
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* If an opcode mnemonic begins with "F", it is a floating-point
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* opcode (the "F" is not printed).
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*/
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static struct tabent *reg_tab = NULL;
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static struct { int opcode; char *name; char numops; } reg_init[] = {
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#define REG_MIN 0x580
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0x580, "notbit", 3,
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0x581, "and", 3,
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0x582, "andnot", 3,
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0x583, "setbit", 3,
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0x584, "notand", 3,
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0x586, "xor", 3,
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0x587, "or", 3,
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0x588, "nor", 3,
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0x589, "xnor", 3,
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0x58a, "not", -2,
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0x58b, "ornot", 3,
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0x58c, "clrbit", 3,
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0x58d, "notor", 3,
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0x58e, "nand", 3,
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0x58f, "alterbit", 3,
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0x590, "addo", 3,
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0x591, "addi", 3,
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0x592, "subo", 3,
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0x593, "subi", 3,
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0x598, "shro", 3,
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0x59a, "shrdi", 3,
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0x59b, "shri", 3,
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0x59c, "shlo", 3,
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0x59d, "rotate", 3,
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0x59e, "shli", 3,
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0x5a0, "cmpo", 2,
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0x5a1, "cmpi", 2,
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0x5a2, "concmpo", 2,
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0x5a3, "concmpi", 2,
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0x5a4, "cmpinco", 3,
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0x5a5, "cmpinci", 3,
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0x5a6, "cmpdeco", 3,
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0x5a7, "cmpdeci", 3,
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||
0x5ac, "scanbyte", 2,
|
||
0x5ae, "chkbit", 2,
|
||
0x5b0, "addc", 3,
|
||
0x5b2, "subc", 3,
|
||
0x5cc, "mov", -2,
|
||
0x5d8, "eshro", 3,
|
||
0x5dc, "movl", -2,
|
||
0x5ec, "movt", -2,
|
||
0x5fc, "movq", -2,
|
||
0x600, "synmov", 2,
|
||
0x601, "synmovl", 2,
|
||
0x602, "synmovq", 2,
|
||
0x603, "cmpstr", 3,
|
||
0x604, "movqstr", 3,
|
||
0x605, "movstr", 3,
|
||
0x610, "atmod", 3,
|
||
0x612, "atadd", 3,
|
||
0x613, "inspacc", -2,
|
||
0x614, "ldphy", -2,
|
||
0x615, "synld", -2,
|
||
0x617, "fill", 3,
|
||
0x630, "sdma", 3,
|
||
0x631, "udma", 0,
|
||
0x640, "spanbit", -2,
|
||
0x641, "scanbit", -2,
|
||
0x642, "daddc", 3,
|
||
0x643, "dsubc", 3,
|
||
0x644, "dmovt", -2,
|
||
0x645, "modac", 3,
|
||
0x646, "condrec", -2,
|
||
0x650, "modify", 3,
|
||
0x651, "extract", 3,
|
||
0x654, "modtc", 3,
|
||
0x655, "modpc", 3,
|
||
0x656, "receive", -2,
|
||
0x659, "sysctl", 3,
|
||
0x660, "calls", 1,
|
||
0x662, "send", 3,
|
||
0x663, "sendserv", 1,
|
||
0x664, "resumprcs", 1,
|
||
0x665, "schedprcs", 1,
|
||
0x666, "saveprcs", 0,
|
||
0x668, "condwait", 1,
|
||
0x669, "wait", 1,
|
||
0x66a, "signal", 1,
|
||
0x66b, "mark", 0,
|
||
0x66c, "fmark", 0,
|
||
0x66d, "flushreg", 0,
|
||
0x66f, "syncf", 0,
|
||
0x670, "emul", 3,
|
||
0x671, "ediv", 3,
|
||
0x673, "ldtime", -1,
|
||
0x674, "Fcvtir", -2,
|
||
0x675, "Fcvtilr", -2,
|
||
0x676, "Fscalerl", 3,
|
||
0x677, "Fscaler", 3,
|
||
0x680, "Fatanr", 3,
|
||
0x681, "Flogepr", 3,
|
||
0x682, "Flogr", 3,
|
||
0x683, "Fremr", 3,
|
||
0x684, "Fcmpor", 2,
|
||
0x685, "Fcmpr", 2,
|
||
0x688, "Fsqrtr", -2,
|
||
0x689, "Fexpr", -2,
|
||
0x68a, "Flogbnr", -2,
|
||
0x68b, "Froundr", -2,
|
||
0x68c, "Fsinr", -2,
|
||
0x68d, "Fcosr", -2,
|
||
0x68e, "Ftanr", -2,
|
||
0x68f, "Fclassr", 1,
|
||
0x690, "Fatanrl", 3,
|
||
0x691, "Flogeprl", 3,
|
||
0x692, "Flogrl", 3,
|
||
0x693, "Fremrl", 3,
|
||
0x694, "Fcmporl", 2,
|
||
0x695, "Fcmprl", 2,
|
||
0x698, "Fsqrtrl", -2,
|
||
0x699, "Fexprl", -2,
|
||
0x69a, "Flogbnrl", -2,
|
||
0x69b, "Froundrl", -2,
|
||
0x69c, "Fsinrl", -2,
|
||
0x69d, "Fcosrl", -2,
|
||
0x69e, "Ftanrl", -2,
|
||
0x69f, "Fclassrl", 1,
|
||
0x6c0, "Fcvtri", -2,
|
||
0x6c1, "Fcvtril", -2,
|
||
0x6c2, "Fcvtzri", -2,
|
||
0x6c3, "Fcvtzril", -2,
|
||
0x6c9, "Fmovr", -2,
|
||
0x6d9, "Fmovrl", -2,
|
||
0x6e1, "Fmovre", -2,
|
||
0x6e2, "Fcpysre", 3,
|
||
0x6e3, "Fcpyrsre", 3,
|
||
0x701, "mulo", 3,
|
||
0x708, "remo", 3,
|
||
0x70b, "divo", 3,
|
||
0x741, "muli", 3,
|
||
0x748, "remi", 3,
|
||
0x749, "modi", 3,
|
||
0x74b, "divi", 3,
|
||
0x78b, "Fdivr", 3,
|
||
0x78c, "Fmulr", 3,
|
||
0x78d, "Fsubr", 3,
|
||
0x78f, "Faddr", 3,
|
||
0x79b, "Fdivrl", 3,
|
||
0x79c, "Fmulrl", 3,
|
||
0x79d, "Fsubrl", 3,
|
||
0x79f, "Faddrl", 3,
|
||
#define REG_MAX 0x79f
|
||
#define REG_SIZ ((REG_MAX-REG_MIN+1) * sizeof(struct tabent))
|
||
0, NULL, 0
|
||
};
|
||
|
||
if ( reg_tab == NULL ){
|
||
reg_tab = (struct tabent *) xmalloc( REG_SIZ );
|
||
bzero( reg_tab, REG_SIZ );
|
||
for ( i = 0; reg_init[i].opcode != 0; i++ ){
|
||
j = reg_init[i].opcode - REG_MIN;
|
||
reg_tab[j].name = reg_init[i].name;
|
||
reg_tab[j].numops = reg_init[i].numops;
|
||
}
|
||
}
|
||
|
||
opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf);
|
||
i = opcode - REG_MIN;
|
||
|
||
if ( (opcode<REG_MIN) || (opcode>REG_MAX) || (reg_tab[i].name==NULL) ){
|
||
invalid( word1 );
|
||
return;
|
||
}
|
||
|
||
mnemp = reg_tab[i].name;
|
||
if ( *mnemp == 'F' ){
|
||
fp = 1;
|
||
mnemp++;
|
||
} else {
|
||
fp = 0;
|
||
}
|
||
|
||
fputs( mnemp, stream );
|
||
|
||
s1 = (word1 >> 5) & 1;
|
||
s2 = (word1 >> 6) & 1;
|
||
m1 = (word1 >> 11) & 1;
|
||
m2 = (word1 >> 12) & 1;
|
||
m3 = (word1 >> 13) & 1;
|
||
src = word1 & 0x1f;
|
||
src2 = (word1 >> 14) & 0x1f;
|
||
dst = (word1 >> 19) & 0x1f;
|
||
|
||
if ( reg_tab[i].numops != 0 ){
|
||
putc( '\t', stream );
|
||
|
||
switch ( reg_tab[i].numops ){
|
||
case 1:
|
||
regop( m1, s1, src, fp );
|
||
break;
|
||
case -1:
|
||
dstop( m3, dst, fp );
|
||
break;
|
||
case 2:
|
||
regop( m1, s1, src, fp );
|
||
putc( ',', stream );
|
||
regop( m2, s2, src2, fp );
|
||
break;
|
||
case -2:
|
||
regop( m1, s1, src, fp );
|
||
putc( ',', stream );
|
||
dstop( m3, dst, fp );
|
||
break;
|
||
case 3:
|
||
regop( m1, s1, src, fp );
|
||
putc( ',', stream );
|
||
regop( m2, s2, src2, fp );
|
||
putc( ',', stream );
|
||
dstop( m3, dst, fp );
|
||
break;
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
/*
|
||
* Print out effective address for memb instructions.
|
||
*/
|
||
static void
|
||
ea( memaddr, mode, reg2, reg3, word1, word2 )
|
||
unsigned long memaddr;
|
||
int mode;
|
||
char *reg2, *reg3;
|
||
unsigned int word2;
|
||
{
|
||
int scale;
|
||
static int scale_tab[] = { 1, 2, 4, 8, 16 };
|
||
|
||
scale = (word1 >> 7) & 0x07;
|
||
if ( (scale > 4) || ((word1 >> 5) & 0x03 != 0) ){
|
||
invalid( word1 );
|
||
return;
|
||
}
|
||
scale = scale_tab[scale];
|
||
|
||
switch (mode) {
|
||
case 4: /* (reg) */
|
||
fprintf( stream, "(%s)", reg2 );
|
||
break;
|
||
case 5: /* displ+8(ip) */
|
||
print_addr( word2+8+memaddr );
|
||
break;
|
||
case 7: /* (reg)[index*scale] */
|
||
if (scale == 1) {
|
||
fprintf( stream, "(%s)[%s]", reg2, reg3 );
|
||
} else {
|
||
fprintf( stream, "(%s)[%s*%d]",reg2,reg3,scale);
|
||
}
|
||
break;
|
||
case 12: /* displacement */
|
||
print_addr( word2 );
|
||
break;
|
||
case 13: /* displ(reg) */
|
||
print_addr( word2 );
|
||
fprintf( stream, "(%s)", reg2 );
|
||
break;
|
||
case 14: /* displ[index*scale] */
|
||
print_addr( word2 );
|
||
if (scale == 1) {
|
||
fprintf( stream, "[%s]", reg3 );
|
||
} else {
|
||
fprintf( stream, "[%s*%d]", reg3, scale );
|
||
}
|
||
break;
|
||
case 15: /* displ(reg)[index*scale] */
|
||
print_addr( word2 );
|
||
if (scale == 1) {
|
||
fprintf( stream, "(%s)[%s]", reg2, reg3 );
|
||
} else {
|
||
fprintf( stream, "(%s)[%s*%d]",reg2,reg3,scale );
|
||
}
|
||
break;
|
||
default:
|
||
invalid( word1 );
|
||
return;
|
||
}
|
||
}
|
||
|
||
|
||
/************************************************/
|
||
/* Register Instruction Operand */
|
||
/************************************************/
|
||
static void
|
||
regop( mode, spec, reg, fp )
|
||
int mode, spec, reg, fp;
|
||
{
|
||
if ( fp ){ /* FLOATING POINT INSTRUCTION */
|
||
if ( mode == 1 ){ /* FP operand */
|
||
switch ( reg ){
|
||
case 0: fputs( "fp0", stream ); break;
|
||
case 1: fputs( "fp1", stream ); break;
|
||
case 2: fputs( "fp2", stream ); break;
|
||
case 3: fputs( "fp3", stream ); break;
|
||
case 16: fputs( "0f0.0", stream ); break;
|
||
case 22: fputs( "0f1.0", stream ); break;
|
||
default: putc( '?', stream ); break;
|
||
}
|
||
} else { /* Non-FP register */
|
||
fputs( reg_names[reg], stream );
|
||
}
|
||
} else { /* NOT FLOATING POINT */
|
||
if ( mode == 1 ){ /* Literal */
|
||
fprintf( stream, "%d", reg );
|
||
} else { /* Register */
|
||
if ( spec == 0 ){
|
||
fputs( reg_names[reg], stream );
|
||
} else {
|
||
fprintf( stream, "sf%d", reg );
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
/************************************************/
|
||
/* Register Instruction Destination Operand */
|
||
/************************************************/
|
||
static void
|
||
dstop( mode, reg, fp )
|
||
int mode, reg, fp;
|
||
{
|
||
/* 'dst' operand can't be a literal. On non-FP instructions, register
|
||
* mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
|
||
* sf registers are not allowed so m3 acts normally.
|
||
*/
|
||
if ( fp ){
|
||
regop( mode, 0, reg, fp );
|
||
} else {
|
||
regop( 0, mode, reg, fp );
|
||
}
|
||
}
|
||
|
||
|
||
static void
|
||
invalid( word1 )
|
||
int word1;
|
||
{
|
||
fprintf( stream, ".word\t0x%08x", word1 );
|
||
}
|
||
|
||
static void
|
||
print_addr(a)
|
||
{
|
||
fprintf( stream, "0x%x", a );
|
||
}
|
||
|
||
static void
|
||
put_abs( word1, word2 )
|
||
unsigned long word1, word2;
|
||
{
|
||
#ifdef IN_GDB
|
||
return;
|
||
#else
|
||
int len;
|
||
|
||
switch ( (word1 >> 28) & 0xf ){
|
||
case 0x8:
|
||
case 0x9:
|
||
case 0xa:
|
||
case 0xb:
|
||
case 0xc:
|
||
/* MEM format instruction */
|
||
len = mem( 0, word1, word2, 1 );
|
||
break;
|
||
default:
|
||
len = 4;
|
||
break;
|
||
}
|
||
|
||
if ( len == 8 ){
|
||
fprintf( stream, "%08x %08x\t", word1, word2 );
|
||
} else {
|
||
fprintf( stream, "%08x \t", word1 );
|
||
}
|
||
;
|
||
|
||
#endif
|
||
}
|