182 lines
3.1 KiB
C
182 lines
3.1 KiB
C
/* Misc. support for CPU family m32rbf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright 1996-2010 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#define WANT_CPU m32rbf
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#define WANT_CPU_M32RBF
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#include "sim-main.h"
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#include "cgen-ops.h"
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/* Get the value of h-pc. */
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USI
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m32rbf_h_pc_get (SIM_CPU *current_cpu)
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{
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return CPU (h_pc);
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}
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/* Set a value for h-pc. */
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void
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m32rbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
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{
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CPU (h_pc) = newval;
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}
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/* Get the value of h-gr. */
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SI
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m32rbf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
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{
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return CPU (h_gr[regno]);
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}
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/* Set a value for h-gr. */
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void
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m32rbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
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{
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CPU (h_gr[regno]) = newval;
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}
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/* Get the value of h-cr. */
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USI
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m32rbf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_CR (regno);
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}
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/* Set a value for h-cr. */
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void
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m32rbf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
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{
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SET_H_CR (regno, newval);
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}
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/* Get the value of h-accum. */
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DI
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m32rbf_h_accum_get (SIM_CPU *current_cpu)
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{
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return GET_H_ACCUM ();
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}
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/* Set a value for h-accum. */
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void
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m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
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{
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SET_H_ACCUM (newval);
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}
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/* Get the value of h-cond. */
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BI
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m32rbf_h_cond_get (SIM_CPU *current_cpu)
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{
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return CPU (h_cond);
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}
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/* Set a value for h-cond. */
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void
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m32rbf_h_cond_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_cond) = newval;
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}
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/* Get the value of h-psw. */
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UQI
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m32rbf_h_psw_get (SIM_CPU *current_cpu)
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{
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return GET_H_PSW ();
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}
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/* Set a value for h-psw. */
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void
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m32rbf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
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{
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SET_H_PSW (newval);
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}
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/* Get the value of h-bpsw. */
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UQI
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m32rbf_h_bpsw_get (SIM_CPU *current_cpu)
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{
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return CPU (h_bpsw);
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}
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/* Set a value for h-bpsw. */
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void
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m32rbf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_bpsw) = newval;
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}
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/* Get the value of h-bbpsw. */
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UQI
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m32rbf_h_bbpsw_get (SIM_CPU *current_cpu)
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{
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return CPU (h_bbpsw);
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}
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/* Set a value for h-bbpsw. */
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void
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m32rbf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_bbpsw) = newval;
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}
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/* Get the value of h-lock. */
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BI
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m32rbf_h_lock_get (SIM_CPU *current_cpu)
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{
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return CPU (h_lock);
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}
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/* Set a value for h-lock. */
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void
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m32rbf_h_lock_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_lock) = newval;
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}
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/* Record trace results for INSN. */
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void
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m32rbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
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int *indices, TRACE_RECORD *tr)
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{
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}
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