278 lines
6.5 KiB
C
278 lines
6.5 KiB
C
/* Functions specific to running gdb native on HPPA running Linux.
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Copyright 2004 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include "defs.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "gdb_string.h"
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#include <sys/procfs.h>
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#include <string.h>
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#include <asm/offsets.h>
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/* Prototypes for supply_gregset etc. */
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#include "gregset.h"
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/* These must match the order of the register names.
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Some sort of lookup table is needed because the offsets associated
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with the registers are all over the board. */
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static const int u_offsets[] =
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{
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/* general registers */
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-1,
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PT_GR1,
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PT_GR2,
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PT_GR3,
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PT_GR4,
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PT_GR5,
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PT_GR6,
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PT_GR7,
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PT_GR8,
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PT_GR9,
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PT_GR10,
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PT_GR11,
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PT_GR12,
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PT_GR13,
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PT_GR14,
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PT_GR15,
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PT_GR16,
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PT_GR17,
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PT_GR18,
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PT_GR19,
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PT_GR20,
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PT_GR21,
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PT_GR22,
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PT_GR23,
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PT_GR24,
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PT_GR25,
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PT_GR26,
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PT_GR27,
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PT_GR28,
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PT_GR29,
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PT_GR30,
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PT_GR31,
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PT_SAR,
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PT_IAOQ0,
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PT_IASQ0,
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PT_IAOQ1,
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PT_IASQ1,
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-1, /* eiem */
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PT_IIR,
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PT_ISR,
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PT_IOR,
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PT_PSW,
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-1, /* goto */
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PT_SR4,
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PT_SR0,
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PT_SR1,
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PT_SR2,
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PT_SR3,
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PT_SR5,
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PT_SR6,
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PT_SR7,
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-1, /* cr0 */
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-1, /* pid0 */
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-1, /* pid1 */
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-1, /* ccr */
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-1, /* pid2 */
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-1, /* pid3 */
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-1, /* cr24 */
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-1, /* cr25 */
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-1, /* cr26 */
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PT_CR27,
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-1, /* cr28 */
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-1, /* cr29 */
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-1, /* cr30 */
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/* Floating point regs. */
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PT_FR0, PT_FR0 + 4,
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PT_FR1, PT_FR1 + 4,
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PT_FR2, PT_FR2 + 4,
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PT_FR3, PT_FR3 + 4,
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PT_FR4, PT_FR4 + 4,
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PT_FR5, PT_FR5 + 4,
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PT_FR6, PT_FR6 + 4,
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PT_FR7, PT_FR7 + 4,
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PT_FR8, PT_FR8 + 4,
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PT_FR9, PT_FR9 + 4,
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PT_FR10, PT_FR10 + 4,
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PT_FR11, PT_FR11 + 4,
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PT_FR12, PT_FR12 + 4,
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PT_FR13, PT_FR13 + 4,
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PT_FR14, PT_FR14 + 4,
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PT_FR15, PT_FR15 + 4,
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PT_FR16, PT_FR16 + 4,
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PT_FR17, PT_FR17 + 4,
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PT_FR18, PT_FR18 + 4,
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PT_FR19, PT_FR19 + 4,
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PT_FR20, PT_FR20 + 4,
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PT_FR21, PT_FR21 + 4,
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PT_FR22, PT_FR22 + 4,
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PT_FR23, PT_FR23 + 4,
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PT_FR24, PT_FR24 + 4,
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PT_FR25, PT_FR25 + 4,
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PT_FR26, PT_FR26 + 4,
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PT_FR27, PT_FR27 + 4,
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PT_FR28, PT_FR28 + 4,
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PT_FR29, PT_FR29 + 4,
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PT_FR30, PT_FR30 + 4,
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PT_FR31, PT_FR31 + 4,
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};
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CORE_ADDR
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register_addr (int regno, CORE_ADDR blockend)
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{
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CORE_ADDR addr;
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if ((unsigned) regno >= NUM_REGS)
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error ("Invalid register number %d.", regno);
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if (u_offsets[regno] == -1)
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addr = 0;
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else
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{
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addr = (CORE_ADDR) u_offsets[regno];
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}
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return addr;
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}
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/*
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* Registers saved in a coredump:
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* gr0..gr31
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* sr0..sr7
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* iaoq0..iaoq1
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* iasq0..iasq1
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* sar, iir, isr, ior, ipsw
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* cr0, cr24..cr31
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* cr8,9,12,13
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* cr10, cr15
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*/
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#define GR_REGNUM(_n) (R0_REGNUM+_n)
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#define TR_REGNUM(_n) (TR0_REGNUM+_n)
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static const int greg_map[] =
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{
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GR_REGNUM(0), GR_REGNUM(1), GR_REGNUM(2), GR_REGNUM(3),
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GR_REGNUM(4), GR_REGNUM(5), GR_REGNUM(6), GR_REGNUM(7),
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GR_REGNUM(8), GR_REGNUM(9), GR_REGNUM(10), GR_REGNUM(11),
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GR_REGNUM(12), GR_REGNUM(13), GR_REGNUM(14), GR_REGNUM(15),
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GR_REGNUM(16), GR_REGNUM(17), GR_REGNUM(18), GR_REGNUM(19),
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GR_REGNUM(20), GR_REGNUM(21), GR_REGNUM(22), GR_REGNUM(23),
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GR_REGNUM(24), GR_REGNUM(25), GR_REGNUM(26), GR_REGNUM(27),
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GR_REGNUM(28), GR_REGNUM(29), GR_REGNUM(30), GR_REGNUM(31),
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SR4_REGNUM+1, SR4_REGNUM+2, SR4_REGNUM+3, SR4_REGNUM+4,
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SR4_REGNUM, SR4_REGNUM+5, SR4_REGNUM+6, SR4_REGNUM+7,
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PCOQ_HEAD_REGNUM, PCOQ_TAIL_REGNUM,
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PCSQ_HEAD_REGNUM, PCSQ_TAIL_REGNUM,
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SAR_REGNUM, IIR_REGNUM, ISR_REGNUM, IOR_REGNUM,
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IPSW_REGNUM, RCR_REGNUM,
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TR_REGNUM(0), TR_REGNUM(1), TR_REGNUM(2), TR_REGNUM(3),
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TR_REGNUM(4), TR_REGNUM(5), TR_REGNUM(6), TR_REGNUM(7),
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PID0_REGNUM, PID1_REGNUM, PID2_REGNUM, PID3_REGNUM,
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CCR_REGNUM, EIEM_REGNUM,
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};
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void
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supply_gregset (gdb_gregset_t *gregsetp)
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{
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int i;
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greg_t *regp = (elf_greg_t *) gregsetp;
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for (i = 0; i < sizeof (greg_map) / sizeof (greg_map[0]); i++, regp++)
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{
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int regno = greg_map[i];
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int size = register_size (current_gdbarch, regno);
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/* When running a 64 bit kernel, a greg_t may be larger than the
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actual register, so just pick off the LS bits of big-endian word. */
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supply_register (regno, ((char *) (regp + 1)) - size);
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}
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}
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void
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fill_gregset (gdb_gregset_t *gregsetp, int regno)
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{
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int i;
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greg_t *regp = (greg_t *) gregsetp;
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memset (gregsetp, 0, sizeof (*gregsetp));
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for (i = 0; i < sizeof (greg_map) / sizeof (greg_map[0]); i++, regp++)
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{
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int regi = greg_map[i];
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if (regno == -1 || regi == regno)
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{
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int rawsize = register_size (current_gdbarch, regi);
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regcache_collect (regi, ((char *) (regp + 1)) - rawsize);
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}
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}
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}
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/* Given a pointer to a floating point register set in /proc format
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(fpregset_t *), unpack the register contents and supply them as gdb's
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idea of the current floating point register values. */
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void
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supply_fpregset (gdb_fpregset_t *fpregsetp)
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{
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register int regi;
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char *from;
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for (regi = 0; regi <= 31; regi++)
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{
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from = (char *) &((*fpregsetp)[regi]);
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supply_register (2*regi + HPPA_FP0_REGNUM, from);
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supply_register (2*regi + HPPA_FP0_REGNUM + 1, from + 4);
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}
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}
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/* Given a pointer to a floating point register set in /proc format
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(fpregset_t *), update the register specified by REGNO from gdb's idea
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of the current floating point register set. If REGNO is -1, update
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them all. */
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void
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fill_fpregset (gdb_fpregset_t *fpregsetp, int regno)
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{
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int i;
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for (i = 0; i < NUM_REGS; i++)
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{
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if (regno == -1 || regno == i)
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{
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/* Gross. fpregset_t is double, registers[x] has single
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precision reg. */
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char *to = (char *) &((*fpregsetp)[(i - HPPA_FP0_REGNUM) / 2]);
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if ((i - HPPA_FP0_REGNUM) & 1)
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to += 4;
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regcache_collect (i, to);
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}
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}
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}
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