555 lines
19 KiB
Plaintext
555 lines
19 KiB
Plaintext
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003
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@c Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node M68K-Dependent
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@chapter M680x0 Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter M680x0 Dependent Features
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@end ifclear
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@cindex M680x0 support
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@menu
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* M68K-Opts:: M680x0 Options
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* M68K-Syntax:: Syntax
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* M68K-Moto-Syntax:: Motorola Syntax
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* M68K-Float:: Floating Point
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* M68K-Directives:: 680x0 Machine Directives
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* M68K-opcodes:: Opcodes
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@end menu
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@node M68K-Opts
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@section M680x0 Options
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@cindex options, M680x0
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@cindex M680x0 options
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The Motorola 680x0 version of @code{@value{AS}} has a few machine
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dependent options:
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@table @samp
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@cindex @samp{-l} option, M680x0
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@item -l
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You can use the @samp{-l} option to shorten the size of references to undefined
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symbols. If you do not use the @samp{-l} option, references to undefined
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symbols are wide enough for a full @code{long} (32 bits). (Since
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@code{@value{AS}} cannot know where these symbols end up, @code{@value{AS}} can
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only allocate space for the linker to fill in later. Since @code{@value{AS}}
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does not know how far away these symbols are, it allocates as much space as it
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can.) If you use this option, the references are only one word wide (16 bits).
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This may be useful if you want the object file to be as small as possible, and
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you know that the relevant symbols are always less than 17 bits away.
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@cindex @samp{--register-prefix-optional} option, M680x0
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@item --register-prefix-optional
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For some configurations, especially those where the compiler normally
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does not prepend an underscore to the names of user variables, the
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assembler requires a @samp{%} before any use of a register name. This
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is intended to let the assembler distinguish between C variables and
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functions named @samp{a0} through @samp{a7}, and so on. The @samp{%} is
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always accepted, but is not required for certain configurations, notably
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@samp{sun3}. The @samp{--register-prefix-optional} option may be used
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to permit omitting the @samp{%} even for configurations for which it is
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normally required. If this is done, it will generally be impossible to
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refer to C variables and functions with the same names as register
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names.
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@cindex @samp{--bitwise-or} option, M680x0
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@item --bitwise-or
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Normally the character @samp{|} is treated as a comment character, which
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means that it can not be used in expressions. The @samp{--bitwise-or}
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option turns @samp{|} into a normal character. In this mode, you must
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either use C style comments, or start comments with a @samp{#} character
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at the beginning of a line.
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@cindex @samp{--base-size-default-16}
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@cindex @samp{--base-size-default-32}
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@item --base-size-default-16 --base-size-default-32
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If you use an addressing mode with a base register without specifying
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the size, @code{@value{AS}} will normally use the full 32 bit value.
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For example, the addressing mode @samp{%a0@@(%d0)} is equivalent to
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@samp{%a0@@(%d0:l)}. You may use the @samp{--base-size-default-16}
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option to tell @code{@value{AS}} to default to using the 16 bit value.
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In this case, @samp{%a0@@(%d0)} is equivalent to @samp{%a0@@(%d0:w)}.
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You may use the @samp{--base-size-default-32} option to restore the
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default behaviour.
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@cindex @samp{--disp-size-default-16}
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@cindex @samp{--disp-size-default-32}
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@item --disp-size-default-16 --disp-size-default-32
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If you use an addressing mode with a displacement, and the value of the
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displacement is not known, @code{@value{AS}} will normally assume that
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the value is 32 bits. For example, if the symbol @samp{disp} has not
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been defined, @code{@value{AS}} will assemble the addressing mode
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@samp{%a0@@(disp,%d0)} as though @samp{disp} is a 32 bit value. You may
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use the @samp{--disp-size-default-16} option to tell @code{@value{AS}}
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to instead assume that the displacement is 16 bits. In this case,
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@code{@value{AS}} will assemble @samp{%a0@@(disp,%d0)} as though
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@samp{disp} is a 16 bit value. You may use the
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@samp{--disp-size-default-32} option to restore the default behaviour.
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@cindex @samp{--pcrel}
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@item --pcrel
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Always keep branches PC-relative. In the M680x0 architecture all branches
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are defined as PC-relative. However, on some processors they are limited
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to word displacements maximum. When @code{@value{AS}} needs a long branch
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that is not available, it normally emits an absolute jump instead. This
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option disables this substitution. When this option is given and no long
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branches are available, only word branches will be emitted. An error
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message will be generated if a word branch cannot reach its target. This
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option has no effect on 68020 and other processors that have long branches.
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@pxref{M68K-Branch,,Branch Improvement}.
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@cindex @samp{-m68000} and related options
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@cindex architecture options, M680x0
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@cindex M680x0 architecture options
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@item -m68000
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@code{@value{AS}} can assemble code for several different members of the
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Motorola 680x0 family. The default depends upon how @code{@value{AS}}
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was configured when it was built; normally, the default is to assemble
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code for the 68020 microprocessor. The following options may be used to
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change the default. These options control which instructions and
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addressing modes are permitted. The members of the 680x0 family are
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very similar. For detailed information about the differences, see the
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Motorola manuals.
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@table @samp
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@item -m68000
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@itemx -m68ec000
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@itemx -m68hc000
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@itemx -m68hc001
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@itemx -m68008
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@itemx -m68302
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@itemx -m68306
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@itemx -m68307
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@itemx -m68322
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@itemx -m68356
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Assemble for the 68000. @samp{-m68008}, @samp{-m68302}, and so on are synonyms
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for @samp{-m68000}, since the chips are the same from the point of view
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of the assembler.
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@item -m68010
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Assemble for the 68010.
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@item -m68020
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@itemx -m68ec020
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Assemble for the 68020. This is normally the default.
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@item -m68030
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@itemx -m68ec030
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Assemble for the 68030.
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@item -m68040
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@itemx -m68ec040
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Assemble for the 68040.
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@item -m68060
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@itemx -m68ec060
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Assemble for the 68060.
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@item -mcpu32
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@itemx -m68330
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@itemx -m68331
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@itemx -m68332
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@itemx -m68333
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@itemx -m68334
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@itemx -m68336
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@itemx -m68340
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@itemx -m68341
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@itemx -m68349
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@itemx -m68360
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Assemble for the CPU32 family of chips.
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@item -m5200
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@item -m5202
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@item -m5204
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@item -m5206
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@item -m5206e
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@item -m528x
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@item -m5307
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@item -m5407
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@item -mcfv4
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@item -mcfv4e
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Assemble for the ColdFire family of chips.
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@item -m68881
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@itemx -m68882
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Assemble 68881 floating point instructions. This is the default for the
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68020, 68030, and the CPU32. The 68040 and 68060 always support
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floating point instructions.
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@item -mno-68881
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Do not assemble 68881 floating point instructions. This is the default
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for 68000 and the 68010. The 68040 and 68060 always support floating
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point instructions, even if this option is used.
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@item -m68851
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Assemble 68851 MMU instructions. This is the default for the 68020,
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68030, and 68060. The 68040 accepts a somewhat different set of MMU
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instructions; @samp{-m68851} and @samp{-m68040} should not be used
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together.
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@item -mno-68851
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Do not assemble 68851 MMU instructions. This is the default for the
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68000, 68010, and the CPU32. The 68040 accepts a somewhat different set
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of MMU instructions.
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@end table
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@end table
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@node M68K-Syntax
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@section Syntax
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@cindex @sc{mit}
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This syntax for the Motorola 680x0 was developed at @sc{mit}.
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@cindex M680x0 syntax
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@cindex syntax, M680x0
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@cindex M680x0 size modifiers
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@cindex size modifiers, M680x0
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The 680x0 version of @code{@value{AS}} uses instructions names and
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syntax compatible with the Sun assembler. Intervening periods are
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ignored; for example, @samp{movl} is equivalent to @samp{mov.l}.
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In the following table @var{apc} stands for any of the address registers
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(@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the
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zero-address relative to the program counter (@samp{%zpc}), a suppressed
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address register (@samp{%za0} through @samp{%za7}), or it may be omitted
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entirely. The use of @var{size} means one of @samp{w} or @samp{l}, and
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it may be omitted, along with the leading colon, unless a scale is also
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specified. The use of @var{scale} means one of @samp{1}, @samp{2},
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@samp{4}, or @samp{8}, and it may always be omitted along with the
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leading colon.
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@cindex M680x0 addressing modes
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@cindex addressing modes, M680x0
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The following addressing modes are understood:
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@table @dfn
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@item Immediate
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@samp{#@var{number}}
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@item Data Register
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@samp{%d0} through @samp{%d7}
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@item Address Register
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@samp{%a0} through @samp{%a7}@*
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@samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer. @code{%a6}
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is also known as @samp{%fp}, the Frame Pointer.
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@item Address Register Indirect
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@samp{%a0@@} through @samp{%a7@@}
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@item Address Register Postincrement
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@samp{%a0@@+} through @samp{%a7@@+}
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@item Address Register Predecrement
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@samp{%a0@@-} through @samp{%a7@@-}
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@item Indirect Plus Offset
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@samp{@var{apc}@@(@var{number})}
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@item Index
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@samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})}
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The @var{number} may be omitted.
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@item Postindex
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@samp{@var{apc}@@(@var{number})@@(@var{onumber},@var{register}:@var{size}:@var{scale})}
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The @var{onumber} or the @var{register}, but not both, may be omitted.
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@item Preindex
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@samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})@@(@var{onumber})}
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The @var{number} may be omitted. Omitting the @var{register} produces
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the Postindex addressing mode.
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@item Absolute
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@samp{@var{symbol}}, or @samp{@var{digits}}, optionally followed by
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@samp{:b}, @samp{:w}, or @samp{:l}.
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@end table
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@node M68K-Moto-Syntax
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@section Motorola Syntax
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@cindex Motorola syntax for the 680x0
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@cindex alternate syntax for the 680x0
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The standard Motorola syntax for this chip differs from the syntax
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already discussed (@pxref{M68K-Syntax,,Syntax}). @code{@value{AS}} can
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accept Motorola syntax for operands, even if @sc{mit} syntax is used for
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other operands in the same instruction. The two kinds of syntax are
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fully compatible.
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In the following table @var{apc} stands for any of the address registers
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(@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the
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zero-address relative to the program counter (@samp{%zpc}), or a
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suppressed address register (@samp{%za0} through @samp{%za7}). The use
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of @var{size} means one of @samp{w} or @samp{l}, and it may always be
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omitted along with the leading dot. The use of @var{scale} means one of
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@samp{1}, @samp{2}, @samp{4}, or @samp{8}, and it may always be omitted
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along with the leading asterisk.
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The following additional addressing modes are understood:
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@table @dfn
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@item Address Register Indirect
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@samp{(%a0)} through @samp{(%a7)}@*
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@samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer. @code{%a6}
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is also known as @samp{%fp}, the Frame Pointer.
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@item Address Register Postincrement
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@samp{(%a0)+} through @samp{(%a7)+}
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@item Address Register Predecrement
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@samp{-(%a0)} through @samp{-(%a7)}
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@item Indirect Plus Offset
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@samp{@var{number}(@var{%a0})} through @samp{@var{number}(@var{%a7})},
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or @samp{@var{number}(@var{%pc})}.
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The @var{number} may also appear within the parentheses, as in
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@samp{(@var{number},@var{%a0})}. When used with the @var{pc}, the
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@var{number} may be omitted (with an address register, omitting the
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@var{number} produces Address Register Indirect mode).
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@item Index
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@samp{@var{number}(@var{apc},@var{register}.@var{size}*@var{scale})}
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The @var{number} may be omitted, or it may appear within the
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parentheses. The @var{apc} may be omitted. The @var{register} and the
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@var{apc} may appear in either order. If both @var{apc} and
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@var{register} are address registers, and the @var{size} and @var{scale}
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are omitted, then the first register is taken as the base register, and
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the second as the index register.
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@item Postindex
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@samp{([@var{number},@var{apc}],@var{register}.@var{size}*@var{scale},@var{onumber})}
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The @var{onumber}, or the @var{register}, or both, may be omitted.
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Either the @var{number} or the @var{apc} may be omitted, but not both.
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@item Preindex
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@samp{([@var{number},@var{apc},@var{register}.@var{size}*@var{scale}],@var{onumber})}
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The @var{number}, or the @var{apc}, or the @var{register}, or any two of
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them, may be omitted. The @var{onumber} may be omitted. The
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@var{register} and the @var{apc} may appear in either order. If both
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@var{apc} and @var{register} are address registers, and the @var{size}
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and @var{scale} are omitted, then the first register is taken as the
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base register, and the second as the index register.
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@end table
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@node M68K-Float
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@section Floating Point
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@cindex floating point, M680x0
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@cindex M680x0 floating point
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Packed decimal (P) format floating literals are not supported.
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Feel free to add the code!
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The floating point formats generated by directives are these.
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@table @code
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@cindex @code{float} directive, M680x0
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@item .float
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@code{Single} precision floating point constants.
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@cindex @code{double} directive, M680x0
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@item .double
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@code{Double} precision floating point constants.
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@cindex @code{extend} directive M680x0
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@cindex @code{ldouble} directive M680x0
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@item .extend
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@itemx .ldouble
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@code{Extended} precision (@code{long double}) floating point constants.
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@end table
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@node M68K-Directives
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@section 680x0 Machine Directives
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@cindex M680x0 directives
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@cindex directives, M680x0
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In order to be compatible with the Sun assembler the 680x0 assembler
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understands the following directives.
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@table @code
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@cindex @code{data1} directive, M680x0
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@item .data1
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This directive is identical to a @code{.data 1} directive.
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@cindex @code{data2} directive, M680x0
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@item .data2
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This directive is identical to a @code{.data 2} directive.
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@cindex @code{even} directive, M680x0
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@item .even
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This directive is a special case of the @code{.align} directive; it
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aligns the output to an even byte boundary.
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@cindex @code{skip} directive, M680x0
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@item .skip
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This directive is identical to a @code{.space} directive.
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@end table
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@need 2000
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@node M68K-opcodes
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@section Opcodes
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@cindex M680x0 opcodes
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@cindex opcodes, M680x0
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@cindex instruction set, M680x0
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@c doc@cygnus.com: I don't see any point in the following
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@c paragraph. Bugs are bugs; how does saying this
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@c help anyone?
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@ignore
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Danger: Several bugs have been found in the opcode table (and
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fixed). More bugs may exist. Be careful when using obscure
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instructions.
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@end ignore
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@menu
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* M68K-Branch:: Branch Improvement
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* M68K-Chars:: Special Characters
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@end menu
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@node M68K-Branch
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@subsection Branch Improvement
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@cindex pseudo-opcodes, M680x0
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@cindex M680x0 pseudo-opcodes
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@cindex branch improvement, M680x0
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@cindex M680x0 branch improvement
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Certain pseudo opcodes are permitted for branch instructions.
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They expand to the shortest branch instruction that reach the
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target. Generally these mnemonics are made by substituting @samp{j} for
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@samp{b} at the start of a Motorola mnemonic.
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The following table summarizes the pseudo-operations. A @code{*} flags
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cases that are more fully described after the table:
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@smallexample
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Displacement
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+------------------------------------------------------------
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| 68020 68000/10, not PC-relative OK
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Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP **
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+------------------------------------------------------------
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jbsr |bsrs bsrw bsrl jsr
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jra |bras braw bral jmp
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* jXX |bXXs bXXw bXXl bNXs;jmp
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* dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp
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fjXX | N/A fbXXw fbXXl N/A
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XX: condition
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NX: negative of condition XX
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@end smallexample
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@center @code{*}---see full description below
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@center @code{**}---this expansion mode is disallowed by @samp{--pcrel}
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@table @code
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@item jbsr
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@itemx jra
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These are the simplest jump pseudo-operations; they always map to one
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particular machine instruction, depending on the displacement to the
|
|
branch target. This instruction will be a byte or word branch is that
|
|
is sufficient. Otherwise, a long branch will be emitted if available.
|
|
If no long branches are available and the @samp{--pcrel} option is not
|
|
given, an absolute long jump will be emitted instead. If no long
|
|
branches are available, the @samp{--pcrel} option is given, and a word
|
|
branch cannot reach the target, an error message is generated.
|
|
|
|
In addition to standard branch operands, @code{@value{AS}} allows these
|
|
pseudo-operations to have all operands that are allowed for jsr and jmp,
|
|
substituting these instructions if the operand given is not valid for a
|
|
branch instruction.
|
|
|
|
@item j@var{XX}
|
|
Here, @samp{j@var{XX}} stands for an entire family of pseudo-operations,
|
|
where @var{XX} is a conditional branch or condition-code test. The full
|
|
list of pseudo-ops in this family is:
|
|
@smallexample
|
|
jhi jls jcc jcs jne jeq jvc
|
|
jvs jpl jmi jge jlt jgt jle
|
|
@end smallexample
|
|
|
|
Usually, each of these pseudo-operations expands to a single branch
|
|
instruction. However, if a word branch is not sufficient, no long branches
|
|
are available, and the @samp{--pcrel} option is not given, @code{@value{AS}}
|
|
issues a longer code fragment in terms of @var{NX}, the opposite condition
|
|
to @var{XX}. For example, under these conditions:
|
|
@smallexample
|
|
j@var{XX} foo
|
|
@end smallexample
|
|
gives
|
|
@smallexample
|
|
b@var{NX}s oof
|
|
jmp foo
|
|
oof:
|
|
@end smallexample
|
|
|
|
@item db@var{XX}
|
|
The full family of pseudo-operations covered here is
|
|
@smallexample
|
|
dbhi dbls dbcc dbcs dbne dbeq dbvc
|
|
dbvs dbpl dbmi dbge dblt dbgt dble
|
|
dbf dbra dbt
|
|
@end smallexample
|
|
|
|
Motorola @samp{db@var{XX}} instructions allow word displacements only. When
|
|
a word displacement is sufficient, each of these pseudo-operations expands
|
|
to the corresponding Motorola instruction. When a word displacement is not
|
|
sufficient and long branches are available, when the source reads
|
|
@samp{db@var{XX} foo}, @code{@value{AS}} emits
|
|
@smallexample
|
|
db@var{XX} oo1
|
|
bras oo2
|
|
oo1:bral foo
|
|
oo2:
|
|
@end smallexample
|
|
|
|
If, however, long branches are not available and the @samp{--pcrel} option is
|
|
not given, @code{@value{AS}} emits
|
|
@smallexample
|
|
db@var{XX} oo1
|
|
bras oo2
|
|
oo1:jmp foo
|
|
oo2:
|
|
@end smallexample
|
|
|
|
@item fj@var{XX}
|
|
This family includes
|
|
@smallexample
|
|
fjne fjeq fjge fjlt fjgt fjle fjf
|
|
fjt fjgl fjgle fjnge fjngl fjngle fjngt
|
|
fjnle fjnlt fjoge fjogl fjogt fjole fjolt
|
|
fjor fjseq fjsf fjsne fjst fjueq fjuge
|
|
fjugt fjule fjult fjun
|
|
@end smallexample
|
|
|
|
Each of these pseudo-operations always expands to a single Motorola
|
|
coprocessor branch instruction, word or long. All Motorola coprocessor
|
|
branch instructions allow both word and long displacements.
|
|
|
|
@end table
|
|
|
|
@node M68K-Chars
|
|
@subsection Special Characters
|
|
|
|
@cindex special characters, M680x0
|
|
@cindex M680x0 immediate character
|
|
@cindex immediate character, M680x0
|
|
@cindex M680x0 line comment character
|
|
@cindex line comment character, M680x0
|
|
@cindex comments, M680x0
|
|
The immediate character is @samp{#} for Sun compatibility. The
|
|
line-comment character is @samp{|} (unless the @samp{--bitwise-or}
|
|
option is used). If a @samp{#} appears at the beginning of a line, it
|
|
is treated as a comment unless it looks like @samp{# line file}, in
|
|
which case it is treated normally.
|
|
|