841 lines
24 KiB
C
841 lines
24 KiB
C
/* dv-m68hc11tim.c -- Simulation of the 68HC11 timer devices.
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Copyright (C) 1999-2015 Free Software Foundation, Inc.
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Written by Stephane Carrez (stcarrez@nerim.fr)
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(From a driver model Contributed by Cygnus Solutions.)
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This file is part of the program GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sim-main.h"
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#include "hw-main.h"
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#include "sim-assert.h"
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#include <limits.h>
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/* DEVICE
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m68hc11tim - m68hc11 timer devices
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DESCRIPTION
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Implements the m68hc11 timer as described in Chapter 10
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of the pink book.
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PROPERTIES
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none
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PORTS
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reset (input)
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Reset the timer device. This port must be connected to
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the cpu-reset output port.
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capture (input)
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Input capture. This port must be connected to the input
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captures. It latches the current TCNT free running counter
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into one of the three input capture registers.
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*/
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/* port ID's */
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enum
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{
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RESET_PORT,
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CAPTURE
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};
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static const struct hw_port_descriptor m68hc11tim_ports[] =
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{
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{ "reset", RESET_PORT, 0, input_port, },
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{ "capture", CAPTURE, 0, input_port, },
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{ NULL, },
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};
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/* Timer Controller information. */
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struct m68hc11tim
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{
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unsigned long cop_delay;
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unsigned long rti_delay;
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unsigned long ovf_delay;
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signed64 clock_prescaler;
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signed64 tcnt_adjust;
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signed64 cop_prev_interrupt;
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signed64 rti_prev_interrupt;
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/* Periodic timers. */
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struct hw_event *rti_timer_event;
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struct hw_event *cop_timer_event;
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struct hw_event *tof_timer_event;
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struct hw_event *cmp_timer_event;
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};
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc. */
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static hw_io_read_buffer_method m68hc11tim_io_read_buffer;
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static hw_io_write_buffer_method m68hc11tim_io_write_buffer;
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static hw_port_event_method m68hc11tim_port_event;
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static hw_ioctl_method m68hc11tim_ioctl;
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#define M6811_TIMER_FIRST_REG (M6811_TCTN)
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#define M6811_TIMER_LAST_REG (M6811_PACNT)
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static void
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attach_m68hc11tim_regs (struct hw *me,
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struct m68hc11tim *controller)
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{
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hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
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M6811_TIMER_FIRST_REG,
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M6811_TIMER_LAST_REG - M6811_TIMER_FIRST_REG + 1,
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me);
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}
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static void
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m68hc11tim_finish (struct hw *me)
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{
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struct m68hc11tim *controller;
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controller = HW_ZALLOC (me, struct m68hc11tim);
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set_hw_data (me, controller);
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set_hw_io_read_buffer (me, m68hc11tim_io_read_buffer);
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set_hw_io_write_buffer (me, m68hc11tim_io_write_buffer);
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set_hw_ports (me, m68hc11tim_ports);
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set_hw_port_event (me, m68hc11tim_port_event);
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#ifdef set_hw_ioctl
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set_hw_ioctl (me, m68hc11tim_ioctl);
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#else
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me->to_ioctl = m68hc11tim_ioctl;
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#endif
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/* Preset defaults. */
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controller->clock_prescaler = 1;
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controller->tcnt_adjust = 0;
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/* Attach ourself to our parent bus. */
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attach_m68hc11tim_regs (me, controller);
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}
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/* An event arrives on an interrupt port. */
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static void
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m68hc11tim_port_event (struct hw *me,
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int my_port,
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struct hw *source,
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int source_port,
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int level)
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{
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SIM_DESC sd;
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struct m68hc11tim *controller;
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sim_cpu *cpu;
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unsigned8 val;
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unsigned16 tcnt;
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controller = hw_data (me);
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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switch (my_port)
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{
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case RESET_PORT:
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{
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HW_TRACE ((me, "Timer reset"));
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/* Cancel all timer events. */
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if (controller->rti_timer_event)
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{
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hw_event_queue_deschedule (me, controller->rti_timer_event);
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controller->rti_timer_event = 0;
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controller->rti_prev_interrupt = 0;
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}
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if (controller->cop_timer_event)
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{
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hw_event_queue_deschedule (me, controller->cop_timer_event);
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controller->cop_timer_event = 0;
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controller->cop_prev_interrupt = 0;
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}
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if (controller->tof_timer_event)
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{
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hw_event_queue_deschedule (me, controller->tof_timer_event);
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controller->tof_timer_event = 0;
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}
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if (controller->cmp_timer_event)
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{
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hw_event_queue_deschedule (me, controller->cmp_timer_event);
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controller->cmp_timer_event = 0;
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}
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/* Reset the state of Timer registers. This also restarts
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the timer events (overflow and RTI clock). The pending
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flags (TFLG2) must be cleared explicitly here. */
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val = 0;
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cpu->ios[M6811_TFLG2] = 0;
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m68hc11tim_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_TMSK2, 1);
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m68hc11tim_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_PACTL, 1);
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break;
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}
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case CAPTURE:
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tcnt = (uint16) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
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/ controller->clock_prescaler);
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switch (level)
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{
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case M6811_TIC1:
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case M6811_TIC2:
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case M6811_TIC3:
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cpu->ios[level] = tcnt >> 8;
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cpu->ios[level + 1] = tcnt;
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break;
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default:
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hw_abort (me, "Invalid event parameter %d", level);
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break;
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}
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break;
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default:
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hw_abort (me, "Event on unknown port %d", my_port);
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break;
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}
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}
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enum event_type
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{
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COP_EVENT,
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RTI_EVENT,
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OVERFLOW_EVENT,
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COMPARE_EVENT
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};
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void
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m68hc11tim_timer_event (struct hw *me, void *data)
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{
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SIM_DESC sd;
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struct m68hc11tim *controller;
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sim_cpu *cpu;
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enum event_type type;
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unsigned long delay;
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struct hw_event **eventp;
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int check_interrupt = 0;
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unsigned mask;
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unsigned flags;
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unsigned long tcnt_internal;
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unsigned long tcnt, tcnt_prev;
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signed64 tcnt_insn_end;
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signed64 tcnt_insn_start;
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int i;
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sim_events *events;
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controller = hw_data (me);
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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type = (enum event_type) ((long) data) & 0x0FF;
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events = STATE_EVENTS (sd);
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delay = 0;
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switch (type)
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{
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case COP_EVENT:
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eventp = &controller->cop_timer_event;
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delay = controller->cop_delay;
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delay = controller->cop_prev_interrupt + controller->cop_delay;
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controller->cop_prev_interrupt = delay;
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delay = delay - cpu->cpu_absolute_cycle;
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check_interrupt = 1;
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delay += events->nr_ticks_to_process;
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break;
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case RTI_EVENT:
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eventp = &controller->rti_timer_event;
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delay = controller->rti_prev_interrupt + controller->rti_delay;
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if (((long) (data) & 0x0100) == 0)
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{
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cpu->ios[M6811_TFLG2] |= M6811_RTIF;
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check_interrupt = 1;
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controller->rti_prev_interrupt = delay;
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delay += controller->rti_delay;
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}
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delay = delay - cpu->cpu_absolute_cycle;
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delay += events->nr_ticks_to_process;
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break;
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case OVERFLOW_EVENT:
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/* Compute the 68HC11 internal free running counter. */
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tcnt_internal = (cpu->cpu_absolute_cycle - controller->tcnt_adjust);
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/* We must take into account the prescaler that comes
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before the counter (it's a power of 2). */
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tcnt_internal &= 0x0ffff * controller->clock_prescaler;
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/* Compute the time when the overflow will occur. It occurs when
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the counter increments from 0x0ffff to 0x10000 (and thus resets). */
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delay = (0x10000 * controller->clock_prescaler) - tcnt_internal;
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/* The 'nr_ticks_to_process' will be subtracted when the event
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is scheduled. */
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delay += events->nr_ticks_to_process;
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eventp = &controller->tof_timer_event;
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if (((long) (data) & 0x100) == 0)
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{
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cpu->ios[M6811_TFLG2] |= M6811_TOF;
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check_interrupt = 1;
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}
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break;
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case COMPARE_EVENT:
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/* Compute value of TCNT register (64-bit precision) at beginning
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and end of instruction. */
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tcnt_insn_end = (cpu->cpu_absolute_cycle - controller->tcnt_adjust);
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tcnt_insn_start = (tcnt_insn_end - cpu->cpu_current_cycle);
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/* TCNT value at beginning of current instruction. */
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tcnt_prev = (tcnt_insn_start / controller->clock_prescaler) & 0x0ffff;
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/* TCNT value at end of current instruction. */
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tcnt = (tcnt_insn_end / controller->clock_prescaler) & 0x0ffff;
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/* We must take into account the prescaler that comes
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before the counter (it's a power of 2). */
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tcnt_internal = tcnt_insn_end;
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tcnt_internal &= 0x0ffff * controller->clock_prescaler;
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flags = cpu->ios[M6811_TMSK1];
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mask = 0x80;
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delay = 65536 * controller->clock_prescaler;
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/* Scan each output compare register to see if one matches
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the free running counter. Set the corresponding OCi flag
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if the output compare is enabled. */
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for (i = M6811_TOC1; i <= M6811_TOC5; i += 2, mask >>= 1)
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{
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unsigned long compare;
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compare = (cpu->ios[i] << 8) + cpu->ios[i + 1];
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/* See if compare is reached; handle wrap arround. */
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if ((compare >= tcnt_prev && compare <= tcnt && tcnt_prev < tcnt)
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|| (compare >= tcnt_prev && tcnt_prev > tcnt)
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|| (compare < tcnt && tcnt_prev > tcnt))
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{
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unsigned dt;
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if (compare > tcnt)
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dt = 0x10000 - compare - tcnt;
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else
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dt = tcnt - compare;
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cpu->ios[M6811_TFLG1] |= mask;
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/* Raise interrupt now at the correct CPU cycle so that
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we can find the interrupt latency. */
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cpu->cpu_absolute_cycle -= dt;
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interrupts_update_pending (&cpu->cpu_interrupts);
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cpu->cpu_absolute_cycle += dt;
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}
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/* Compute how many times for the next match.
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Use the internal counter value to take into account the
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prescaler accurately. */
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compare = compare * controller->clock_prescaler;
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if (compare > tcnt_internal)
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compare = compare - tcnt_internal;
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else
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compare = compare - tcnt_internal
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+ 65536 * controller->clock_prescaler;
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if (compare < delay)
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delay = compare;
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}
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/* Deactivate the compare timer if no output compare is enabled. */
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if ((flags & 0xF8) == 0)
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delay = 0;
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else
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delay += events->nr_ticks_to_process;
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eventp = &controller->cmp_timer_event;
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break;
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default:
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eventp = 0;
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break;
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}
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if (*eventp)
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{
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hw_event_queue_deschedule (me, *eventp);
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*eventp = 0;
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}
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if (delay != 0)
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{
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*eventp = hw_event_queue_schedule (me, delay,
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m68hc11tim_timer_event,
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(void*) type);
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}
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if (check_interrupt)
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interrupts_update_pending (&cpu->cpu_interrupts);
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}
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/* Descriptions of the Timer I/O ports. These descriptions are only used to
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give information of the Timer device under GDB. */
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io_reg_desc tmsk1_desc[] = {
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{ M6811_OC1I, "OC1I ", "Timer Output Compare 1 Interrupt Enable" },
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{ M6811_OC2I, "OC2I ", "Timer Output Compare 2 Interrupt Enable" },
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{ M6811_OC3I, "OC3I ", "Timer Output Compare 3 Interrupt Enable" },
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{ M6811_OC4I, "OC4I ", "Timer Output Compare 4 Interrupt Enable" },
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{ M6811_OC5I, "OC5I ", "Timer Input Capture 4 / Output Compare 5 Enable" },
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{ M6811_IC1I, "IC1I ", "Timer Input Capture 1 Interrupt Enable" },
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{ M6811_IC2I, "IC2I ", "Timer Input Capture 2 Interrupt Enable" },
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{ M6811_IC3I, "IC3I ", "Timer Input Capture 3 Interrupt Enable" },
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{ 0, 0, 0 }
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};
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io_reg_desc tflg1_desc[] = {
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{ M6811_OC1F, "OC1F ", "Timer Output Compare 1 Interrupt Flag" },
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{ M6811_OC2F, "OC2F ", "Timer Output Compare 2 Interrupt Flag" },
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{ M6811_OC3F, "OC3F ", "Timer Output Compare 3 Interrupt Flag" },
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{ M6811_OC4F, "OC4F ", "Timer Output Compare 4 Interrupt Flag" },
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{ M6811_OC5F, "OC5F ", "Timer Input Capture 4 / Output Compare 5 Flag" },
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{ M6811_IC1F, "IC1F ", "Timer Input Capture 1 Interrupt Flag" },
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{ M6811_IC2F, "IC2F ", "Timer Input Capture 2 Interrupt Flag" },
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{ M6811_IC3F, "IC3F ", "Timer Input Capture 3 Interrupt Flag" },
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{ 0, 0, 0 }
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};
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io_reg_desc tmsk2_desc[] = {
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{ M6811_TOI, "TOI ", "Timer Overflow Interrupt Enable" },
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{ M6811_RTII, "RTII ", "RTI Interrupt Enable" },
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{ M6811_PAOVI, "PAOVI ", "Pulse Accumulator Overflow Interrupt Enable" },
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{ M6811_PAII, "PAII ", "Pulse Accumulator Interrupt Enable" },
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{ M6811_PR1, "PR1 ", "Timer prescaler (PR1)" },
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{ M6811_PR0, "PR0 ", "Timer prescaler (PR0)" },
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{ M6811_TPR_1, "TPR_1 ", "Timer prescaler div 1" },
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{ M6811_TPR_4, "TPR_4 ", "Timer prescaler div 4" },
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{ M6811_TPR_8, "TPR_8 ", "Timer prescaler div 8" },
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{ M6811_TPR_16, "TPR_16", "Timer prescaler div 16" },
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{ 0, 0, 0 }
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};
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io_reg_desc tflg2_desc[] = {
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{ M6811_TOF, "TOF ", "Timer Overflow Bit" },
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{ M6811_RTIF, "RTIF ", "Read Time Interrupt Flag" },
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{ M6811_PAOVF, "PAOVF ", "Pulse Accumulator Overflow Interrupt Flag" },
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{ M6811_PAIF, "PAIF ", "Pulse Accumulator Input Edge" },
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{ 0, 0, 0 }
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};
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io_reg_desc pactl_desc[] = {
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{ M6811_DDRA7, "DDRA7 ", "Data Direction for Port A bit-7" },
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{ M6811_PAEN, "PAEN ", "Pulse Accumulator System Enable" },
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{ M6811_PAMOD, "PAMOD ", "Pulse Accumulator Mode" },
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{ M6811_PEDGE, "PEDGE ", "Pulse Accumulator Edge Control" },
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{ M6811_RTR1, "RTR1 ", "RTI Interrupt rate select (RTR1)" },
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{ M6811_RTR0, "RTR0 ", "RTI Interrupt rate select (RTR0)" },
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{ 0, 0, 0 }
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};
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static double
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to_realtime (sim_cpu *cpu, signed64 t)
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{
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return (double) (t) / (double) (cpu->cpu_frequency / 4);
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}
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const char*
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cycle_to_string (sim_cpu *cpu, signed64 t, int flags)
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{
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char time_buf[32];
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char cycle_buf[32];
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static char buf[64];
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time_buf[0] = 0;
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cycle_buf[0] = 0;
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if (flags & PRINT_TIME)
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{
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double dt;
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dt = to_realtime (cpu, t);
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if (dt < 0.001)
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sprintf (time_buf, " (%3.1f us)", dt * 1000000.0);
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else if (dt < 1.0)
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sprintf (time_buf, " (%3.1f ms)", dt * 1000.0);
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else
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sprintf (time_buf, " (%3.1f s)", dt);
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}
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if (flags & PRINT_CYCLE)
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sprintf (cycle_buf, " cycle%s",
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(t > 1 ? "s" : ""));
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if (t < LONG_MAX)
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sprintf (buf, "%9lu%s%s", (unsigned long) t, cycle_buf, time_buf);
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else
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sprintf (buf, "%llu%s%s", t, cycle_buf, time_buf);
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return buf;
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}
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static void
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m68hc11tim_print_timer (struct hw *me, const char *name,
|
|
struct hw_event *event)
|
|
{
|
|
SIM_DESC sd;
|
|
|
|
sd = hw_system (me);
|
|
if (event == 0)
|
|
{
|
|
sim_io_printf (sd, " No %s interrupt will be raised.\n", name);
|
|
}
|
|
else
|
|
{
|
|
signed64 t;
|
|
sim_cpu* cpu;
|
|
|
|
cpu = STATE_CPU (sd, 0);
|
|
|
|
t = hw_event_remain_time (me, event);
|
|
sim_io_printf (sd, " Next %s interrupt in %s\n",
|
|
name, cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE));
|
|
}
|
|
}
|
|
|
|
static void
|
|
m68hc11tim_info (struct hw *me)
|
|
{
|
|
SIM_DESC sd;
|
|
uint16 base = 0;
|
|
sim_cpu *cpu;
|
|
struct m68hc11tim *controller;
|
|
uint8 val;
|
|
uint16 val16;
|
|
|
|
sd = hw_system (me);
|
|
cpu = STATE_CPU (sd, 0);
|
|
controller = hw_data (me);
|
|
|
|
sim_io_printf (sd, "M68HC11 Timer:\n");
|
|
|
|
base = cpu_get_io_base (cpu);
|
|
|
|
/* Info for TIC1 */
|
|
val16 = (cpu->ios[M6811_TIC1_H] << 8) + cpu->ios[M6811_TIC1_L];
|
|
print_io_word (sd, "TIC1 ", 0, val16, base + M6811_TIC1);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Info for TIC2 */
|
|
val16 = (cpu->ios[M6811_TIC2_H] << 8) + cpu->ios[M6811_TIC2_L];
|
|
print_io_word (sd, "TIC2 ", 0, val16, base + M6811_TIC2);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Info for TIC3 */
|
|
val16 = (cpu->ios[M6811_TIC3_H] << 8) + cpu->ios[M6811_TIC3_L];
|
|
print_io_word (sd, "TIC3 ", 0, val16, base + M6811_TIC3);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Info for TOC1 */
|
|
val16 = (cpu->ios[M6811_TOC1_H] << 8) + cpu->ios[M6811_TOC1_L];
|
|
print_io_word (sd, "TOC1 ", 0, val16, base + M6811_TOC1);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Info for TOC2 */
|
|
val16 = (cpu->ios[M6811_TOC2_H] << 8) + cpu->ios[M6811_TOC2_L];
|
|
print_io_word (sd, "TOC2 ", 0, val16, base + M6811_TOC2);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Info for TOC3 */
|
|
val16 = (cpu->ios[M6811_TOC3_H] << 8) + cpu->ios[M6811_TOC3_L];
|
|
print_io_word (sd, "TOC3 ", 0, val16, base + M6811_TOC3);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Info for TOC4 */
|
|
val16 = (cpu->ios[M6811_TOC4_H] << 8) + cpu->ios[M6811_TOC4_L];
|
|
print_io_word (sd, "TOC4 ", 0, val16, base + M6811_TOC4);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Info for TOC5 */
|
|
val16 = (cpu->ios[M6811_TOC5_H] << 8) + cpu->ios[M6811_TOC5_L];
|
|
print_io_word (sd, "TOC5 ", 0, val16, base + M6811_TOC5);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Info for TMSK1 */
|
|
val = cpu->ios[M6811_TMSK1];
|
|
print_io_byte (sd, "TMSK1 ", tmsk1_desc, val, base + M6811_TMSK1);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Info for TFLG1 */
|
|
val = cpu->ios[M6811_TFLG1];
|
|
print_io_byte (sd, "TFLG1", tflg1_desc, val, base + M6811_TFLG1);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
val = cpu->ios[M6811_TMSK2];
|
|
print_io_byte (sd, "TMSK2 ", tmsk2_desc, val, base + M6811_TMSK2);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
val = cpu->ios[M6811_TFLG2];
|
|
print_io_byte (sd, "TFLG2", tflg2_desc, val, base + M6811_TFLG2);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
val = cpu->ios[M6811_PACTL];
|
|
print_io_byte (sd, "PACTL", pactl_desc, val, base + M6811_PACTL);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
val = cpu->ios[M6811_PACNT];
|
|
print_io_byte (sd, "PACNT", 0, val, base + M6811_PACNT);
|
|
sim_io_printf (sd, "\n");
|
|
|
|
/* Give info about the next timer interrupts. */
|
|
m68hc11tim_print_timer (me, "RTI", controller->rti_timer_event);
|
|
m68hc11tim_print_timer (me, "COP", controller->cop_timer_event);
|
|
m68hc11tim_print_timer (me, "OVERFLOW", controller->tof_timer_event);
|
|
m68hc11tim_print_timer (me, "COMPARE", controller->cmp_timer_event);
|
|
}
|
|
|
|
static int
|
|
m68hc11tim_ioctl (struct hw *me,
|
|
hw_ioctl_request request,
|
|
va_list ap)
|
|
{
|
|
m68hc11tim_info (me);
|
|
return 0;
|
|
}
|
|
|
|
/* generic read/write */
|
|
|
|
static unsigned
|
|
m68hc11tim_io_read_buffer (struct hw *me,
|
|
void *dest,
|
|
int space,
|
|
unsigned_word base,
|
|
unsigned nr_bytes)
|
|
{
|
|
SIM_DESC sd;
|
|
struct m68hc11tim *controller;
|
|
sim_cpu *cpu;
|
|
unsigned8 val;
|
|
unsigned cnt = 0;
|
|
|
|
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
|
|
|
|
sd = hw_system (me);
|
|
cpu = STATE_CPU (sd, 0);
|
|
controller = hw_data (me);
|
|
|
|
while (nr_bytes)
|
|
{
|
|
switch (base)
|
|
{
|
|
/* The cpu_absolute_cycle is updated after each instruction.
|
|
Reading in a 16-bit register will be split in two accesses
|
|
but this will be atomic within the simulator. */
|
|
case M6811_TCTN_H:
|
|
val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
|
/ (controller->clock_prescaler * 256));
|
|
break;
|
|
|
|
case M6811_TCTN_L:
|
|
val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
|
/ controller->clock_prescaler);
|
|
break;
|
|
|
|
default:
|
|
val = cpu->ios[base];
|
|
break;
|
|
}
|
|
*((unsigned8*) dest) = val;
|
|
dest = (char*) dest + 1;
|
|
base++;
|
|
nr_bytes--;
|
|
cnt++;
|
|
}
|
|
return cnt;
|
|
}
|
|
|
|
static unsigned
|
|
m68hc11tim_io_write_buffer (struct hw *me,
|
|
const void *source,
|
|
int space,
|
|
unsigned_word base,
|
|
unsigned nr_bytes)
|
|
{
|
|
SIM_DESC sd;
|
|
struct m68hc11tim *controller;
|
|
sim_cpu *cpu;
|
|
unsigned8 val, n;
|
|
signed64 adj;
|
|
int reset_compare = 0;
|
|
int reset_overflow = 0;
|
|
int cnt = 0;
|
|
|
|
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
|
|
|
|
sd = hw_system (me);
|
|
cpu = STATE_CPU (sd, 0);
|
|
controller = hw_data (me);
|
|
|
|
while (nr_bytes)
|
|
{
|
|
val = *((const unsigned8*) source);
|
|
switch (base)
|
|
{
|
|
/* Set the timer counter low part, trying to preserve the low part.
|
|
We compute the absolute cycle adjustment that we have to apply
|
|
to obtain the timer current value. Computation must be made
|
|
in 64-bit to avoid overflow problems. */
|
|
case M6811_TCTN_L:
|
|
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
|
/ (controller->clock_prescaler * (signed64) 256)) & 0x0FF;
|
|
adj = cpu->cpu_absolute_cycle
|
|
- (adj * controller->clock_prescaler * (signed64) 256)
|
|
- ((signed64) adj * controller->clock_prescaler);
|
|
controller->tcnt_adjust = adj;
|
|
reset_compare = 1;
|
|
reset_overflow = 1;
|
|
break;
|
|
|
|
case M6811_TCTN_H:
|
|
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
|
|
/ controller->clock_prescaler) & 0x0ff;
|
|
adj = cpu->cpu_absolute_cycle
|
|
- ((signed64) val * controller->clock_prescaler * (signed64) 256)
|
|
- (adj * controller->clock_prescaler);
|
|
controller->tcnt_adjust = adj;
|
|
reset_compare = 1;
|
|
reset_overflow = 1;
|
|
break;
|
|
|
|
case M6811_TMSK2:
|
|
|
|
/* Timer prescaler cannot be changed after 64 bus cycles. */
|
|
if (cpu->cpu_absolute_cycle >= 64)
|
|
{
|
|
val &= ~(M6811_PR1 | M6811_PR0);
|
|
val |= cpu->ios[M6811_TMSK2] & (M6811_PR1 | M6811_PR0);
|
|
}
|
|
switch (val & (M6811_PR1 | M6811_PR0))
|
|
{
|
|
case 0:
|
|
n = 1;
|
|
break;
|
|
case M6811_PR0:
|
|
n = 4;
|
|
break;
|
|
case M6811_PR1:
|
|
n = 8;
|
|
break;
|
|
default:
|
|
case M6811_PR1 | M6811_PR0:
|
|
n = 16;
|
|
break;
|
|
}
|
|
if (cpu->cpu_absolute_cycle < 64)
|
|
{
|
|
reset_overflow = 1;
|
|
controller->clock_prescaler = n;
|
|
}
|
|
cpu->ios[base] = val;
|
|
interrupts_update_pending (&cpu->cpu_interrupts);
|
|
break;
|
|
|
|
case M6811_PACTL:
|
|
n = (1 << ((val & (M6811_RTR1 | M6811_RTR0))));
|
|
cpu->ios[base] = val;
|
|
|
|
controller->rti_delay = (long) (n) * 8192;
|
|
m68hc11tim_timer_event (me, (void*) (RTI_EVENT| 0x100));
|
|
break;
|
|
|
|
case M6811_TFLG2:
|
|
val &= cpu->ios[M6811_TFLG2];
|
|
cpu->ios[M6811_TFLG2] &= ~val;
|
|
interrupts_update_pending (&cpu->cpu_interrupts);
|
|
break;
|
|
|
|
case M6811_TMSK1:
|
|
cpu->ios[M6811_TMSK1] = val;
|
|
interrupts_update_pending (&cpu->cpu_interrupts);
|
|
reset_compare = 1;
|
|
break;
|
|
|
|
case M6811_TFLG1:
|
|
val &= cpu->ios[M6811_TFLG1];
|
|
cpu->ios[M6811_TFLG1] &= ~val;
|
|
interrupts_update_pending (&cpu->cpu_interrupts);
|
|
break;
|
|
|
|
case M6811_TOC1:
|
|
case M6811_TOC2:
|
|
case M6811_TOC3:
|
|
case M6811_TOC4:
|
|
case M6811_TOC5:
|
|
cpu->ios[base] = val;
|
|
reset_compare = 1;
|
|
break;
|
|
|
|
case M6811_TCTL1:
|
|
case M6811_TCTL2:
|
|
cpu->ios[base] = val;
|
|
break;
|
|
|
|
default:
|
|
cpu->ios[base] = val;
|
|
break;
|
|
}
|
|
|
|
base++;
|
|
nr_bytes--;
|
|
cnt++;
|
|
source = (char*) source + 1;
|
|
}
|
|
|
|
/* Re-compute the next timer compare event. */
|
|
if (reset_compare)
|
|
{
|
|
m68hc11tim_timer_event (me, (void*) (COMPARE_EVENT));
|
|
}
|
|
if (reset_overflow)
|
|
{
|
|
m68hc11tim_timer_event (me, (void*) (OVERFLOW_EVENT| 0x100));
|
|
}
|
|
return cnt;
|
|
}
|
|
|
|
|
|
const struct hw_descriptor dv_m68hc11tim_descriptor[] = {
|
|
{ "m68hc11tim", m68hc11tim_finish },
|
|
{ "m68hc12tim", m68hc11tim_finish },
|
|
{ NULL },
|
|
};
|
|
|