291 lines
8.2 KiB
C
291 lines
8.2 KiB
C
/* Ravenscar PowerPC target support.
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Copyright (C) 2011-2018 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "ppc-tdep.h"
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#include "inferior.h"
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#include "ravenscar-thread.h"
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#include "ppc-ravenscar-thread.h"
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#define NO_OFFSET -1
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/* See ppc-tdep.h for register numbers. */
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static const int powerpc_context_offsets[] =
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{
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/* R0 - R32 */
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NO_OFFSET, 0, 4, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, 8, 12, 16,
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20, 24, 28, 32,
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36, 40, 44, 48,
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52, 56, 60, 64,
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68, 72, 76, 80,
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/* F0 - F31 */
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, 96, 104,
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112, 120, 128, 136,
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144, 152, 160, 168,
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176, 184, 192, 200,
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208, 216, 224, 232,
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/* PC, MSR, CR, LR */
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88, NO_OFFSET, 84, NO_OFFSET,
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/* CTR, XER, FPSCR */
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NO_OFFSET, NO_OFFSET, 240
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};
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static const int e500_context_offsets[] =
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{
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/* R0 - R32 */
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NO_OFFSET, 4, 12, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, 20, 28, 36,
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44, 52, 60, 68,
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76, 84, 92, 100,
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108, 116, 124, 132,
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140, 148, 156, 164,
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/* F0 - F31 */
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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/* PC, MSR, CR, LR */
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172, NO_OFFSET, 168, NO_OFFSET,
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/* CTR, XER, FPSCR, MQ */
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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/* Upper R0-R32. */
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NO_OFFSET, 0, 8, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
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NO_OFFSET, 16, 24, 32,
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40, 48, 56, 64,
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72, 80, 88, 96,
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104, 112, 120, 128,
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136, 144, 152, 160,
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/* ACC, FSCR */
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NO_OFFSET, 176
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};
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/* The register layout info. */
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struct ravenscar_reg_info
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{
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/* A table providing the offset relative to the context structure
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where each register is saved. */
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const int *context_offsets;
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/* The number of elements in the context_offsets table above. */
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int context_offsets_size;
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};
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/* supply register REGNUM, which has been saved on REGISTER_ADDR, to the
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regcache. */
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static void
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supply_register_at_address (struct regcache *regcache, int regnum,
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CORE_ADDR register_addr)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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int buf_size = register_size (gdbarch, regnum);
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gdb_byte *buf;
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buf = (gdb_byte *) alloca (buf_size);
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read_memory (register_addr, buf, buf_size);
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regcache->raw_supply (regnum, buf);
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}
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/* Return true if, for a non-running thread, REGNUM has been saved on the
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Thread_Descriptor. */
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static int
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register_in_thread_descriptor_p (const struct ravenscar_reg_info *reg_info,
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int regnum)
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{
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return (regnum < reg_info->context_offsets_size
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&& reg_info->context_offsets[regnum] != NO_OFFSET);
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}
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/* to_fetch_registers when inferior_ptid is different from the running
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thread. */
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static void
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ppc_ravenscar_generic_fetch_registers
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(const struct ravenscar_reg_info *reg_info,
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struct regcache *regcache, int regnum)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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const int num_regs = gdbarch_num_regs (gdbarch);
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int current_regnum;
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CORE_ADDR current_address;
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CORE_ADDR thread_descriptor_address;
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/* The tid is the thread_id field, which is a pointer to the thread. */
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thread_descriptor_address = (CORE_ADDR) inferior_ptid.tid ();
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/* Read registers. */
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for (current_regnum = 0; current_regnum < num_regs; current_regnum++)
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{
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if (register_in_thread_descriptor_p (reg_info, current_regnum))
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{
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current_address = thread_descriptor_address
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+ reg_info->context_offsets[current_regnum];
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supply_register_at_address (regcache, current_regnum,
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current_address);
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}
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}
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}
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/* to_prepare_to_store when inferior_ptid is different from the running
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thread. */
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static void
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ppc_ravenscar_generic_prepare_to_store (struct regcache *regcache)
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{
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/* Nothing to do. */
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}
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/* to_store_registers when inferior_ptid is different from the running
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thread. */
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static void
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ppc_ravenscar_generic_store_registers
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(const struct ravenscar_reg_info *reg_info,
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struct regcache *regcache, int regnum)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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int buf_size = register_size (gdbarch, regnum);
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gdb_byte buf[buf_size];
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ULONGEST register_address;
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if (register_in_thread_descriptor_p (reg_info, regnum))
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register_address
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= inferior_ptid.tid () + reg_info->context_offsets [regnum];
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else
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return;
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regcache->raw_collect (regnum, buf);
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write_memory (register_address,
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buf,
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buf_size);
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}
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/* The ravenscar_reg_info for most PowerPC targets. */
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static const struct ravenscar_reg_info ppc_reg_info =
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{
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powerpc_context_offsets,
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ARRAY_SIZE (powerpc_context_offsets),
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};
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/* Implement the to_fetch_registers ravenscar_arch_ops method
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for most PowerPC targets. */
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static void
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ppc_ravenscar_powerpc_fetch_registers (struct regcache *regcache, int regnum)
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{
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ppc_ravenscar_generic_fetch_registers (&ppc_reg_info, regcache, regnum);
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}
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/* Implement the to_store_registers ravenscar_arch_ops method
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for most PowerPC targets. */
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static void
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ppc_ravenscar_powerpc_store_registers (struct regcache *regcache, int regnum)
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{
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ppc_ravenscar_generic_store_registers (&ppc_reg_info, regcache, regnum);
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}
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/* The ravenscar_arch_ops vector for most PowerPC targets. */
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static struct ravenscar_arch_ops ppc_ravenscar_powerpc_ops =
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{
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ppc_ravenscar_powerpc_fetch_registers,
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ppc_ravenscar_powerpc_store_registers,
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ppc_ravenscar_generic_prepare_to_store
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};
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/* Register ppc_ravenscar_powerpc_ops in GDBARCH. */
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void
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register_ppc_ravenscar_ops (struct gdbarch *gdbarch)
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{
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set_gdbarch_ravenscar_ops (gdbarch, &ppc_ravenscar_powerpc_ops);
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}
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/* The ravenscar_reg_info for E500 targets. */
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static const struct ravenscar_reg_info e500_reg_info =
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{
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e500_context_offsets,
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ARRAY_SIZE (e500_context_offsets),
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};
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/* Implement the to_fetch_registers ravenscar_arch_ops method
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for E500 targets. */
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static void
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ppc_ravenscar_e500_fetch_registers (struct regcache *regcache, int regnum)
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{
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ppc_ravenscar_generic_fetch_registers (&e500_reg_info, regcache, regnum);
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}
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/* Implement the to_store_registers ravenscar_arch_ops method
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for E500 targets. */
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static void
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ppc_ravenscar_e500_store_registers (struct regcache *regcache, int regnum)
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{
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ppc_ravenscar_generic_store_registers (&e500_reg_info, regcache, regnum);
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}
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/* The ravenscar_arch_ops vector for E500 targets. */
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static struct ravenscar_arch_ops ppc_ravenscar_e500_ops =
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{
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ppc_ravenscar_e500_fetch_registers,
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ppc_ravenscar_e500_store_registers,
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ppc_ravenscar_generic_prepare_to_store
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};
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/* Register ppc_ravenscar_e500_ops in GDBARCH. */
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void
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register_e500_ravenscar_ops (struct gdbarch *gdbarch)
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{
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set_gdbarch_ravenscar_ops (gdbarch, &ppc_ravenscar_e500_ops);
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}
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