609 lines
15 KiB
C
609 lines
15 KiB
C
/* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly
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Copyright (C) 1999, 2000 Free Software Foundation, Inc.
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Written by Stephane Carrez (stcarrez@worldnet.fr)
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "ansidecl.h"
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#include "opcode/m68hc11.h"
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#include "dis-asm.h"
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static const char *const reg_name[] = {
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"X", "Y", "SP", "PC"
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};
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static const char *const reg_src_table[] = {
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"A", "B", "CCR", "TMP3", "D", "X", "Y", "SP"
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};
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static const char *const reg_dst_table[] = {
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"A", "B", "CCR", "TMP2", "D", "X", "Y", "SP"
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};
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#define OP_PAGE_MASK (M6811_OP_PAGE2|M6811_OP_PAGE3|M6811_OP_PAGE4)
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static int
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read_memory (memaddr, buffer, size, info)
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bfd_vma memaddr;
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bfd_byte *buffer;
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int size;
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struct disassemble_info *info;
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{
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int status;
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/* Get first byte. Only one at a time because we don't know the
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size of the insn. */
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status = (*info->read_memory_func) (memaddr, buffer, size, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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return 0;
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}
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/* Read the 68HC12 indexed operand byte and print the corresponding mode.
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Returns the number of bytes read or -1 if failure. */
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static int
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print_indexed_operand (memaddr, info, mov_insn)
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bfd_vma memaddr;
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struct disassemble_info *info;
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int mov_insn;
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{
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bfd_byte buffer[4];
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int reg;
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int status;
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short sval;
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int pos = 1;
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status = read_memory (memaddr, &buffer[0], 1, info);
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if (status != 0)
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{
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return status;
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}
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/* n,r with 5-bits signed constant. */
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if ((buffer[0] & 0x20) == 0)
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{
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reg = (buffer[0] >> 6) & 3;
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sval = (buffer[0] & 0x1f);
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if (sval & 0x10)
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sval |= 0xfff0;
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(*info->fprintf_func) (info->stream, "%d,%s",
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(int) sval, reg_name[reg]);
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}
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/* Auto pre/post increment/decrement. */
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else if ((buffer[0] & 0xc0) != 0xc0)
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{
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const char *mode;
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reg = (buffer[0] >> 6) & 3;
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sval = (buffer[0] & 0x0f);
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if (sval & 0x8)
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{
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sval |= 0xfff0;
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sval = -sval;
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mode = "-";
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}
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else
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{
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sval = sval + 1;
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mode = "+";
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}
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(*info->fprintf_func) (info->stream, "%d,%s%s%s",
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(int) sval,
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(buffer[0] & 0x10 ? "" : mode),
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reg_name[reg], (buffer[0] & 0x10 ? mode : ""));
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}
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/* [n,r] 16-bits offset indexed indirect. */
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else if ((buffer[0] & 0x07) == 3)
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{
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if (mov_insn)
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{
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(*info->fprintf_func) (info->stream, "<invalid op: 0x%x>",
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buffer[0] & 0x0ff);
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return 0;
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}
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reg = (buffer[0] >> 3) & 0x03;
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status = read_memory (memaddr + pos, &buffer[0], 2, info);
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if (status != 0)
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{
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return status;
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}
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pos += 2;
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sval = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
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(*info->fprintf_func) (info->stream, "[%u,%s]",
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sval & 0x0ffff, reg_name[reg]);
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}
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else if ((buffer[0] & 0x4) == 0)
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{
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if (mov_insn)
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{
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(*info->fprintf_func) (info->stream, "<invalid op: 0x%x>",
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buffer[0] & 0x0ff);
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return 0;
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}
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reg = (buffer[0] >> 3) & 0x03;
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status = read_memory (memaddr + pos,
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&buffer[1], (buffer[0] & 0x2 ? 2 : 1), info);
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if (status != 0)
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{
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return status;
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}
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if (buffer[0] & 2)
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{
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sval = ((buffer[1] << 8) | (buffer[2] & 0x0FF));
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sval &= 0x0FFFF;
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pos += 2;
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}
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else
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{
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sval = buffer[1] & 0x00ff;
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if (buffer[0] & 0x01)
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sval |= 0xff00;
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pos++;
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}
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(*info->fprintf_func) (info->stream, "%d,%s",
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(int) sval, reg_name[reg]);
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}
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else
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{
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reg = (buffer[0] >> 3) & 0x03;
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switch (buffer[0] & 3)
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{
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case 0:
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(*info->fprintf_func) (info->stream, "A,%s", reg_name[reg]);
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break;
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case 1:
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(*info->fprintf_func) (info->stream, "B,%s", reg_name[reg]);
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break;
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case 2:
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(*info->fprintf_func) (info->stream, "D,%s", reg_name[reg]);
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break;
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case 3:
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default:
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(*info->fprintf_func) (info->stream, "[D,%s]", reg_name[reg]);
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break;
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}
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}
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return pos;
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}
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/* Disassemble one instruction at address 'memaddr'. Returns the number
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of bytes used by that instruction. */
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static int
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print_insn (memaddr, info, arch)
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bfd_vma memaddr;
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struct disassemble_info *info;
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int arch;
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{
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int status;
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bfd_byte buffer[4];
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unsigned char code;
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long format, pos, i;
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short sval;
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const struct m68hc11_opcode *opcode;
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/* Get first byte. Only one at a time because we don't know the
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size of the insn. */
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status = read_memory (memaddr, buffer, 1, info);
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if (status != 0)
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{
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return status;
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}
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format = 0;
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code = buffer[0];
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pos = 0;
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/* Look for page2,3,4 opcodes. */
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if (code == M6811_OPCODE_PAGE2)
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{
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pos++;
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format = M6811_OP_PAGE2;
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}
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else if (code == M6811_OPCODE_PAGE3 && arch == cpu6811)
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{
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pos++;
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format = M6811_OP_PAGE3;
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}
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else if (code == M6811_OPCODE_PAGE4 && arch == cpu6811)
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{
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pos++;
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format = M6811_OP_PAGE4;
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}
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/* We are in page2,3,4; get the real opcode. */
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if (pos == 1)
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{
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status = read_memory (memaddr + pos, &buffer[1], 1, info);
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if (status != 0)
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{
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return status;
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}
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code = buffer[1];
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}
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/* Look first for a 68HC12 alias. All of them are 2-bytes long and
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in page 1. There is no operand to print. We read the second byte
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only when we have a possible match. */
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if ((arch & cpu6812) && format == 0)
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{
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int must_read = 1;
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/* Walk the alias table to find a code1+code2 match. */
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for (i = 0; i < m68hc12_num_alias; i++)
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{
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if (m68hc12_alias[i].code1 == code)
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{
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if (must_read)
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{
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status = read_memory (memaddr + pos + 1,
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&buffer[1], 1, info);
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if (status != 0)
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break;
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must_read = 1;
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}
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if (m68hc12_alias[i].code2 == (unsigned char) buffer[1])
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{
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(*info->fprintf_func) (info->stream, "%s",
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m68hc12_alias[i].name);
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return 2;
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}
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}
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}
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}
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pos++;
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/* Scan the opcode table until we find the opcode
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with the corresponding page. */
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opcode = m68hc11_opcodes;
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for (i = 0; i < m68hc11_num_opcodes; i++, opcode++)
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{
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int offset;
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if ((opcode->arch & arch) == 0)
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continue;
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if (opcode->opcode != code)
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continue;
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if ((opcode->format & OP_PAGE_MASK) != format)
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continue;
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if (opcode->format & M6812_OP_REG)
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{
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int j;
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int is_jump;
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if (opcode->format & M6811_OP_JUMP_REL)
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is_jump = 1;
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else
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is_jump = 0;
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status = read_memory (memaddr + pos, &buffer[0], 1, info);
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if (status != 0)
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{
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return status;
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}
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for (j = 0; i + j < m68hc11_num_opcodes; j++)
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{
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if ((opcode[j].arch & arch) == 0)
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continue;
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if (opcode[j].opcode != code)
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continue;
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if (is_jump)
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{
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if (!(opcode[j].format & M6811_OP_JUMP_REL))
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continue;
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if ((opcode[j].format & M6812_OP_IBCC_MARKER)
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&& (buffer[0] & 0xc0) != 0x80)
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continue;
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if ((opcode[j].format & M6812_OP_TBCC_MARKER)
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&& (buffer[0] & 0xc0) != 0x40)
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continue;
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if ((opcode[j].format & M6812_OP_DBCC_MARKER)
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&& (buffer[0] & 0xc0) != 0)
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continue;
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if ((opcode[j].format & M6812_OP_EQ_MARKER)
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&& (buffer[0] & 0x20) == 0)
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break;
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if (!(opcode[j].format & M6812_OP_EQ_MARKER)
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&& (buffer[0] & 0x20) != 0)
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break;
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continue;
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}
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if (opcode[j].format & M6812_OP_EXG_MARKER && buffer[0] & 0x80)
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break;
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if ((opcode[j].format & M6812_OP_SEX_MARKER)
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&& (((buffer[0] & 0x07) >= 3 && (buffer[0] & 7) <= 7))
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&& ((buffer[0] & 0x0f0) <= 0x20))
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break;
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if (opcode[j].format & M6812_OP_TFR_MARKER
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&& !(buffer[0] & 0x80))
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break;
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}
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if (i + j < m68hc11_num_opcodes)
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opcode = &opcode[j];
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}
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/* We have found the opcode. Extract the operand and print it. */
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
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format = opcode->format;
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if (format & (M6811_OP_MASK | M6811_OP_BITMASK
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| M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
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{
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(*info->fprintf_func) (info->stream, "\t");
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}
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/* The movb and movw must be handled in a special way... */
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offset = 0;
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if (format & (M6812_OP_IDX_P2 | M6812_OP_IND16_P2))
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{
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if ((format & M6812_OP_IDX_P2)
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&& (format & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_IND16)))
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offset = 1;
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}
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/* Operand with one more byte: - immediate, offset,
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direct-low address. */
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if (format &
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(M6811_OP_IMM8 | M6811_OP_IX | M6811_OP_IY | M6811_OP_DIRECT))
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{
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status = read_memory (memaddr + pos + offset, &buffer[0], 1, info);
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if (status != 0)
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{
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return status;
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}
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pos++;
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offset = -1;
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if (format & M6811_OP_IMM8)
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{
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(*info->fprintf_func) (info->stream, "#%d", (int) buffer[0]);
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format &= ~M6811_OP_IMM8;
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}
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else if (format & M6811_OP_IX)
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{
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/* Offsets are in range 0..255, print them unsigned. */
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(*info->fprintf_func) (info->stream, "%u,x", buffer[0] & 0x0FF);
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format &= ~M6811_OP_IX;
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}
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else if (format & M6811_OP_IY)
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{
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(*info->fprintf_func) (info->stream, "%u,y", buffer[0] & 0x0FF);
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format &= ~M6811_OP_IY;
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}
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else if (format & M6811_OP_DIRECT)
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{
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(*info->fprintf_func) (info->stream, "*");
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(*info->print_address_func) (buffer[0] & 0x0FF, info);
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format &= ~M6811_OP_DIRECT;
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}
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}
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#define M6812_INDEXED_FLAGS (M6812_OP_IDX|M6812_OP_IDX_1|M6812_OP_IDX_2)
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/* Analyze the 68HC12 indexed byte. */
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if (format & M6812_INDEXED_FLAGS)
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{
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status = print_indexed_operand (memaddr + pos, info, 0);
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if (status < 0)
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{
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return status;
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}
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pos += status;
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}
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/* 68HC12 dbcc/ibcc/tbcc operands. */
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if ((format & M6812_OP_REG) && (format & M6811_OP_JUMP_REL))
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{
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status = read_memory (memaddr + pos, &buffer[0], 2, info);
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if (status != 0)
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{
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return status;
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}
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(*info->fprintf_func) (info->stream, "%s,",
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reg_src_table[buffer[0] & 0x07]);
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sval = buffer[1] & 0x0ff;
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if (buffer[0] & 0x10)
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sval |= 0xff00;
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pos += 2;
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(*info->print_address_func) (memaddr + pos + sval, info);
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format &= ~(M6812_OP_REG | M6811_OP_JUMP_REL);
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}
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else if (format & (M6812_OP_REG | M6812_OP_REG_2))
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{
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status = read_memory (memaddr + pos, &buffer[0], 1, info);
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if (status != 0)
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{
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return status;
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}
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pos++;
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(*info->fprintf_func) (info->stream, "%s,%s",
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reg_src_table[(buffer[0] >> 4) & 7],
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reg_dst_table[(buffer[0] & 7)]);
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}
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/* M6811_OP_BITMASK and M6811_OP_JUMP_REL must be treated separately
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and in that order. The brset/brclr insn have a bitmask and then
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a relative branch offset. */
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if (format & M6811_OP_BITMASK)
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{
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status = read_memory (memaddr + pos, &buffer[0], 1, info);
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if (status != 0)
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{
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return status;
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}
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pos++;
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(*info->fprintf_func) (info->stream, " #$%02x%s",
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buffer[0] & 0x0FF,
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(format & M6811_OP_JUMP_REL ? " " : ""));
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format &= ~M6811_OP_BITMASK;
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}
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if (format & M6811_OP_JUMP_REL)
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{
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int val;
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status = read_memory (memaddr + pos, &buffer[0], 1, info);
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if (status != 0)
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{
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return status;
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}
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pos++;
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val = (buffer[0] & 0x80) ? buffer[0] | 0xFFFFFF00 : buffer[0];
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(*info->print_address_func) (memaddr + pos + val, info);
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format &= ~M6811_OP_JUMP_REL;
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}
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else if (format & M6812_OP_JUMP_REL16)
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{
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int val;
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status = read_memory (memaddr + pos, &buffer[0], 2, info);
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if (status != 0)
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{
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return status;
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}
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pos += 2;
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val = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
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if (val & 0x8000)
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val |= 0xffff0000;
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(*info->print_address_func) (memaddr + pos + val, info);
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format &= ~M6812_OP_JUMP_REL16;
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}
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if (format & (M6811_OP_IMM16 | M6811_OP_IND16))
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{
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int val;
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status = read_memory (memaddr + pos + offset, &buffer[0], 2, info);
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if (status != 0)
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{
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return status;
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}
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if (format & M6812_OP_IDX_P2)
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offset = -2;
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else
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offset = 0;
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pos += 2;
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val = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
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val &= 0x0FFFF;
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if (format & M6811_OP_IMM16)
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{
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format &= ~M6811_OP_IMM16;
|
|
(*info->fprintf_func) (info->stream, "#");
|
|
}
|
|
else
|
|
format &= ~M6811_OP_IND16;
|
|
|
|
(*info->print_address_func) (val, info);
|
|
}
|
|
|
|
if (format & M6812_OP_IDX_P2)
|
|
{
|
|
(*info->fprintf_func) (info->stream, ", ");
|
|
status = print_indexed_operand (memaddr + pos + offset, info, 1);
|
|
if (status < 0)
|
|
return status;
|
|
pos += status;
|
|
}
|
|
|
|
if (format & M6812_OP_IND16_P2)
|
|
{
|
|
int val;
|
|
|
|
(*info->fprintf_func) (info->stream, ", ");
|
|
|
|
status = read_memory (memaddr + pos + offset, &buffer[0], 2, info);
|
|
if (status != 0)
|
|
{
|
|
return status;
|
|
}
|
|
pos += 2;
|
|
|
|
val = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
|
|
val &= 0x0FFFF;
|
|
(*info->print_address_func) (val, info);
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
/* Consistency check. 'format' must be 0, so that we have handled
|
|
all formats; and the computed size of the insn must match the
|
|
opcode table content. */
|
|
if (format & ~(M6811_OP_PAGE4 | M6811_OP_PAGE3 | M6811_OP_PAGE2))
|
|
{
|
|
(*info->fprintf_func) (info->stream, "; Error, format: %x", format);
|
|
}
|
|
if (pos != opcode->size)
|
|
{
|
|
(*info->fprintf_func) (info->stream, "; Error, size: %d expect %d",
|
|
pos, opcode->size);
|
|
}
|
|
#endif
|
|
return pos;
|
|
}
|
|
|
|
/* Opcode not recognized. */
|
|
if (format == M6811_OP_PAGE2 && arch & cpu6812
|
|
&& ((code >= 0x30 && code <= 0x39) || (code >= 0x40 && code <= 0xff)))
|
|
(*info->fprintf_func) (info->stream, "trap\t#%d", code & 0x0ff);
|
|
|
|
else if (format == M6811_OP_PAGE2)
|
|
(*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x",
|
|
M6811_OPCODE_PAGE2, code);
|
|
else if (format == M6811_OP_PAGE3)
|
|
(*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x",
|
|
M6811_OPCODE_PAGE3, code);
|
|
else if (format == M6811_OP_PAGE4)
|
|
(*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x",
|
|
M6811_OPCODE_PAGE4, code);
|
|
else
|
|
(*info->fprintf_func) (info->stream, ".byte\t0x%02x", code);
|
|
|
|
return pos;
|
|
}
|
|
|
|
/* Disassemble one instruction at address 'memaddr'. Returns the number
|
|
of bytes used by that instruction. */
|
|
int
|
|
print_insn_m68hc11 (memaddr, info)
|
|
bfd_vma memaddr;
|
|
struct disassemble_info *info;
|
|
{
|
|
return print_insn (memaddr, info, cpu6811);
|
|
}
|
|
|
|
int
|
|
print_insn_m68hc12 (memaddr, info)
|
|
bfd_vma memaddr;
|
|
struct disassemble_info *info;
|
|
{
|
|
return print_insn (memaddr, info, cpu6812);
|
|
}
|