de52b9607d
GDB is currently crashing anytime we try to access the fs_base/gs_base
registers, either to read them, or to write them. This can be observed
under various scenarios:
- Explicit reference to those registers (eg: print $fs_base) --
probably relatively rare;
- Calling a function in the inferior, with the crash happening
because we are trying to read those registers in order to save
their value ahead of making the function call;
- Just a plain "info registers";
The crash was introduced by the following commit:
| commit 48aeef91c2
| Date: Mon Jun 26 18:14:43 2017 -0700
| Subject: Include the fs_base and gs_base registers in amd64 target descriptions.
The Windows-nat implementation was unfortunately not prepared to deal
with those new registers. In particular, the way it fetches registers
is done by using a table where the index is the register number, and
the value at that index is the offset in the area in the thread's CONTEXT
data where the corresponding register value is stored.
For instance, in amd64-windows-nat.c, we can find the mappings static
array containing the following 57 elements in it:
#define context_offset(x) (offsetof (CONTEXT, x))
static const int mappings[] =
{
context_offset (Rax),
[...]
context_offset (FloatSave.MxCsr)
};
That array is then used by windows_fetch_one_register via:
char *context_offset = ((char *) &th->context) + mappings[r];
The problem is that fs_base's register number is 172, which is
well past the end of the mappings array (57 elements in total).
We end up getting an undefined offset, which happens to be so large
that it then causes the address where we try to read the register
value (a little bit later) to be invalid, thus crashing GDB with
a SEGV.
This patch side-steps the issue entirely by removing support for
those registers in GDB on x86_64-windows, because a look at the
CONTEXT structure indicates no support for getting those registers.
A more comprehensive fix would patch the potential buffer overflow
of the mappings array, but this can be done as a separate commit.
gdb/ChangeLog:
* gdb/amd64-tdep.h (amd64_create_target_description): Add
"segments" parameter.
* gdb/amd64-tdep.c (amd64_none_init_abi, amd64_x32_none_init_abi)
(_initialize_amd64_tdep): Update call to
amd64_create_target_description.
(amd64_target_description): Add "segments" parameter. Adjust
the implementation to use it.
* gdb/amd64-linux-tdep.c (amd64_linux_read_description): Update
call to amd64_create_target_description.
* gdb/amd64-windows-tdep.c (amd64_windows_init_abi): Likewise.
* gdb/arch/amd64.h (amd64_create_target_description): Add
"segments" register.
* gdb/arch/amd64.c (amd64_create_target_description): Add
"segments" parameter. Call create_feature_i386_64bit_segments
only if SEGMENTS is true.
* gdb/gdbserver/win32-i386-low.c (i386_arch_setup): Update
call to amd64_create_target_description.
Tested on x86_64-windows using AdaCore's testsuite (by Joel Brobecker
<brobecker at adacore dot com>).
153 lines
5.1 KiB
C
153 lines
5.1 KiB
C
/* Target-dependent definitions for AMD64.
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Copyright (C) 2001-2018 Free Software Foundation, Inc.
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Contributed by Jiri Smid, SuSE Labs.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef AMD64_TDEP_H
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#define AMD64_TDEP_H
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struct gdbarch;
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struct frame_info;
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struct regcache;
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#include "i386-tdep.h"
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/* Register numbers of various important registers. */
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enum amd64_regnum
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{
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AMD64_RAX_REGNUM, /* %rax */
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AMD64_RBX_REGNUM, /* %rbx */
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AMD64_RCX_REGNUM, /* %rcx */
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AMD64_RDX_REGNUM, /* %rdx */
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AMD64_RSI_REGNUM, /* %rsi */
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AMD64_RDI_REGNUM, /* %rdi */
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AMD64_RBP_REGNUM, /* %rbp */
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AMD64_RSP_REGNUM, /* %rsp */
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AMD64_R8_REGNUM, /* %r8 */
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AMD64_R9_REGNUM, /* %r9 */
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AMD64_R10_REGNUM, /* %r10 */
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AMD64_R11_REGNUM, /* %r11 */
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AMD64_R12_REGNUM, /* %r12 */
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AMD64_R13_REGNUM, /* %r13 */
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AMD64_R14_REGNUM, /* %r14 */
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AMD64_R15_REGNUM, /* %r15 */
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AMD64_RIP_REGNUM, /* %rip */
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AMD64_EFLAGS_REGNUM, /* %eflags */
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AMD64_CS_REGNUM, /* %cs */
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AMD64_SS_REGNUM, /* %ss */
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AMD64_DS_REGNUM, /* %ds */
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AMD64_ES_REGNUM, /* %es */
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AMD64_FS_REGNUM, /* %fs */
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AMD64_GS_REGNUM, /* %gs */
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AMD64_ST0_REGNUM = 24, /* %st0 */
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AMD64_ST1_REGNUM, /* %st1 */
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AMD64_FCTRL_REGNUM = AMD64_ST0_REGNUM + 8,
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AMD64_FSTAT_REGNUM = AMD64_ST0_REGNUM + 9,
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AMD64_FTAG_REGNUM = AMD64_ST0_REGNUM + 10,
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AMD64_XMM0_REGNUM = 40, /* %xmm0 */
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AMD64_XMM1_REGNUM, /* %xmm1 */
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AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16,
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AMD64_YMM0H_REGNUM, /* %ymm0h */
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AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15,
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AMD64_BND0R_REGNUM = AMD64_YMM15H_REGNUM + 1,
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AMD64_BND3R_REGNUM = AMD64_BND0R_REGNUM + 3,
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AMD64_BNDCFGU_REGNUM,
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AMD64_BNDSTATUS_REGNUM,
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AMD64_XMM16_REGNUM,
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AMD64_XMM31_REGNUM = AMD64_XMM16_REGNUM + 15,
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AMD64_YMM16H_REGNUM,
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AMD64_YMM31H_REGNUM = AMD64_YMM16H_REGNUM + 15,
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AMD64_K0_REGNUM,
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AMD64_K7_REGNUM = AMD64_K0_REGNUM + 7,
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AMD64_ZMM0H_REGNUM,
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AMD64_ZMM31H_REGNUM = AMD64_ZMM0H_REGNUM + 31,
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AMD64_PKRU_REGNUM,
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AMD64_FSBASE_REGNUM,
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AMD64_GSBASE_REGNUM
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};
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/* Number of general purpose registers. */
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#define AMD64_NUM_GREGS 24
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#define AMD64_NUM_REGS (AMD64_GSBASE_REGNUM + 1)
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extern struct displaced_step_closure *amd64_displaced_step_copy_insn
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(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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extern void amd64_displaced_step_fixup (struct gdbarch *gdbarch,
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struct displaced_step_closure *closure,
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CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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/* Initialize the ABI for amd64. Uses DEFAULT_TDESC as fallback
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tdesc, if INFO does not specify one. */
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extern void amd64_init_abi (struct gdbarch_info info,
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struct gdbarch *gdbarch,
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const target_desc *default_tdesc);
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/* Initialize the ABI for x32. Uses DEFAULT_TDESC as fallback tdesc,
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if INFO does not specify one. */
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extern void amd64_x32_init_abi (struct gdbarch_info info,
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struct gdbarch *gdbarch,
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const target_desc *default_tdesc);
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extern const struct target_desc *amd64_target_description (uint64_t xcr0,
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bool segments);
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/* Fill register REGNUM in REGCACHE with the appropriate
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floating-point or SSE register value from *FXSAVE. If REGNUM is
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-1, do this for all registers. This function masks off any of the
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reserved bits in *FXSAVE. */
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extern void amd64_supply_fxsave (struct regcache *regcache, int regnum,
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const void *fxsave);
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/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
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extern void amd64_supply_xsave (struct regcache *regcache, int regnum,
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const void *xsave);
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/* Fill register REGNUM (if it is a floating-point or SSE register) in
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*FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
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all registers. This function doesn't touch any of the reserved
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bits in *FXSAVE. */
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extern void amd64_collect_fxsave (const struct regcache *regcache, int regnum,
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void *fxsave);
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/* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
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extern void amd64_collect_xsave (const struct regcache *regcache,
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int regnum, void *xsave, int gcore);
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/* Floating-point register set. */
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extern const struct regset amd64_fpregset;
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/* Variables exported from amd64-linux-tdep.c. */
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extern int amd64_linux_gregset_reg_offset[];
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/* Variables exported from amd64-nbsd-tdep.c. */
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extern int amd64nbsd_r_reg_offset[];
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/* Variables exported from amd64-obsd-tdep.c. */
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extern int amd64obsd_r_reg_offset[];
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/* Variables exported from amd64-fbsd-tdep.c. */
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extern CORE_ADDR amd64fbsd_sigtramp_start_addr;
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extern CORE_ADDR amd64fbsd_sigtramp_end_addr;
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extern int amd64fbsd_sc_reg_offset[];
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#endif /* amd64-tdep.h */
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