641 lines
14 KiB
C
641 lines
14 KiB
C
/* m6811_cpu.c -- 68HC11 CPU Emulation
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Copyright 1999, 2000 Free Software Foundation, Inc.
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Written by Stephane Carrez (stcarrez@worldnet.fr)
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sim-main.h"
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#include "sim-assert.h"
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#include "sim-module.h"
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#include "sim-options.h"
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void cpu_free_frame (sim_cpu* cpu, struct cpu_frame *frame);
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enum {
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OPTION_CPU_RESET = OPTION_START,
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OPTION_EMUL_OS,
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OPTION_CPU_CONFIG,
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OPTION_CPU_MODE
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};
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static DECLARE_OPTION_HANDLER (cpu_option_handler);
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static const OPTION cpu_options[] =
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{
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{ {"cpu-reset", no_argument, NULL, OPTION_CPU_RESET },
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'\0', NULL, "Reset the CPU",
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cpu_option_handler },
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{ {"emulos", no_argument, NULL, OPTION_EMUL_OS },
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'\0', NULL, "Emulate some OS system calls (read, write, ...)",
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cpu_option_handler },
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{ {"cpu-config", required_argument, NULL, OPTION_CPU_CONFIG },
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'\0', NULL, "Specify the initial CPU configuration register",
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cpu_option_handler },
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{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
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};
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static SIM_RC
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cpu_option_handler (SIM_DESC sd, sim_cpu *cpu,
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int opt, char *arg, int is_command)
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{
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sim_cpu *cpu;
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int val;
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cpu = STATE_CPU (sd, 0);
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switch (opt)
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{
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case OPTION_CPU_RESET:
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sim_board_reset (sd);
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break;
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case OPTION_EMUL_OS:
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cpu->cpu_emul_syscall = 1;
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break;
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case OPTION_CPU_CONFIG:
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if (sscanf(arg, "0x%x", &val) == 1
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|| sscanf(arg, "%d", &val) == 1)
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{
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cpu->cpu_config = val;
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cpu->cpu_use_local_config = 1;
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}
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else
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cpu->cpu_use_local_config = 0;
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break;
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case OPTION_CPU_MODE:
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break;
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}
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return SIM_RC_OK;
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}
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/* Tentative to keep track of the cpu frame. */
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struct cpu_frame*
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cpu_find_frame (sim_cpu *cpu, uint16 sp)
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{
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struct cpu_frame_list *flist;
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flist = cpu->cpu_frames;
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while (flist)
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{
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struct cpu_frame *frame;
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frame = flist->frame;
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while (frame)
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{
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if (frame->sp_low <= sp && frame->sp_high >= sp)
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{
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cpu->cpu_current_frame = flist;
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return frame;
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}
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frame = frame->up;
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}
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flist = flist->next;
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}
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return 0;
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}
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struct cpu_frame_list*
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cpu_create_frame_list (sim_cpu *cpu)
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{
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struct cpu_frame_list *flist;
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flist = (struct cpu_frame_list*) malloc (sizeof (struct cpu_frame_list));
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flist->frame = 0;
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flist->next = cpu->cpu_frames;
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flist->prev = 0;
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if (flist->next)
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flist->next->prev = flist;
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cpu->cpu_frames = flist;
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cpu->cpu_current_frame = flist;
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return flist;
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}
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void
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cpu_remove_frame_list (sim_cpu *cpu, struct cpu_frame_list *flist)
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{
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struct cpu_frame *frame;
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if (flist->prev == 0)
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cpu->cpu_frames = flist->next;
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else
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flist->prev->next = flist->next;
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if (flist->next)
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flist->next->prev = flist->prev;
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frame = flist->frame;
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while (frame)
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{
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struct cpu_frame* up = frame->up;
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cpu_free_frame (cpu, frame);
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frame = up;
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}
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free (flist);
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}
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struct cpu_frame*
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cpu_create_frame (sim_cpu *cpu, uint16 pc, uint16 sp)
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{
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struct cpu_frame *frame;
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frame = (struct cpu_frame*) malloc (sizeof(struct cpu_frame));
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frame->up = 0;
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frame->pc = pc;
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frame->sp_low = sp;
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frame->sp_high = sp;
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return frame;
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}
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void
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cpu_free_frame (sim_cpu *cpu, struct cpu_frame *frame)
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{
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free (frame);
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}
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uint16
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cpu_frame_reg (sim_cpu *cpu, uint16 rn)
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{
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struct cpu_frame *frame;
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if (cpu->cpu_current_frame == 0)
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return 0;
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frame = cpu->cpu_current_frame->frame;
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while (frame)
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{
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if (rn == 0)
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return frame->sp_high;
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frame = frame->up;
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rn--;
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}
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return 0;
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}
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void
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cpu_call (sim_cpu *cpu, uint16 addr)
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{
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#if HAVE_FRAME
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uint16 pc = cpu->cpu_insn_pc;
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uint16 sp;
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struct cpu_frame_list *flist;
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struct cpu_frame* frame;
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struct cpu_frame* new_frame;
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#endif
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cpu_set_pc (cpu, addr);
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#if HAVE_FRAME
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sp = cpu_get_sp (cpu);
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cpu->cpu_need_update_frame = 0;
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flist = cpu->cpu_current_frame;
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if (flist == 0)
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flist = cpu_create_frame_list (cpu);
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frame = flist->frame;
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if (frame && frame->sp_low > sp)
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frame->sp_low = sp;
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new_frame = cpu_create_frame (cpu, pc, sp);
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new_frame->up = frame;
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flist->frame = new_frame;
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#endif
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}
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void
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cpu_update_frame (sim_cpu *cpu, int do_create)
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{
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#if HAVE_FRAME
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struct cpu_frame *frame;
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frame = cpu_find_frame (cpu, cpu_get_sp (cpu));
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if (frame)
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{
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while (frame != cpu->cpu_current_frame->frame)
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{
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struct cpu_frame* up;
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up = cpu->cpu_current_frame->frame->up;
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cpu_free_frame (cpu, cpu->cpu_current_frame->frame);
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cpu->cpu_current_frame->frame = up;
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}
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return;
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}
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if (do_create)
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{
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cpu_create_frame_list (cpu);
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frame = cpu_create_frame (cpu, cpu_get_pc (cpu), cpu_get_sp (cpu));
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cpu->cpu_current_frame->frame = frame;
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}
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#endif
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}
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void
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cpu_return (sim_cpu *cpu)
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{
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#if HAVE_FRAME
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uint16 sp = cpu_get_sp (cpu);
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struct cpu_frame *frame;
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struct cpu_frame_list *flist;
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cpu->cpu_need_update_frame = 0;
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flist = cpu->cpu_current_frame;
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if (flist && flist->frame && flist->frame->up)
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{
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frame = flist->frame->up;
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if (frame->sp_low <= sp && frame->sp_high >= sp)
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{
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cpu_free_frame (cpu, flist->frame);
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flist->frame = frame;
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return;
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}
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}
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cpu_update_frame (cpu, 1);
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#endif
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}
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void
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cpu_print_frame (SIM_DESC sd, sim_cpu *cpu)
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{
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struct cpu_frame* frame;
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int level = 0;
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if (cpu->cpu_current_frame == 0 || cpu->cpu_current_frame->frame == 0)
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{
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sim_io_printf (sd, "No frame.\n");
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return;
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}
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sim_io_printf (sd, " # PC SP-L SP-H\n");
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frame = cpu->cpu_current_frame->frame;
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while (frame)
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{
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sim_io_printf (sd, "%3d 0x%04x 0x%04x 0x%04x\n",
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level, frame->pc, frame->sp_low, frame->sp_high);
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frame = frame->up;
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level++;
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}
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}
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/* Set the stack pointer and re-compute the current frame. */
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void
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cpu_set_sp (sim_cpu *cpu, uint16 val)
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{
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cpu->cpu_regs.sp = val;
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cpu_update_frame (cpu, 0);
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}
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int
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cpu_initialize (SIM_DESC sd, sim_cpu *cpu)
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{
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int result;
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sim_add_option_table (sd, 0, cpu_options);
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memset (&cpu->cpu_regs, 0, sizeof(cpu->cpu_regs));
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cpu->cpu_absolute_cycle = 0;
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cpu->cpu_current_cycle = 0;
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cpu->cpu_emul_syscall = 1;
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cpu->cpu_running = 1;
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cpu->cpu_stop_on_interrupt = 0;
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cpu->cpu_frequency = 8 * 1000 * 1000;
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cpu->cpu_frames = 0;
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cpu->cpu_current_frame = 0;
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cpu->cpu_use_elf_start = 0;
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cpu->cpu_elf_start = 0;
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cpu->cpu_use_local_config = 0;
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cpu->cpu_config = M6811_NOSEC | M6811_NOCOP | M6811_ROMON |
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M6811_EEON;
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result = interrupts_initialize (cpu);
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cpu->cpu_is_initialized = 1;
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return result;
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}
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/* Reinitialize the processor after a reset. */
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int
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cpu_reset (sim_cpu *cpu)
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{
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cpu->cpu_need_update_frame = 0;
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cpu->cpu_current_frame = 0;
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while (cpu->cpu_frames)
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cpu_remove_frame_list (cpu, cpu->cpu_frames);
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/* Initialize the config register.
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It is only initialized at reset time. */
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memset (cpu->ios, 0, sizeof (cpu->ios));
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cpu->ios[M6811_INIT] = 0x1;
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/* Output compare registers set to 0xFFFF. */
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cpu->ios[M6811_TOC1_H] = 0xFF;
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cpu->ios[M6811_TOC1_L] = 0xFF;
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cpu->ios[M6811_TOC2_H] = 0xFF;
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cpu->ios[M6811_TOC2_L] = 0xFF;
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cpu->ios[M6811_TOC3_H] = 0xFF;
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cpu->ios[M6811_TOC4_L] = 0xFF;
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cpu->ios[M6811_TOC5_H] = 0xFF;
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cpu->ios[M6811_TOC5_L] = 0xFF;
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/* Setup the processor registers. */
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memset (&cpu->cpu_regs, 0, sizeof(cpu->cpu_regs));
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cpu->cpu_absolute_cycle = 0;
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cpu->cpu_current_cycle = 0;
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cpu->cpu_is_initialized = 0;
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/* Reinitialize the CPU operating mode. */
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cpu->ios[M6811_HPRIO] = cpu->cpu_mode;
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return 0;
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}
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/* Reinitialize the processor after a reset. */
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int
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cpu_restart (sim_cpu *cpu)
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{
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uint16 addr;
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/* Get CPU starting address depending on the CPU mode. */
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if (cpu->cpu_use_elf_start == 0)
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{
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switch ((cpu->ios[M6811_HPRIO]) & (M6811_SMOD | M6811_MDA))
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{
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/* Single Chip */
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default:
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case 0 :
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addr = memory_read16 (cpu, 0xFFFE);
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break;
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/* Expanded Multiplexed */
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case M6811_MDA:
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addr = memory_read16 (cpu, 0xFFFE);
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break;
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/* Special Bootstrap */
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case M6811_SMOD:
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addr = 0;
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break;
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/* Factory Test */
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case M6811_MDA | M6811_SMOD:
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addr = memory_read16 (cpu, 0xFFFE);
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break;
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}
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}
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else
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{
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addr = cpu->cpu_elf_start;
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}
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/* Setup the processor registers. */
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cpu->cpu_insn_pc = addr;
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cpu->cpu_regs.pc = addr;
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cpu->cpu_regs.ccr = M6811_X_BIT | M6811_I_BIT | M6811_S_BIT;
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cpu->cpu_absolute_cycle = 0;
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cpu->cpu_is_initialized = 1;
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cpu->cpu_current_cycle = 0;
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cpu_call (cpu, addr);
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return 0;
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}
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void
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print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val, int mode)
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{
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while (desc->mask)
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{
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if (val & desc->mask)
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sim_io_printf (sd, "%s",
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mode == 0 ? desc->short_name : desc->long_name);
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desc++;
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}
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}
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void
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print_io_byte (SIM_DESC sd, const char *name, io_reg_desc *desc,
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uint8 val, uint16 addr)
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{
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sim_io_printf (sd, " %-9.9s @ 0x%04x 0x%02x ", name, addr, val);
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if (desc)
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print_io_reg_desc (sd, desc, val, 0);
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}
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void
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cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val)
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{
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cpu_set_ccr_V (proc, 0);
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cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
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cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
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}
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uint16
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cpu_fetch_relbranch (sim_cpu *cpu)
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{
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uint16 addr = (uint16) cpu_fetch8 (cpu);
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if (addr & 0x0080)
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{
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addr |= 0xFF00;
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}
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addr += cpu->cpu_regs.pc;
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return addr;
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}
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/* Push all the CPU registers (when an interruption occurs). */
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void
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cpu_push_all (sim_cpu *cpu)
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{
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cpu_push_uint16 (cpu, cpu->cpu_regs.pc);
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cpu_push_uint16 (cpu, cpu->cpu_regs.iy);
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cpu_push_uint16 (cpu, cpu->cpu_regs.ix);
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cpu_push_uint16 (cpu, cpu->cpu_regs.d);
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cpu_push_uint8 (cpu, cpu->cpu_regs.ccr);
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}
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/* Handle special instructions. */
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void
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cpu_special (sim_cpu *cpu, enum M6811_Special special)
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{
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switch (special)
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{
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case M6811_RTI:
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{
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uint8 ccr;
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ccr = cpu_pop_uint8 (cpu);
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cpu_set_ccr (cpu, ccr);
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cpu_set_d (cpu, cpu_pop_uint16 (cpu));
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cpu_set_x (cpu, cpu_pop_uint16 (cpu));
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cpu_set_y (cpu, cpu_pop_uint16 (cpu));
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cpu_set_pc (cpu, cpu_pop_uint16 (cpu));
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cpu_return (cpu);
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break;
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}
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case M6811_WAI:
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/* In the ELF-start mode, we are in a special mode where
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the WAI corresponds to an exit. */
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if (cpu->cpu_use_elf_start)
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{
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cpu_set_pc (cpu, cpu->cpu_insn_pc);
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sim_engine_halt (CPU_STATE (cpu), cpu,
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NULL, NULL_CIA, sim_exited,
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cpu_get_d (cpu));
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return;
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}
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/* SCz: not correct... */
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cpu_push_all (cpu);
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break;
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case M6811_SWI:
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interrupts_raise (&cpu->cpu_interrupts, M6811_INT_SWI);
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interrupts_process (&cpu->cpu_interrupts);
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break;
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case M6811_EMUL_SYSCALL:
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case M6811_ILLEGAL:
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if (cpu->cpu_emul_syscall)
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{
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uint8 op = memory_read8 (cpu,
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cpu_get_pc (cpu) - 1);
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if (op == 0x41)
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{
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cpu_set_pc (cpu, cpu->cpu_insn_pc);
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sim_engine_halt (CPU_STATE (cpu), cpu,
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NULL, NULL_CIA, sim_exited,
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cpu_get_d (cpu));
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return;
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}
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else
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{
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emul_os (op, cpu);
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}
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return;
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}
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interrupts_raise (&cpu->cpu_interrupts, M6811_INT_ILLEGAL);
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interrupts_process (&cpu->cpu_interrupts);
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break;
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case M6811_TEST:
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{
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SIM_DESC sd;
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sd = CPU_STATE (cpu);
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/* Breakpoint instruction if we are under gdb. */
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if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG)
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{
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cpu->cpu_regs.pc --;
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sim_engine_halt (CPU_STATE (cpu), cpu,
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0, cpu_get_pc (cpu), sim_stopped,
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SIM_SIGTRAP);
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}
|
|
/* else this is a nop but not in test factory mode. */
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
cpu_single_step (sim_cpu *cpu)
|
|
{
|
|
cpu->cpu_current_cycle = 0;
|
|
cpu->cpu_insn_pc = cpu_get_pc (cpu);
|
|
|
|
/* Handle the pending interrupts. If an interrupt is handled,
|
|
treat this as an single step. */
|
|
if (interrupts_process (&cpu->cpu_interrupts))
|
|
{
|
|
cpu->cpu_absolute_cycle += cpu->cpu_current_cycle;
|
|
return;
|
|
}
|
|
|
|
/* printf("PC = 0x%04x\n", cpu_get_pc (cpu));*/
|
|
cpu_interp (cpu);
|
|
cpu->cpu_absolute_cycle += cpu->cpu_current_cycle;
|
|
}
|
|
|
|
/* VARARGS */
|
|
void
|
|
sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
|
|
uint16 addr, const char *message, ...)
|
|
{
|
|
char buf[1024];
|
|
va_list args;
|
|
|
|
va_start (args, message);
|
|
vsprintf (buf, message, args);
|
|
va_end (args);
|
|
|
|
printf("%s\n", buf);
|
|
cpu_memory_exception (cpu, excep, addr, buf);
|
|
}
|
|
|
|
|
|
void
|
|
cpu_memory_exception (sim_cpu *cpu, SIM_SIGNAL excep,
|
|
uint16 addr, const char *message)
|
|
{
|
|
if (cpu->cpu_running == 0)
|
|
return;
|
|
|
|
cpu_set_pc (cpu, cpu->cpu_insn_pc);
|
|
sim_engine_halt (CPU_STATE (cpu), cpu, NULL,
|
|
cpu_get_pc (cpu), sim_stopped, excep);
|
|
|
|
#if 0
|
|
cpu->mem_exception = excep;
|
|
cpu->fault_addr = addr;
|
|
cpu->fault_msg = strdup (message);
|
|
|
|
if (cpu->cpu_use_handler)
|
|
{
|
|
longjmp (&cpu->cpu_exception_handler, 1);
|
|
}
|
|
(* cpu->callback->printf_filtered)
|
|
(cpu->callback, "Fault at 0x%04x: %s\n", addr, message);
|
|
#endif
|
|
}
|
|
|
|
void
|
|
cpu_info (SIM_DESC sd, sim_cpu *cpu)
|
|
{
|
|
sim_io_printf (sd, "CPU info:\n");
|
|
sim_io_printf (sd, " Absolute cycle: %s\n",
|
|
cycle_to_string (cpu, cpu->cpu_absolute_cycle));
|
|
|
|
sim_io_printf (sd, " Syscall emulation: %s\n",
|
|
cpu->cpu_emul_syscall ? "yes, via 0xcd <n>" : "no");
|
|
sim_io_printf (sd, " Memory errors detection: %s\n",
|
|
cpu->cpu_check_memory ? "yes" : "no");
|
|
sim_io_printf (sd, " Stop on interrupt: %s\n",
|
|
cpu->cpu_stop_on_interrupt ? "yes" : "no");
|
|
}
|
|
|