99 lines
2.4 KiB
C
99 lines
2.4 KiB
C
/* H8/300 simulator
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Copyright 1993 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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Written by Steve Chamberlain (sac@cygnus.com).
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Fake peripherals for the H8/330 */
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#include "state.h"
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perifs( )
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/* This routine is called every few instructions to see if some sort
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of hardware event is needed */
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{
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int interrupt = 0;
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int lval;
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int tmp;
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/* What to do about the 16 bit timer */
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/* Free running counter same as reg a */
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if (saved_state.reg[OCRA] == saved_state.reg[FRC])
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{
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/* Set the counter A overflow bit */
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saved_state.reg[TCSR] |= OCFA;
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if (saved_state.reg[TCSR] & CCLRA)
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{
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saved_state.reg[FRC] = 0;
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}
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if (saved_state.reg[TIER] & OCIEA)
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{
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interrupt = 16;
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}
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}
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/* Free running counter same as reg b */
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if (saved_state.reg[OCRB] == saved_state.reg[FRC])
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{
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saved_state.reg[TCSR] |= OCFB;
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if (saved_state.reg[TIER] & OCIEB)
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{
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interrupt = 17;
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}
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}
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/* inc free runnning counter */
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saved_state.reg[FRC]++;
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if (saved_state.reg[FRC] == 0)
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{
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/* Must have overflowed */
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saved_state.reg[TCSR] |= OVF;
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if (BYTE_MEM(TIER) & OVIE)
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interrupt = 18;
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}
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/* If we've had an interrupt and the bit is on */
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if (interrupt && saved_state.ienable)
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{
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int ccr;
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saved_state.ienable = 0;
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ccr = saved_state.reg[CCR];
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lval = WORD_MEM((interrupt)<<1);
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lval = WORD_MEM(lval);
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{
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/* Push PC */
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saved_state.reg[7] -= 2;
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tmp = saved_state.reg[7];
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SET_WORD_MEM (tmp, saved_state.reg[PC]);
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/* Push CCR twice */
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saved_state.reg[7] -=2 ;
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tmp = saved_state.reg[7];
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SET_BYTE_MEM(tmp,ccr);
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SET_BYTE_MEM(tmp+1,ccr);
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/* Set pc to point to first instruction of i vector */
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saved_state.reg[PC] = lval;
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}
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}
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}
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