cpuid: hardcode cores num for <v6 processors
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@ -14,7 +14,7 @@ as published by Sam Hocevar. See http://www.wtfpl.net/ for more details.
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/**
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* e2k cpuid single-header library, v1
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*
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*
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* Changes from v0:
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* - initial release
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*
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@ -37,6 +37,7 @@ typedef enum e2k_cpuid_mdl_e
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{
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MDL_E2S = 0x03, /* Elbrus-4C */
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MDL_ES2 = 0x04, /* Elbrus-2C+ */
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MDL_RESERVED = 0x05, /* unknown "reserved" processor */
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MDL_ES2_NO_DSP = 0x06, /* Elbrus-2CM */
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MDL_E8C = 0x07, /* Elbrus-8C */
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MDL_E1CP = 0x08, /* Elbrus-1C+ */
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@ -48,7 +49,7 @@ typedef enum e2k_cpuid_mdl_e
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int e2k_cpuid( e2k_cpuid_t *cpuid );
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int e2k_cpuid_from_regs( e2k_cpuid_t *cpuid, uint64_t idr, uint32_t core_mode /* only v6 */ );
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int e2k_cpuid_model_from_mdl( char *out, size_t len, uint32_t mdl );
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int e2k_cpuid_model_from_mdl( char *modelname, size_t len, uint32_t mdl );
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#ifdef E2K_CPUID_IMPLEMENTATION
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@ -86,6 +87,7 @@ int e2k_cpuid_model_from_mdl( char *out, size_t len, uint32_t mdl )
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{
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case MDL_E2S: str = "Elbrus-4C"; break;
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case MDL_ES2: str = "Elbrus-2C+"; break;
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case MDL_RESERVED: str = "Elbrus-Reserved"; break;
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case MDL_ES2_NO_DSP: str = "Elbrus-2CM"; break;
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case MDL_E8C: str = "Elbrus-8C"; break;
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case MDL_E1CP: str = "Elbrus-1C+"; break;
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@ -109,6 +111,21 @@ int e2k_cpuid_model_from_mdl( char *out, size_t len, uint32_t mdl )
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return retval;
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}
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static int e2k_cpuid_cores_from_mdl( uint32_t mdl )
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{
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/* only for processors that doesn't report cores num through IDR */
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switch( mdl )
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{
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case MDL_E1CP: return 1;
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case MDL_ES2:
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case MDL_ES2_NO_DSP: return 2;
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case MDL_E2S: return 4;
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case MDL_E8C2:
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case MDL_E8C: return 8;
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default: return 1;
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}
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}
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int e2k_cpuid_from_regs( e2k_cpuid_t *cpuid, uint64_t idr, uint32_t core_mode )
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{
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int retval = 0;
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@ -129,6 +146,10 @@ int e2k_cpuid_from_regs( e2k_cpuid_t *cpuid, uint64_t idr, uint32_t core_mode )
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cpuid->is_guest = extract32( core_mode, CORE_MODE_GUEST_START, CORE_MODE_GUEST_BITS );
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}
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else
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{
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cpuid->cores = e2k_cpuid_cores_from_mdl( cpuid->mdl );
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}
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// finalize data
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cpuid->l2_wb_len = IDR_WBL_TO_BYTES( cpuid->l2_wb_len );
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