2002-01-23 22:03:53 +01:00
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/* Xtensa configuration settings.
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2004-10-08 02:28:50 +02:00
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Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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2002-01-23 22:03:53 +01:00
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Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
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lib1funcs.asm: Avoid use of .Lfe* in .size directives.
* config/xtensa/lib1funcs.asm: Avoid use of .Lfe* in .size directives.
(do_abs, do_addx2, do_addx4, do_addx8): New assembler macros.
(__mulsi3): Use do_addx* instead of ADDX* instructions. Formatting.
(nsau): Rename to do_nsau. Provide alternate version for use when
the NSAU instruction is available.
(__udivsi3, __divsi3, __umodsi3, __modsi3): Use do_nsau macro.
(__divsi3, __modsi3): Use do_abs macro instead of ABS instruction.
* config/xtensa/xtensa-config.h: Update comments to match binutils.
(XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX): Define.
* config/xtensa/xtensa.h (MASK_ABS, MASK_ADDX): Define.
(TARGET_ABS, TARGET_ADDX): Define.
(TARGET_DEFAULT): Conditionally add MASK_ABS and MASK_ADDX.
(TARGET_SWITCHES): Add "abs", "no-abs", "addx", and "no-addx".
* config/xtensa/xtensa.md (*addx2, *addx4, *addx8, *subx2, *subx4,
*subx8): Set predicate condition to TARGET_ADDX.
(abssi2): Set predicate condition to TARGET_ABS.
* doc/invoke.texi (Option Summary): Document new "-mabs", "-mno-abs",
"-maddx", and "-mno-addx" options.
(Xtensa Options): Likewise. Also tag some opcode names with @code.
From-SVN: r67044
2003-05-21 01:39:09 +02:00
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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2005-05-10 17:22:21 +02:00
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Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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2002-01-23 22:03:53 +01:00
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#ifndef XTENSA_CONFIG_H
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#define XTENSA_CONFIG_H
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lib1funcs.asm: Avoid use of .Lfe* in .size directives.
* config/xtensa/lib1funcs.asm: Avoid use of .Lfe* in .size directives.
(do_abs, do_addx2, do_addx4, do_addx8): New assembler macros.
(__mulsi3): Use do_addx* instead of ADDX* instructions. Formatting.
(nsau): Rename to do_nsau. Provide alternate version for use when
the NSAU instruction is available.
(__udivsi3, __divsi3, __umodsi3, __modsi3): Use do_nsau macro.
(__divsi3, __modsi3): Use do_abs macro instead of ABS instruction.
* config/xtensa/xtensa-config.h: Update comments to match binutils.
(XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX): Define.
* config/xtensa/xtensa.h (MASK_ABS, MASK_ADDX): Define.
(TARGET_ABS, TARGET_ADDX): Define.
(TARGET_DEFAULT): Conditionally add MASK_ABS and MASK_ADDX.
(TARGET_SWITCHES): Add "abs", "no-abs", "addx", and "no-addx".
* config/xtensa/xtensa.md (*addx2, *addx4, *addx8, *subx2, *subx4,
*subx8): Set predicate condition to TARGET_ADDX.
(abssi2): Set predicate condition to TARGET_ABS.
* doc/invoke.texi (Option Summary): Document new "-mabs", "-mno-abs",
"-maddx", and "-mno-addx" options.
(Xtensa Options): Likewise. Also tag some opcode names with @code.
From-SVN: r67044
2003-05-21 01:39:09 +02:00
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/* The macros defined here match those with the same names in the Xtensa
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compile-time HAL (Hardware Abstraction Layer). Please refer to the
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Xtensa System Software Reference Manual for documentation of these
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macros. */
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_BE
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_BE 1
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_DENSITY
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_DENSITY 1
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_CONST16
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lib2funcs.S (TRAMPOLINE_SIZE): Change from 49 to 59.
* config/xtensa/lib2funcs.S (TRAMPOLINE_SIZE): Change from 49 to 59.
* config/xtensa/xtensa-config.h (XCHAL_HAVE_CONST16,
XCHAL_HAVE_L32R): New.
* config/xtensa/xtensa-protos.h (non_const_move_operand,
xtensa_load_constant, xtensa_function_prologue,
xtensa_function_epilogue): Delete prototypes.
(xtensa_expand_prologue): New.
* config/xtensa/xtensa.c (frame_size_const,
TARGET_ASM_FUNCTION_PROLOGUE, TARGET_MACHINE_DEPENDENT_REORG,
non_const_move_operand, xtensa_load_constant, xtensa_reorg,
xtensa_function_prologue): Delete.
(add_operand, xtensa_mem_offset): Formatting.
(move_operand): If the const16 option is available, allow any SFmode
and SImode constants.
(xtensa_emit_move_sequence): Inline the former contents of
xtensa_load_constant with modifications to handle the const16 option.
(override_options): Add xtensa_char_to_class['W'] and set it to
the general register class only if the const16 option is enabled.
Fix formatting. Disallow PIC when using the const16 option.
(print_operand): Reorganize to switch on "letter" instead of the
RTL code. Add output_operand_lossage calls for invalid cases.
Add support for 't' and 'b' letters.
(xtensa_expand_prologue): New function to replace
xtensa_function_prologue and xtensa_reorg.
(xtensa_function_epilogue): Declare this as static. Delete code
to print the retw.n or retw instruction.
(xtensa_return_addr): Use A0_REG instead of 0.
(xtensa_rtx_costs): Add costs for using the const16 option.
* config/xtensa/xtensa.h (MASK_CONST16, TARGET_CONST16): New.
(TARGET_DEFAULT): Add CONST16 if L32R instructions not available.
(TARGET_SWITCHES): Add "const16" and "no-const16".
(REG_CLASS_FROM_LETTER): Add comment about new 'W' letter.
(EXTRA_CONSTRAINT): Change 'T' constraint to only apply when not
using the const16 option.
(TRAMPOLINE_TEMPLATE): Rewrite to avoid hardwired use of l32r insn.
(TRAMPOLINE_SIZE): Change from 49 to 59.
(INITIALIZE_TRAMPOLINE): Adjust offsets to match new trampoline.
(GO_IF_LEGITIMATE_ADDRESS): Do not allow constant pool addresses
when using the const16 option.
(PREDICATE_CODES): Delete non_const_move_operand.
* config/xtensa/xtensa.md (define_constants): Add A1_REG, A8_REG, and
UNSPECV_ENTRY.
(movdi, movdf): If the source is a constant, always expand to a
sequence of movsi insns.
(movdi_internal, movdf_internal): Remove alternative using l32r insns.
(movsi_internal, movsf_internal): Add alternative using const16 insns.
(movsf): Add const16 support.
(entry, prologue, epilogue): New.
(set_frame_ptr): Add missing mode for unspec_volatile operation.
Likewise for subsequent split pattern.
* doc/invoke.texi (Option Summary, Xtensa Options): Document new
"-mconst16" and "-mno-const16" options.
From-SVN: r66809
2003-05-14 20:37:26 +02:00
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#define XCHAL_HAVE_CONST16 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_ABS
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lib1funcs.asm: Avoid use of .Lfe* in .size directives.
* config/xtensa/lib1funcs.asm: Avoid use of .Lfe* in .size directives.
(do_abs, do_addx2, do_addx4, do_addx8): New assembler macros.
(__mulsi3): Use do_addx* instead of ADDX* instructions. Formatting.
(nsau): Rename to do_nsau. Provide alternate version for use when
the NSAU instruction is available.
(__udivsi3, __divsi3, __umodsi3, __modsi3): Use do_nsau macro.
(__divsi3, __modsi3): Use do_abs macro instead of ABS instruction.
* config/xtensa/xtensa-config.h: Update comments to match binutils.
(XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX): Define.
* config/xtensa/xtensa.h (MASK_ABS, MASK_ADDX): Define.
(TARGET_ABS, TARGET_ADDX): Define.
(TARGET_DEFAULT): Conditionally add MASK_ABS and MASK_ADDX.
(TARGET_SWITCHES): Add "abs", "no-abs", "addx", and "no-addx".
* config/xtensa/xtensa.md (*addx2, *addx4, *addx8, *subx2, *subx4,
*subx8): Set predicate condition to TARGET_ADDX.
(abssi2): Set predicate condition to TARGET_ABS.
* doc/invoke.texi (Option Summary): Document new "-mabs", "-mno-abs",
"-maddx", and "-mno-addx" options.
(Xtensa Options): Likewise. Also tag some opcode names with @code.
From-SVN: r67044
2003-05-21 01:39:09 +02:00
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#define XCHAL_HAVE_ABS 1
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_ADDX
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lib1funcs.asm: Avoid use of .Lfe* in .size directives.
* config/xtensa/lib1funcs.asm: Avoid use of .Lfe* in .size directives.
(do_abs, do_addx2, do_addx4, do_addx8): New assembler macros.
(__mulsi3): Use do_addx* instead of ADDX* instructions. Formatting.
(nsau): Rename to do_nsau. Provide alternate version for use when
the NSAU instruction is available.
(__udivsi3, __divsi3, __umodsi3, __modsi3): Use do_nsau macro.
(__divsi3, __modsi3): Use do_abs macro instead of ABS instruction.
* config/xtensa/xtensa-config.h: Update comments to match binutils.
(XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX): Define.
* config/xtensa/xtensa.h (MASK_ABS, MASK_ADDX): Define.
(TARGET_ABS, TARGET_ADDX): Define.
(TARGET_DEFAULT): Conditionally add MASK_ABS and MASK_ADDX.
(TARGET_SWITCHES): Add "abs", "no-abs", "addx", and "no-addx".
* config/xtensa/xtensa.md (*addx2, *addx4, *addx8, *subx2, *subx4,
*subx8): Set predicate condition to TARGET_ADDX.
(abssi2): Set predicate condition to TARGET_ABS.
* doc/invoke.texi (Option Summary): Document new "-mabs", "-mno-abs",
"-maddx", and "-mno-addx" options.
(Xtensa Options): Likewise. Also tag some opcode names with @code.
From-SVN: r67044
2003-05-21 01:39:09 +02:00
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#define XCHAL_HAVE_ADDX 1
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_L32R
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lib2funcs.S (TRAMPOLINE_SIZE): Change from 49 to 59.
* config/xtensa/lib2funcs.S (TRAMPOLINE_SIZE): Change from 49 to 59.
* config/xtensa/xtensa-config.h (XCHAL_HAVE_CONST16,
XCHAL_HAVE_L32R): New.
* config/xtensa/xtensa-protos.h (non_const_move_operand,
xtensa_load_constant, xtensa_function_prologue,
xtensa_function_epilogue): Delete prototypes.
(xtensa_expand_prologue): New.
* config/xtensa/xtensa.c (frame_size_const,
TARGET_ASM_FUNCTION_PROLOGUE, TARGET_MACHINE_DEPENDENT_REORG,
non_const_move_operand, xtensa_load_constant, xtensa_reorg,
xtensa_function_prologue): Delete.
(add_operand, xtensa_mem_offset): Formatting.
(move_operand): If the const16 option is available, allow any SFmode
and SImode constants.
(xtensa_emit_move_sequence): Inline the former contents of
xtensa_load_constant with modifications to handle the const16 option.
(override_options): Add xtensa_char_to_class['W'] and set it to
the general register class only if the const16 option is enabled.
Fix formatting. Disallow PIC when using the const16 option.
(print_operand): Reorganize to switch on "letter" instead of the
RTL code. Add output_operand_lossage calls for invalid cases.
Add support for 't' and 'b' letters.
(xtensa_expand_prologue): New function to replace
xtensa_function_prologue and xtensa_reorg.
(xtensa_function_epilogue): Declare this as static. Delete code
to print the retw.n or retw instruction.
(xtensa_return_addr): Use A0_REG instead of 0.
(xtensa_rtx_costs): Add costs for using the const16 option.
* config/xtensa/xtensa.h (MASK_CONST16, TARGET_CONST16): New.
(TARGET_DEFAULT): Add CONST16 if L32R instructions not available.
(TARGET_SWITCHES): Add "const16" and "no-const16".
(REG_CLASS_FROM_LETTER): Add comment about new 'W' letter.
(EXTRA_CONSTRAINT): Change 'T' constraint to only apply when not
using the const16 option.
(TRAMPOLINE_TEMPLATE): Rewrite to avoid hardwired use of l32r insn.
(TRAMPOLINE_SIZE): Change from 49 to 59.
(INITIALIZE_TRAMPOLINE): Adjust offsets to match new trampoline.
(GO_IF_LEGITIMATE_ADDRESS): Do not allow constant pool addresses
when using the const16 option.
(PREDICATE_CODES): Delete non_const_move_operand.
* config/xtensa/xtensa.md (define_constants): Add A1_REG, A8_REG, and
UNSPECV_ENTRY.
(movdi, movdf): If the source is a constant, always expand to a
sequence of movsi insns.
(movdi_internal, movdf_internal): Remove alternative using l32r insns.
(movsi_internal, movsf_internal): Add alternative using const16 insns.
(movsf): Add const16 support.
(entry, prologue, epilogue): New.
(set_frame_ptr): Add missing mode for unspec_volatile operation.
Likewise for subsequent split pattern.
* doc/invoke.texi (Option Summary, Xtensa Options): Document new
"-mconst16" and "-mno-const16" options.
From-SVN: r66809
2003-05-14 20:37:26 +02:00
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#define XCHAL_HAVE_L32R 1
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2003-07-10 07:08:27 +02:00
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2004-10-08 02:28:50 +02:00
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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#define XSHAL_USE_ABSOLUTE_LITERALS 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_MAC16
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_MAC16 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_MUL16
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_MUL16 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_MUL32
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_MUL32 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_DIV32
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_DIV32 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_NSA
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_NSA 1
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_MINMAX
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_MINMAX 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_SEXT
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_SEXT 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_LOOPS
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2002-03-12 21:02:36 +01:00
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#define XCHAL_HAVE_LOOPS 1
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_BOOLEANS
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_BOOLEANS 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_FP
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_FP 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_FP_DIV
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_FP_DIV 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_FP_RECIP
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_FP_RECIP 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_FP_SQRT
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_FP_SQRT 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_FP_RSQRT
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_FP_RSQRT 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_WINDOWED
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2003-07-01 02:14:33 +02:00
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#define XCHAL_HAVE_WINDOWED 1
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2002-01-23 22:03:53 +01:00
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2004-10-08 02:28:50 +02:00
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#undef XCHAL_HAVE_PREDICTED_BRANCHES
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_ICACHE_SIZE
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2002-01-23 22:03:53 +01:00
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#define XCHAL_ICACHE_SIZE 8192
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_DCACHE_SIZE
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2002-01-23 22:03:53 +01:00
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#define XCHAL_DCACHE_SIZE 8192
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_ICACHE_LINESIZE
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2002-01-23 22:03:53 +01:00
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#define XCHAL_ICACHE_LINESIZE 16
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_DCACHE_LINESIZE
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2002-01-23 22:03:53 +01:00
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#define XCHAL_DCACHE_LINESIZE 16
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_ICACHE_LINEWIDTH
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2002-01-23 22:03:53 +01:00
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#define XCHAL_ICACHE_LINEWIDTH 4
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_DCACHE_LINEWIDTH
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2002-01-23 22:03:53 +01:00
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#define XCHAL_DCACHE_LINEWIDTH 4
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_DCACHE_IS_WRITEBACK
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2002-01-23 22:03:53 +01:00
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#define XCHAL_DCACHE_IS_WRITEBACK 0
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_MMU
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2002-01-23 22:03:53 +01:00
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#define XCHAL_HAVE_MMU 1
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
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2002-01-23 22:03:53 +01:00
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#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_HAVE_DEBUG
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2003-07-01 02:14:33 +02:00
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#define XCHAL_HAVE_DEBUG 1
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_NUM_IBREAK
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2003-07-01 02:14:33 +02:00
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#define XCHAL_NUM_IBREAK 2
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_NUM_DBREAK
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2003-07-01 02:14:33 +02:00
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#define XCHAL_NUM_DBREAK 2
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2003-07-10 07:08:27 +02:00
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#undef XCHAL_DEBUGLEVEL
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2003-07-01 02:14:33 +02:00
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#define XCHAL_DEBUGLEVEL 4
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2003-07-10 07:08:27 +02:00
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2004-10-08 02:28:50 +02:00
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#undef XCHAL_INST_FETCH_WIDTH
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#define XCHAL_INST_FETCH_WIDTH 4
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2003-07-01 02:14:33 +02:00
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2002-01-23 22:03:53 +01:00
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#endif /* !XTENSA_CONFIG_H */
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