2012-04-25 02:08:37 +02:00
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/* Get CPU type and Features for x86 processors.
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2017-01-01 13:07:43 +01:00
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Copyright (C) 2012-2017 Free Software Foundation, Inc.
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2012-04-25 02:08:37 +02:00
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Contributed by Sriraman Tallam (tmsriram@google.com)
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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2013-08-01 23:09:10 +02:00
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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2012-04-25 02:08:37 +02:00
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#include "cpuid.h"
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#include "tsystem.h"
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2012-05-10 10:51:39 +02:00
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#include "auto-target.h"
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2016-12-03 10:44:35 +01:00
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#include "cpuinfo.h"
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2012-04-25 02:08:37 +02:00
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2012-05-10 10:51:39 +02:00
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#ifdef HAVE_INIT_PRIORITY
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#define CONSTRUCTOR_PRIORITY (101)
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#else
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#define CONSTRUCTOR_PRIORITY
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#endif
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int __cpu_indicator_init (void)
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__attribute__ ((constructor CONSTRUCTOR_PRIORITY));
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2012-04-25 02:08:37 +02:00
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2016-12-03 10:44:35 +01:00
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struct __processor_model __cpu_model = { };
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2012-04-25 02:08:37 +02:00
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/* Get the specific type of AMD CPU. */
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static void
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get_amd_cpu (unsigned int family, unsigned int model)
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{
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switch (family)
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{
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/* AMD Family 10h. */
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case 0x10:
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re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
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__cpu_model.__cpu_type = AMDFAM10H;
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2012-04-25 02:08:37 +02:00
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switch (model)
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{
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case 0x2:
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/* Barcelona. */
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__cpu_model.__cpu_subtype = AMDFAM10H_BARCELONA;
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break;
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case 0x4:
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/* Shanghai. */
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__cpu_model.__cpu_subtype = AMDFAM10H_SHANGHAI;
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break;
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case 0x8:
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/* Istanbul. */
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__cpu_model.__cpu_subtype = AMDFAM10H_ISTANBUL;
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break;
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default:
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break;
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}
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break;
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2013-12-26 09:54:49 +01:00
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/* AMD Family 14h "btver1". */
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re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
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case 0x14:
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2013-12-26 09:54:49 +01:00
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__cpu_model.__cpu_type = AMD_BTVER1;
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re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
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break;
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/* AMD Family 15h "Bulldozer". */
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2012-04-25 02:08:37 +02:00
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case 0x15:
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__cpu_model.__cpu_type = AMDFAM15H;
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/* Bulldozer version 1. */
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if ( model <= 0xf)
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__cpu_model.__cpu_subtype = AMDFAM15H_BDVER1;
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re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
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/* Bulldozer version 2 "Piledriver" */
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if (model >= 0x10 && model <= 0x2f)
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__cpu_model.__cpu_subtype = AMDFAM15H_BDVER2;
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/* Bulldozer version 3 "Steamroller" */
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if (model >= 0x30 && model <= 0x4f)
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__cpu_model.__cpu_subtype = AMDFAM15H_BDVER3;
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2015-10-11 10:06:14 +02:00
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/* Bulldozer version 4 "Excavator" */
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if (model >= 0x60 && model <= 0x7f)
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__cpu_model.__cpu_subtype = AMDFAM15H_BDVER4;
|
re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
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break;
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2013-12-26 09:54:49 +01:00
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/* AMD Family 16h "btver2" */
|
re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
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case 0x16:
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2013-12-26 09:54:49 +01:00
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__cpu_model.__cpu_type = AMD_BTVER2;
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2012-04-25 02:08:37 +02:00
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break;
|
2015-10-30 14:20:42 +01:00
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case 0x17:
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__cpu_model.__cpu_type = AMDFAM17H;
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/* AMD family 17h version 1. */
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if (model <= 0x1f)
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__cpu_model.__cpu_subtype = AMDFAM17H_ZNVER1;
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break;
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2012-04-25 02:08:37 +02:00
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default:
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break;
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}
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}
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/* Get the specific type of Intel CPU. */
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static void
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get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
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{
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/* Parse family and model only if brand ID is 0. */
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if (brand_id == 0)
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{
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switch (family)
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{
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case 0x5:
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/* Pentium. */
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break;
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case 0x6:
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switch (model)
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{
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case 0x1c:
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case 0x26:
|
Use proper Intel processor names for -march=/-mtune=
gcc/
* config/i386/core2.md: Replace corei7 with nehalem.
* config/i386/driver-i386.c (host_detect_local_cpu): Use nehalem,
westmere, sandybridge, ivybridge, haswell, bonnell, silvermont
for cpu names.
* config/i386/i386-c.c (ix86_target_macros_internal): Replace
PROCESSOR_COREI7, PROCESSOR_COREI7_AVX, PROCESSOR_ATOM,
PROCESSOR_SLM with PROCESSOR_NEHALEM, PROCESSOR_SANDYBRIDGE,
PROCESSOR_BONNELL, PROCESSOR_SILVERMONT. Define
__nehalem/__nehalem__, __sandybridge/__sandybridge__,
__haswell/__haswell__, __tune_nehalem__, __tune_sandybridge__,
__tune_haswell__, __bonnell/__bonnell__,
__silvermont/__silvermont__, __tune_bonnell__,
__tune_silvermont__.
* config/i386/i386.c (m_COREI7): Renamed to ...
(m_NEHALEM): This.
(m_COREI7_AVX): Renamed to ...
(m_SANDYBRIDGE): This.
(m_ATOM): Renamed to ...
(m_BONNELL): This.
(m_SLM): Renamed to ...
(m_SILVERMONT): This.
(m_CORE_ALL): Updated.
(cpu_names): Add "nehalem", "westmere", "sandybridge",
"ivybridge", "haswell", "broadwell", "bonnell", "silvermont".
(PTA_CORE2): New.
(PTA_NEHALEM): Likewise.
(PTA_WESTMERE): Likewise.
(PTA_SANDYBRIDGE): Likewise.
(PTA_IVYBRIDGE): Likewise.
(PTA_HASWELL): Likewise.
(PTA_BROADWELL): Likewise.
(PTA_BONNELL): Likewise.
(PTA_SILVERMONT): Likewise.
(ix86_option_override_internal): Use new PTA_XXX. Add nehalem,
westmere, sandybridge, ivybridge, haswell, bonnell, silvermont.
(ix86_lea_outperforms): Updated.
(ix86_issue_rate): Likewise.
(ix86_adjust_cost): Likewise.
(ia32_multipass_dfa_lookahead): Likewise.
(do_reorder_for_imul): Likewise.
(swap_top_of_ready_list): Likewise.
(ix86_sched_reorder): Likewise.
(ix86_sched_init_global): Likewise.
(get_builtin_code_for_version): Likewise.
(processor_model): Replace M_INTEL_ATOM, M_INTEL_SLM with
M_INTEL_BONNELL, M_INTEL_SILVERMONT.
(arch_names_table): Updated.
* config/i386/i386.h (TARGET_COREI7): Removed.
(TARGET_COREI7_AVX): Likewise.
(TARGET_ATOM): Likewise.
(TARGET_SLM): Likewise.
(TARGET_NEHALEM): New.
(TARGET_SANDYBRIDGE): Likewise.
(TARGET_BONNELL): Likewise.
(TARGET_SILVERMONT): Likewise.
(target_cpu_default): Add TARGET_CPU_DEFAULT_core_avx2,
TARGET_CPU_DEFAULT_nehalem, TARGET_CPU_DEFAULT_westmere,
TARGET_CPU_DEFAULT_sandybridge, TARGET_CPU_DEFAULT_ivybridge,
TARGET_CPU_DEFAULT_broadwell, TARGET_CPU_DEFAULT_bonnell,
TARGET_CPU_DEFAULT_silvermont. Move TARGET_CPU_DEFAULT_haswell
before TARGET_CPU_DEFAULT_broadwell.
(processor_type): Replace PROCESSOR_COREI7, PROCESSOR_COREI7_AVX,
PROCESSOR_ATOM, PROCESSOR_SLM with PROCESSOR_NEHALEM,
PROCESSOR_SANDYBRIDGE, PROCESSOR_BONNELL, PROCESSOR_SILVERMONT.
* config/i386/i386.md (cpu): Replace corei7 with nehalem.
* config/i386/x86-tune.def: Updated.
* doc/invoke.texi: Replace corei7, corei7-avx, core-avx-i,
core-avx2, atom, slm with nehalem, sandybridge, ivybridge,
haswell, bonnel, silvermont. Add westmere.
libgcc/
* config/i386/cpuinfo.c (processor_subtypes): Replace INTEL_ATOM,
INTEL_SLM with INTEL_BONNELL, INTEL_SILVERMONT.
(get_intel_cpu): Updated.
Co-Authored-By: Tocar Ilya <ilya.tocar@intel.com>
From-SVN: r206178
2013-12-23 14:05:09 +01:00
|
|
|
/* Bonnell. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_BONNELL;
|
2012-04-25 02:08:37 +02:00
|
|
|
break;
|
2013-11-22 17:33:40 +01:00
|
|
|
case 0x37:
|
2015-01-25 05:42:50 +01:00
|
|
|
case 0x4a:
|
2013-11-22 17:33:40 +01:00
|
|
|
case 0x4d:
|
2015-01-25 05:42:50 +01:00
|
|
|
case 0x5a:
|
|
|
|
case 0x5d:
|
2013-11-22 17:33:40 +01:00
|
|
|
/* Silvermont. */
|
Use proper Intel processor names for -march=/-mtune=
gcc/
* config/i386/core2.md: Replace corei7 with nehalem.
* config/i386/driver-i386.c (host_detect_local_cpu): Use nehalem,
westmere, sandybridge, ivybridge, haswell, bonnell, silvermont
for cpu names.
* config/i386/i386-c.c (ix86_target_macros_internal): Replace
PROCESSOR_COREI7, PROCESSOR_COREI7_AVX, PROCESSOR_ATOM,
PROCESSOR_SLM with PROCESSOR_NEHALEM, PROCESSOR_SANDYBRIDGE,
PROCESSOR_BONNELL, PROCESSOR_SILVERMONT. Define
__nehalem/__nehalem__, __sandybridge/__sandybridge__,
__haswell/__haswell__, __tune_nehalem__, __tune_sandybridge__,
__tune_haswell__, __bonnell/__bonnell__,
__silvermont/__silvermont__, __tune_bonnell__,
__tune_silvermont__.
* config/i386/i386.c (m_COREI7): Renamed to ...
(m_NEHALEM): This.
(m_COREI7_AVX): Renamed to ...
(m_SANDYBRIDGE): This.
(m_ATOM): Renamed to ...
(m_BONNELL): This.
(m_SLM): Renamed to ...
(m_SILVERMONT): This.
(m_CORE_ALL): Updated.
(cpu_names): Add "nehalem", "westmere", "sandybridge",
"ivybridge", "haswell", "broadwell", "bonnell", "silvermont".
(PTA_CORE2): New.
(PTA_NEHALEM): Likewise.
(PTA_WESTMERE): Likewise.
(PTA_SANDYBRIDGE): Likewise.
(PTA_IVYBRIDGE): Likewise.
(PTA_HASWELL): Likewise.
(PTA_BROADWELL): Likewise.
(PTA_BONNELL): Likewise.
(PTA_SILVERMONT): Likewise.
(ix86_option_override_internal): Use new PTA_XXX. Add nehalem,
westmere, sandybridge, ivybridge, haswell, bonnell, silvermont.
(ix86_lea_outperforms): Updated.
(ix86_issue_rate): Likewise.
(ix86_adjust_cost): Likewise.
(ia32_multipass_dfa_lookahead): Likewise.
(do_reorder_for_imul): Likewise.
(swap_top_of_ready_list): Likewise.
(ix86_sched_reorder): Likewise.
(ix86_sched_init_global): Likewise.
(get_builtin_code_for_version): Likewise.
(processor_model): Replace M_INTEL_ATOM, M_INTEL_SLM with
M_INTEL_BONNELL, M_INTEL_SILVERMONT.
(arch_names_table): Updated.
* config/i386/i386.h (TARGET_COREI7): Removed.
(TARGET_COREI7_AVX): Likewise.
(TARGET_ATOM): Likewise.
(TARGET_SLM): Likewise.
(TARGET_NEHALEM): New.
(TARGET_SANDYBRIDGE): Likewise.
(TARGET_BONNELL): Likewise.
(TARGET_SILVERMONT): Likewise.
(target_cpu_default): Add TARGET_CPU_DEFAULT_core_avx2,
TARGET_CPU_DEFAULT_nehalem, TARGET_CPU_DEFAULT_westmere,
TARGET_CPU_DEFAULT_sandybridge, TARGET_CPU_DEFAULT_ivybridge,
TARGET_CPU_DEFAULT_broadwell, TARGET_CPU_DEFAULT_bonnell,
TARGET_CPU_DEFAULT_silvermont. Move TARGET_CPU_DEFAULT_haswell
before TARGET_CPU_DEFAULT_broadwell.
(processor_type): Replace PROCESSOR_COREI7, PROCESSOR_COREI7_AVX,
PROCESSOR_ATOM, PROCESSOR_SLM with PROCESSOR_NEHALEM,
PROCESSOR_SANDYBRIDGE, PROCESSOR_BONNELL, PROCESSOR_SILVERMONT.
* config/i386/i386.md (cpu): Replace corei7 with nehalem.
* config/i386/x86-tune.def: Updated.
* doc/invoke.texi: Replace corei7, corei7-avx, core-avx-i,
core-avx2, atom, slm with nehalem, sandybridge, ivybridge,
haswell, bonnel, silvermont. Add westmere.
libgcc/
* config/i386/cpuinfo.c (processor_subtypes): Replace INTEL_ATOM,
INTEL_SLM with INTEL_BONNELL, INTEL_SILVERMONT.
(get_intel_cpu): Updated.
Co-Authored-By: Tocar Ilya <ilya.tocar@intel.com>
From-SVN: r206178
2013-12-23 14:05:09 +01:00
|
|
|
__cpu_model.__cpu_type = INTEL_SILVERMONT;
|
2013-11-22 17:33:40 +01:00
|
|
|
break;
|
2015-08-12 16:52:22 +02:00
|
|
|
case 0x57:
|
|
|
|
/* Knights Landing. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_KNL;
|
|
|
|
break;
|
2012-04-25 02:08:37 +02:00
|
|
|
case 0x1a:
|
|
|
|
case 0x1e:
|
|
|
|
case 0x1f:
|
|
|
|
case 0x2e:
|
|
|
|
/* Nehalem. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_COREI7;
|
|
|
|
__cpu_model.__cpu_subtype = INTEL_COREI7_NEHALEM;
|
|
|
|
break;
|
|
|
|
case 0x25:
|
|
|
|
case 0x2c:
|
|
|
|
case 0x2f:
|
|
|
|
/* Westmere. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_COREI7;
|
|
|
|
__cpu_model.__cpu_subtype = INTEL_COREI7_WESTMERE;
|
|
|
|
break;
|
|
|
|
case 0x2a:
|
2013-03-08 02:02:29 +01:00
|
|
|
case 0x2d:
|
2012-04-25 02:08:37 +02:00
|
|
|
/* Sandy Bridge. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_COREI7;
|
|
|
|
__cpu_model.__cpu_subtype = INTEL_COREI7_SANDYBRIDGE;
|
|
|
|
break;
|
re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
|
|
|
case 0x3a:
|
|
|
|
case 0x3e:
|
|
|
|
/* Ivy Bridge. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_COREI7;
|
|
|
|
__cpu_model.__cpu_subtype = INTEL_COREI7_IVYBRIDGE;
|
|
|
|
break;
|
|
|
|
case 0x3c:
|
2015-01-25 05:42:50 +01:00
|
|
|
case 0x3f:
|
re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
|
|
|
case 0x45:
|
|
|
|
case 0x46:
|
|
|
|
/* Haswell. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_COREI7;
|
|
|
|
__cpu_model.__cpu_subtype = INTEL_COREI7_HASWELL;
|
|
|
|
break;
|
2015-01-25 05:42:50 +01:00
|
|
|
case 0x3d:
|
2015-08-10 21:19:05 +02:00
|
|
|
case 0x47:
|
2015-01-25 05:42:50 +01:00
|
|
|
case 0x4f:
|
|
|
|
case 0x56:
|
|
|
|
/* Broadwell. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_COREI7;
|
|
|
|
__cpu_model.__cpu_subtype = INTEL_COREI7_BROADWELL;
|
|
|
|
break;
|
2015-08-14 11:11:01 +02:00
|
|
|
case 0x4e:
|
|
|
|
case 0x5e:
|
|
|
|
/* Skylake. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_COREI7;
|
|
|
|
__cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE;
|
|
|
|
break;
|
2015-10-05 15:16:07 +02:00
|
|
|
case 0x55:
|
|
|
|
/* Skylake with AVX-512 support. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_COREI7;
|
|
|
|
__cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE_AVX512;
|
|
|
|
break;
|
2012-04-25 02:08:37 +02:00
|
|
|
case 0x17:
|
|
|
|
case 0x1d:
|
|
|
|
/* Penryn. */
|
|
|
|
case 0x0f:
|
|
|
|
/* Merom. */
|
|
|
|
__cpu_model.__cpu_type = INTEL_CORE2;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* We have no idea. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-04-26 02:52:09 +02:00
|
|
|
/* ECX and EDX are output of CPUID at level one. MAX_CPUID_LEVEL is
|
|
|
|
the max possible level of CPUID insn. */
|
2012-04-25 02:08:37 +02:00
|
|
|
static void
|
2012-04-26 02:52:09 +02:00
|
|
|
get_available_features (unsigned int ecx, unsigned int edx,
|
|
|
|
int max_cpuid_level)
|
2012-04-25 02:08:37 +02:00
|
|
|
{
|
2017-01-12 18:30:03 +01:00
|
|
|
unsigned int eax, ebx;
|
|
|
|
unsigned int ext_level;
|
|
|
|
|
2012-04-25 02:08:37 +02:00
|
|
|
unsigned int features = 0;
|
|
|
|
|
|
|
|
if (edx & bit_CMOV)
|
|
|
|
features |= (1 << FEATURE_CMOV);
|
|
|
|
if (edx & bit_MMX)
|
|
|
|
features |= (1 << FEATURE_MMX);
|
|
|
|
if (edx & bit_SSE)
|
|
|
|
features |= (1 << FEATURE_SSE);
|
|
|
|
if (edx & bit_SSE2)
|
|
|
|
features |= (1 << FEATURE_SSE2);
|
|
|
|
if (ecx & bit_POPCNT)
|
|
|
|
features |= (1 << FEATURE_POPCNT);
|
2015-07-22 20:01:33 +02:00
|
|
|
if (ecx & bit_AES)
|
|
|
|
features |= (1 << FEATURE_AES);
|
2015-08-11 19:53:41 +02:00
|
|
|
if (ecx & bit_PCLMUL)
|
|
|
|
features |= (1 << FEATURE_PCLMUL);
|
2012-04-25 02:08:37 +02:00
|
|
|
if (ecx & bit_SSE3)
|
|
|
|
features |= (1 << FEATURE_SSE3);
|
|
|
|
if (ecx & bit_SSSE3)
|
|
|
|
features |= (1 << FEATURE_SSSE3);
|
|
|
|
if (ecx & bit_SSE4_1)
|
|
|
|
features |= (1 << FEATURE_SSE4_1);
|
|
|
|
if (ecx & bit_SSE4_2)
|
|
|
|
features |= (1 << FEATURE_SSE4_2);
|
|
|
|
if (ecx & bit_AVX)
|
|
|
|
features |= (1 << FEATURE_AVX);
|
re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
|
|
|
if (ecx & bit_FMA)
|
|
|
|
features |= (1 << FEATURE_FMA);
|
2012-04-25 02:08:37 +02:00
|
|
|
|
2012-04-26 02:52:09 +02:00
|
|
|
/* Get Advanced Features at level 7 (eax = 7, ecx = 0). */
|
|
|
|
if (max_cpuid_level >= 7)
|
|
|
|
{
|
|
|
|
__cpuid_count (7, 0, eax, ebx, ecx, edx);
|
2015-01-25 19:17:46 +01:00
|
|
|
if (ebx & bit_BMI)
|
|
|
|
features |= (1 << FEATURE_BMI);
|
2012-04-26 02:52:09 +02:00
|
|
|
if (ebx & bit_AVX2)
|
|
|
|
features |= (1 << FEATURE_AVX2);
|
2015-01-25 19:17:46 +01:00
|
|
|
if (ebx & bit_BMI2)
|
|
|
|
features |= (1 << FEATURE_BMI2);
|
2014-11-27 14:51:10 +01:00
|
|
|
if (ebx & bit_AVX512F)
|
|
|
|
features |= (1 << FEATURE_AVX512F);
|
AVX-512. Introduce SKylake server CPU.
gcc/
* config.gcc: Support "skylake-avx512".
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
PROCESSOR_SKYLAKE_AVX512.
* config/i386/i386.c (m_SKYLAKE_AVX512): Define.
(processor_target_table): Add "skylake-avx512".
(PTA_SKYLAKE_AVX512): Define.
(ix86_option_override_internal): Add "skylake_avx512".
(fold_builtin_cpu): Handle "skylake_avx512", add F_AVX512VL
F_AVX512BW, F_AVX512DQ, F_AVX512ER, F_AVX512PF, F_AVX512CD.
* config/i386/i386.h (TARGET_SKYLAKE_AVX512): Define.
(processor_type): Add PROCESSOR_SKYLAKE_AVX512.
* doc/invoke.texi (skylake-avx512): New.
libgcc/
* libgcc/config/i386/cpuinfo.c (enum processor_features): Add
FEATURE_AVX512VL, FEATURE_AVX512BW, FEATURE_AVX512DQ,
FEATURE_AVX512CD, FEATURE_AVX512ER, FEATURE_AVX512PF.
(get_available_features): Habdle new features.
gcc/testsuite/
* gcc.target/i386/funcspec-5.c: Test avx512vl, avx512bw,
avx512dq, avx512cd, avx512er, avx512pf and skylake-avx512.
* gcc.target/i386/builtin_target.c: Test avx512vl, avx512bw,
avx512dq, avx512cd, avx512er and avx512pf.
From-SVN: r228009
2015-09-22 13:10:21 +02:00
|
|
|
if (ebx & bit_AVX512VL)
|
|
|
|
features |= (1 << FEATURE_AVX512VL);
|
|
|
|
if (ebx & bit_AVX512BW)
|
|
|
|
features |= (1 << FEATURE_AVX512BW);
|
|
|
|
if (ebx & bit_AVX512DQ)
|
|
|
|
features |= (1 << FEATURE_AVX512DQ);
|
|
|
|
if (ebx & bit_AVX512CD)
|
|
|
|
features |= (1 << FEATURE_AVX512CD);
|
|
|
|
if (ebx & bit_AVX512PF)
|
|
|
|
features |= (1 << FEATURE_AVX512PF);
|
|
|
|
if (ebx & bit_AVX512ER)
|
|
|
|
features |= (1 << FEATURE_AVX512ER);
|
2015-10-02 17:25:26 +02:00
|
|
|
if (ebx & bit_AVX512IFMA)
|
|
|
|
features |= (1 << FEATURE_AVX512IFMA);
|
|
|
|
if (ecx & bit_AVX512VBMI)
|
|
|
|
features |= (1 << FEATURE_AVX512VBMI);
|
2017-01-12 18:30:03 +01:00
|
|
|
if (ecx & bit_AVX512VPOPCNTDQ)
|
|
|
|
features |= (1 << FEATURE_AVX512VPOPCNTDQ);
|
2016-11-17 23:18:23 +01:00
|
|
|
if (edx & bit_AVX5124VNNIW)
|
|
|
|
features |= (1 << FEATURE_AVX5124VNNIW);
|
|
|
|
if (edx & bit_AVX5124FMAPS)
|
|
|
|
features |= (1 << FEATURE_AVX5124FMAPS);
|
2012-04-26 02:52:09 +02:00
|
|
|
}
|
|
|
|
|
re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
|
|
|
/* Check cpuid level of extended features. */
|
|
|
|
__cpuid (0x80000000, ext_level, ebx, ecx, edx);
|
|
|
|
|
2017-01-12 18:30:03 +01:00
|
|
|
if (ext_level >= 0x80000001)
|
re PR target/59422 (Support more targets for function multi versioning)
gcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/i386.c (get_builtin_code_for_version): Handle
PROCESSOR_HASWELL, PROCESSOR_SILVERMONT, PROCESSOR_BTVER1,
PROCESSOR_BTVER2, PROCESSOR_BDVER3 and PROCESSOR_BDVER4.
Change priority of PROCESSOR_BDVER1 to P_PROC_XOP.
(fold_builtin_cpu): Add "ivybridge", "haswell", "bonnell",
"silvermont", "bobcat" and "jaguar" CPU names. Add "sse4a",
"fma4", "xop" and "fma" ISA names.
libgcc/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
H.J. Lu <hongjiu.lu@intel.com>
PR target/59422
* config/i386/cpuinfo.c (enum processor_types): Add AMD_BOBCAT
and AMD_JAGUAR.
(enum processor_subtypes): Add AMDFAM15H_BDVER3, AMDFAM15H_BDVER4,
INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
(enum processor_features): Add FEATURE_SSE4_A, FEATURE_FMA4,
FEATURE_XOP and FEATURE_FMA.
(get_amd_cpu): Handle AMD_BOBCAT, AMD_JAGUAR, AMDFAM15H_BDVER2 and
AMDFAM15H_BDVER3.
(get_intel_cpu): Handle INTEL_COREI7 and INTEL_COREI7_HASWELL.
(get_available_features): Handle FEATURE_FMA, FEATURE_SSE4_A,
FEATURE_FMA4 and FEATURE_XOP.
testsuite/
2013-12-25 Allan Sandfeld Jensen <sandfeld@kde.org>
PR target/59422
* gcc.target/i386/funcspec-5.c (test_fma, test_xop, test_no_fma,
test_no_xop, test_arch_corei7, test_arch_corei7_avx,
test_arch_core_avx2, test_arch_bdver1, test_arch_bdver2,
test_arch_bdver3, test_tune_corei7, test_tune_corei7_avx,
test_tune_core_avx2, test_tune_bdver1, test_tune_bdver2 and
test_tune_bdver3): New function prototypes.
From-SVN: r206200
2013-12-25 23:22:24 +01:00
|
|
|
{
|
|
|
|
__cpuid (0x80000001, eax, ebx, ecx, edx);
|
|
|
|
|
|
|
|
if (ecx & bit_SSE4a)
|
|
|
|
features |= (1 << FEATURE_SSE4_A);
|
|
|
|
if (ecx & bit_FMA4)
|
|
|
|
features |= (1 << FEATURE_FMA4);
|
|
|
|
if (ecx & bit_XOP)
|
|
|
|
features |= (1 << FEATURE_XOP);
|
|
|
|
}
|
|
|
|
|
2012-04-25 02:08:37 +02:00
|
|
|
__cpu_model.__cpu_features[0] = features;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* A constructor function that is sets __cpu_model and __cpu_features with
|
|
|
|
the right values. This needs to run only once. This constructor is
|
|
|
|
given the highest priority and it should run before constructors without
|
|
|
|
the priority set. However, it still runs after ifunc initializers and
|
|
|
|
needs to be called explicitly there. */
|
|
|
|
|
2012-05-10 10:51:39 +02:00
|
|
|
int __attribute__ ((constructor CONSTRUCTOR_PRIORITY))
|
2012-04-25 02:08:37 +02:00
|
|
|
__cpu_indicator_init (void)
|
|
|
|
{
|
|
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
|
2016-09-28 20:22:16 +02:00
|
|
|
int max_level;
|
2012-04-25 02:08:37 +02:00
|
|
|
unsigned int vendor;
|
|
|
|
unsigned int model, family, brand_id;
|
|
|
|
unsigned int extended_model, extended_family;
|
|
|
|
|
|
|
|
/* This function needs to run just once. */
|
|
|
|
if (__cpu_model.__cpu_vendor)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Assume cpuid insn present. Run in level 0 to get vendor id. */
|
2016-09-28 20:22:16 +02:00
|
|
|
if (!__get_cpuid (0, &eax, &ebx, &ecx, &edx))
|
2012-04-25 04:04:22 +02:00
|
|
|
{
|
|
|
|
__cpu_model.__cpu_vendor = VENDOR_OTHER;
|
|
|
|
return -1;
|
|
|
|
}
|
2012-04-25 02:08:37 +02:00
|
|
|
|
|
|
|
vendor = ebx;
|
|
|
|
max_level = eax;
|
|
|
|
|
|
|
|
if (max_level < 1)
|
2012-04-25 04:04:22 +02:00
|
|
|
{
|
|
|
|
__cpu_model.__cpu_vendor = VENDOR_OTHER;
|
|
|
|
return -1;
|
|
|
|
}
|
2012-04-25 02:08:37 +02:00
|
|
|
|
2016-09-28 20:22:16 +02:00
|
|
|
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
|
2012-04-25 04:04:22 +02:00
|
|
|
{
|
|
|
|
__cpu_model.__cpu_vendor = VENDOR_OTHER;
|
|
|
|
return -1;
|
|
|
|
}
|
2012-04-25 02:08:37 +02:00
|
|
|
|
|
|
|
model = (eax >> 4) & 0x0f;
|
|
|
|
family = (eax >> 8) & 0x0f;
|
|
|
|
brand_id = ebx & 0xff;
|
|
|
|
extended_model = (eax >> 12) & 0xf0;
|
|
|
|
extended_family = (eax >> 20) & 0xff;
|
|
|
|
|
2013-12-26 15:12:20 +01:00
|
|
|
if (vendor == signature_INTEL_ebx)
|
2012-04-25 02:08:37 +02:00
|
|
|
{
|
|
|
|
/* Adjust model and family for Intel CPUS. */
|
|
|
|
if (family == 0x0f)
|
|
|
|
{
|
|
|
|
family += extended_family;
|
|
|
|
model += extended_model;
|
|
|
|
}
|
|
|
|
else if (family == 0x06)
|
|
|
|
model += extended_model;
|
|
|
|
|
|
|
|
/* Get CPU type. */
|
|
|
|
get_intel_cpu (family, model, brand_id);
|
|
|
|
/* Find available features. */
|
2012-04-26 02:52:09 +02:00
|
|
|
get_available_features (ecx, edx, max_level);
|
2012-04-25 02:08:37 +02:00
|
|
|
__cpu_model.__cpu_vendor = VENDOR_INTEL;
|
|
|
|
}
|
2013-12-26 15:12:20 +01:00
|
|
|
else if (vendor == signature_AMD_ebx)
|
2012-04-25 02:08:37 +02:00
|
|
|
{
|
|
|
|
/* Adjust model and family for AMD CPUS. */
|
|
|
|
if (family == 0x0f)
|
|
|
|
{
|
|
|
|
family += extended_family;
|
2015-10-11 10:06:14 +02:00
|
|
|
model += extended_model;
|
2012-04-25 02:08:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Get CPU type. */
|
|
|
|
get_amd_cpu (family, model);
|
|
|
|
/* Find available features. */
|
2012-04-26 02:52:09 +02:00
|
|
|
get_available_features (ecx, edx, max_level);
|
2012-04-25 02:08:37 +02:00
|
|
|
__cpu_model.__cpu_vendor = VENDOR_AMD;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
__cpu_model.__cpu_vendor = VENDOR_OTHER;
|
|
|
|
|
|
|
|
gcc_assert (__cpu_model.__cpu_vendor < VENDOR_MAX);
|
|
|
|
gcc_assert (__cpu_model.__cpu_type < CPU_TYPE_MAX);
|
|
|
|
gcc_assert (__cpu_model.__cpu_subtype < CPU_SUBTYPE_MAX);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2015-04-17 14:58:07 +02:00
|
|
|
|
|
|
|
#if defined SHARED && defined USE_ELF_SYMVER
|
|
|
|
__asm__ (".symver __cpu_indicator_init, __cpu_indicator_init@GCC_4.8.0");
|
|
|
|
__asm__ (".symver __cpu_model, __cpu_model@GCC_4.8.0");
|
|
|
|
#endif
|