2015-01-05 13:33:28 +01:00
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/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
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2012-01-05 22:36:35 +01:00
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Contributed by Richard Henderson <rth@redhat.com>.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef LIBITM_POWERPC_CACHELINE_H
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#define LIBITM_POWERPC_CACHELINE_H 1
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// A cacheline is the smallest unit with which locks are associated.
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// The current implementation of the _ITM_[RW] barriers assumes that
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// all data types can fit (aligned) within a cachline, which means
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// in practice sizeof(complex long double) is the smallest cacheline size.
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// It ought to be small enough for efficient manipulation of the
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// modification mask, below.
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#if defined (__powerpc64__) || defined (__ppc64__)
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# define CACHELINE_SIZE 64
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#else
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# define CACHELINE_SIZE 32
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#endif
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#include "config/generic/cacheline.h"
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#endif // LIBITM_POWERPC_CACHELINE_H
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