2010-11-02 03:35:28 +01:00
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// -*- C++ -*- header.
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2009-12-21 20:00:34 +01:00
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2019-01-01 13:31:55 +01:00
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// Copyright (C) 2008-2019 Free Software Foundation, Inc.
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2009-12-21 20:00:34 +01:00
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//
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// This file is part of the GNU ISO C++ Library. This library is free
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// software; you can redistribute it and/or modify it under the
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// terms of the GNU General Public License as published by the
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// Free Software Foundation; either version 3, or (at your option)
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// any later version.
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// Under Section 7 of GPL version 3, you are granted additional
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// permissions described in the GCC Runtime Library Exception, version
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// 3.1, as published by the Free Software Foundation.
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// You should have received a copy of the GNU General Public License and
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// a copy of the GCC Runtime Library Exception along with this program;
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// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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// <http://www.gnu.org/licenses/>.
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2011-02-16 20:01:51 +01:00
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/** @file bits/atomic_base.h
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2010-11-02 03:35:28 +01:00
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* This is an internal header file, included by other library headers.
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2010-12-19 10:21:16 +01:00
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* Do not attempt to use it directly. @headername{atomic}
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2009-12-21 20:00:34 +01:00
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*/
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#ifndef _GLIBCXX_ATOMIC_BASE_H
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#define _GLIBCXX_ATOMIC_BASE_H 1
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2010-11-02 03:35:28 +01:00
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#pragma GCC system_header
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#include <bits/c++config.h>
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#include <stdint.h>
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2011-12-01 03:20:32 +01:00
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#include <bits/atomic_lockfree_defines.h>
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2019-07-11 21:43:25 +02:00
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#include <bits/move.h>
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2010-11-02 03:35:28 +01:00
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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#ifndef _GLIBCXX_ALWAYS_INLINE
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2015-01-29 13:47:20 +01:00
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#define _GLIBCXX_ALWAYS_INLINE inline __attribute__((__always_inline__))
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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#endif
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PR libstdc++/36104 part four
2011-01-30 Benjamin Kosnik <bkoz@redhat.com>
PR libstdc++/36104 part four
* include/bits/c++config (_GLIBCXX_STD): Remove.
(_GLIBCXX_STD_D, _GLIBCXX_PR): Now _GLIBCXX_STD_C.
(_GLIBCXX_P): Now _GLIBCXX_STD_A.
(_GLIBCXX_NAMESPACE_DEBUG, _GLIBCXX_NAMESPACE_PARALLEL,
_GLIBCXX_NAMESPACE_PROFILE, _GLIBCXX_NAMESPACE_VERSION): Remove.
(_GLIBCXX_INLINE_DEBUG, _GLIBCXX_INLINE_PARALLEL,
_GLIBCXX_INLINE_PROFILE): Remove.
(_GLIBCXX_BEGIN_NAMESPACE(X)): Remove.
(_GLIBCXX_END_NAMESPACE): Remove.
(_GLIBCXX_BEGIN_NESTED_NAMESPACE(X, Y)): Remove.
(_GLIBCXX_END_NESTED_NAMESPACE): Remove.
(_GLIBCXX_BEGIN_NAMESPACE_ALGO): Add.
(_GLIBCXX_END_NAMESPACE_ALGO): Add.
(_GLIBCXX_BEGIN_NAMESPACE_CONTAINER): Add.
(_GLIBCXX_END_NAMESPACE_CONTAINER): Add.
(_GLIBCXX_BEGIN_NAMESPACE_VERSION): Add.
(_GLIBCXX_END_NAMESPACE_VERSION): Add.
(_GLIBCXX_BEGIN_LDBL_NAMESPACE): To _GLIBCXX_BEGIN_NAMESPACE_LDBL.
(_GLIBCXX_END_LDBL_NAMESPACE): To _GLIBCXX_END_NAMESPACE_LDBL.
(_GLIBCXX_VISIBILITY_ATTR): Revert to _GLIBCXX_VISIBILITY.
* include/*: Use new macros for namespace scope.
* config/*: Same.
* src/*: Same.
* src/Makefile.am (sources): Remove debug_list.cc, add
compatibility-debug_list-2.cc.
(parallel_sources): Remove parallel_list.cc, add
compatibility-parallel_list-2.cc.
(compatibility-parallel_list-2.[o,lo]): New rule.
* src/Makefile.in: Regenerate.
* src/debug_list.cc: Remove.
* src/parallel_list.cc: Remove.
* src/compatibility-list-2.cc: New.
* src/compatibility-debug_list-2.cc: New.
* src/compatibility-parallel_list-2.cc: New.
* doc/doxygen/user.cfg.in: Adjust macros.
* testsuite/20_util/auto_ptr/assign_neg.cc: Adjust line numbers, macros.
* testsuite/20_util/declval/requirements/1_neg.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg1.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg2.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg3.cc: Same.
* testsuite/20_util/forward/c_neg.cc: Same.
* testsuite/20_util/forward/f_neg.cc: Same.
* testsuite/20_util/make_signed/requirements/typedefs_neg.cc: Same.
* testsuite/20_util/make_unsigned/requirements/typedefs_neg.cc: Same.
* testsuite/20_util/ratio/cons/cons_overflow_neg.cc: Same.
* testsuite/20_util/ratio/operations/ops_overflow_neg.cc: Same.
* testsuite/20_util/shared_ptr/cons/43820_neg.cc: Same.
* testsuite/20_util/weak_ptr/comparison/cmp_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/insert_neg.cc: Same.
* testsuite/23_containers/forward_list/capacity/1.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
assign_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
insert_neg.cc: Same.
* testsuite/23_containers/list/capacity/29134.cc: Same.
* testsuite/23_containers/list/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/insert_neg.cc: Same.
* testsuite/23_containers/vector/bool/capacity/29134.cc: Same.
* testsuite/23_containers/vector/bool/modifiers/insert/31370.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/insert_neg.cc: Same.
* testsuite/25_algorithms/sort/35588.cc: Same.
* testsuite/27_io/ios_base/cons/assign_neg.cc: Same.
* testsuite/27_io/ios_base/cons/copy_neg.cc: Same.
* testsuite/ext/profile/mutex_extensions_neg.cc: Same.
* testsuite/ext/profile/profiler_algos.cc: Same.
* testsuite/ext/type_traits/add_unsigned_floating_neg.cc: Same.
* testsuite/ext/type_traits/add_unsigned_integer_neg.cc: Same.
* testsuite/ext/type_traits/remove_unsigned_floating_neg.cc: Same.
* testsuite/ext/type_traits/remove_unsigned_integer_neg.cc: Same.
* testsuite/tr1/2_general_utilities/shared_ptr/cons/43820_neg.cc: Same.
From-SVN: r169421
2011-01-30 23:39:36 +01:00
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namespace std _GLIBCXX_VISIBILITY(default)
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{
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_GLIBCXX_BEGIN_NAMESPACE_VERSION
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2009-12-21 20:00:34 +01:00
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/**
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* @defgroup atomics Atomics
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*
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* Components for performing atomic operations.
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* @{
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*/
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/// Enumeration for memory_order
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2019-03-04 21:11:14 +01:00
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#if __cplusplus > 201703L
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enum class memory_order : int
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{
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relaxed,
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consume,
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acquire,
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release,
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acq_rel,
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seq_cst
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};
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inline constexpr memory_order memory_order_relaxed = memory_order::relaxed;
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inline constexpr memory_order memory_order_consume = memory_order::consume;
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inline constexpr memory_order memory_order_acquire = memory_order::acquire;
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inline constexpr memory_order memory_order_release = memory_order::release;
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inline constexpr memory_order memory_order_acq_rel = memory_order::acq_rel;
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inline constexpr memory_order memory_order_seq_cst = memory_order::seq_cst;
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#else
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2009-12-21 20:00:34 +01:00
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typedef enum memory_order
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{
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memory_order_relaxed,
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memory_order_consume,
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memory_order_acquire,
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memory_order_release,
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memory_order_acq_rel,
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memory_order_seq_cst
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} memory_order;
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2019-03-04 21:11:14 +01:00
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#endif
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2009-12-21 20:00:34 +01:00
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libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
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enum __memory_order_modifier
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{
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__memory_order_mask = 0x0ffff,
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__memory_order_modifier_mask = 0xffff0000,
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__memory_order_hle_acquire = 0x10000,
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__memory_order_hle_release = 0x20000
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};
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constexpr memory_order
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operator|(memory_order __m, __memory_order_modifier __mod)
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{
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2019-03-04 21:11:14 +01:00
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return memory_order(int(__m) | int(__mod));
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libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
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}
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constexpr memory_order
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operator&(memory_order __m, __memory_order_modifier __mod)
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{
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2019-03-04 21:11:14 +01:00
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return memory_order(int(__m) & int(__mod));
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libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
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}
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2011-12-08 10:44:57 +01:00
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// Drop release ordering as per [atomics.types.operations.req]/21
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constexpr memory_order
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libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
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__cmpexch_failure_order2(memory_order __m) noexcept
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2010-11-02 03:35:28 +01:00
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{
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2011-12-08 10:44:57 +01:00
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return __m == memory_order_acq_rel ? memory_order_acquire
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: __m == memory_order_release ? memory_order_relaxed : __m;
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2010-11-02 03:35:28 +01:00
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}
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libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
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constexpr memory_order
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__cmpexch_failure_order(memory_order __m) noexcept
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{
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return memory_order(__cmpexch_failure_order2(__m & __memory_order_mask)
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2019-03-04 21:11:14 +01:00
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| __memory_order_modifier(__m & __memory_order_modifier_mask));
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libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
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}
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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_GLIBCXX_ALWAYS_INLINE void
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2011-11-10 21:38:33 +01:00
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atomic_thread_fence(memory_order __m) noexcept
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2019-03-04 21:11:14 +01:00
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{ __atomic_thread_fence(int(__m)); }
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2011-02-16 20:01:51 +01:00
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-10 21:38:33 +01:00
|
|
|
atomic_signal_fence(memory_order __m) noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ __atomic_signal_fence(int(__m)); }
|
2011-02-16 20:01:51 +01:00
|
|
|
|
2010-11-02 03:35:28 +01:00
|
|
|
/// kill_dependency
|
|
|
|
template<typename _Tp>
|
|
|
|
inline _Tp
|
2011-08-04 21:57:48 +02:00
|
|
|
kill_dependency(_Tp __y) noexcept
|
2010-11-02 03:35:28 +01:00
|
|
|
{
|
2011-01-28 17:59:49 +01:00
|
|
|
_Tp __ret(__y);
|
|
|
|
return __ret;
|
2010-11-02 03:35:28 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Base types for atomics.
|
2011-11-06 15:55:48 +01:00
|
|
|
template<typename _IntTp>
|
|
|
|
struct __atomic_base;
|
2010-11-02 03:35:28 +01:00
|
|
|
|
|
|
|
|
|
|
|
#define ATOMIC_VAR_INIT(_VI) { _VI }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
struct atomic;
|
2009-12-21 20:00:34 +01:00
|
|
|
|
2011-02-16 20:01:51 +01:00
|
|
|
template<typename _Tp>
|
|
|
|
struct atomic<_Tp*>;
|
|
|
|
|
2013-02-27 00:46:21 +01:00
|
|
|
/* The target's "set" value for test-and-set may not be exactly 1. */
|
|
|
|
#if __GCC_ATOMIC_TEST_AND_SET_TRUEVAL == 1
|
|
|
|
typedef bool __atomic_flag_data_type;
|
|
|
|
#else
|
|
|
|
typedef unsigned char __atomic_flag_data_type;
|
|
|
|
#endif
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Base type for atomic_flag.
|
|
|
|
*
|
|
|
|
* Base type is POD with data, allowing atomic_flag to derive from
|
|
|
|
* it and meet the standard layout type requirement. In addition to
|
2013-11-15 17:33:59 +01:00
|
|
|
* compatibility with a C interface, this allows different
|
2011-11-06 15:55:48 +01:00
|
|
|
* implementations of atomic_flag to use the same atomic operation
|
|
|
|
* functions, via a standard conversion to the __atomic_flag_base
|
|
|
|
* argument.
|
|
|
|
*/
|
|
|
|
_GLIBCXX_BEGIN_EXTERN_C
|
|
|
|
|
|
|
|
struct __atomic_flag_base
|
|
|
|
{
|
2013-02-27 00:46:21 +01:00
|
|
|
__atomic_flag_data_type _M_i;
|
2011-11-06 15:55:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
_GLIBCXX_END_EXTERN_C
|
|
|
|
|
2012-01-26 22:50:52 +01:00
|
|
|
#define ATOMIC_FLAG_INIT { 0 }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
/// atomic_flag
|
|
|
|
struct atomic_flag : public __atomic_flag_base
|
|
|
|
{
|
|
|
|
atomic_flag() noexcept = default;
|
|
|
|
~atomic_flag() noexcept = default;
|
|
|
|
atomic_flag(const atomic_flag&) = delete;
|
|
|
|
atomic_flag& operator=(const atomic_flag&) = delete;
|
|
|
|
atomic_flag& operator=(const atomic_flag&) volatile = delete;
|
|
|
|
|
|
|
|
// Conversion to ATOMIC_FLAG_INIT.
|
2012-01-26 22:50:52 +01:00
|
|
|
constexpr atomic_flag(bool __i) noexcept
|
2013-02-27 00:46:21 +01:00
|
|
|
: __atomic_flag_base{ _S_init(__i) }
|
2012-01-26 22:50:52 +01:00
|
|
|
{ }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
test_and_set(memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_test_and_set (&_M_i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
test_and_set(memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_test_and_set (&_M_i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
clear(memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
__atomic_clear (&_M_i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
clear(memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
__atomic_clear (&_M_i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
2013-02-27 00:46:21 +01:00
|
|
|
|
|
|
|
private:
|
|
|
|
static constexpr __atomic_flag_data_type
|
|
|
|
_S_init(bool __i)
|
|
|
|
{ return __i ? __GCC_ATOMIC_TEST_AND_SET_TRUEVAL : 0; }
|
2011-11-06 15:55:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/// Base class for atomic integrals.
|
|
|
|
//
|
|
|
|
// For each of the integral types, define atomic_[integral type] struct
|
|
|
|
//
|
|
|
|
// atomic_bool bool
|
|
|
|
// atomic_char char
|
|
|
|
// atomic_schar signed char
|
|
|
|
// atomic_uchar unsigned char
|
|
|
|
// atomic_short short
|
|
|
|
// atomic_ushort unsigned short
|
|
|
|
// atomic_int int
|
|
|
|
// atomic_uint unsigned int
|
|
|
|
// atomic_long long
|
|
|
|
// atomic_ulong unsigned long
|
|
|
|
// atomic_llong long long
|
|
|
|
// atomic_ullong unsigned long long
|
P0482R5 char8_t: Standard library support
gcc/cp:
2019-02-19 Tom Honermann <tom@honermann.net>
* name-lookup.c (get_std_name_hint): Added u8string as a name hint.
libstdc++:
2019-02-19 Tom Honermann <tom@honermann.net>
P0482R5 char8_t: Standard library support
* config/abi/pre/gnu-versioned-namespace.ver (CXXABI_2.0): Add
typeinfo symbols for char8_t.
* config/abi/pre/gnu.ver: Add CXXABI_1.3.12.
(GLIBCXX_3.4.26): Add symbols for specializations of
numeric_limits and codecvt that involve char8_t.
(CXXABI_1.3.12): Add typeinfo symbols for char8_t.
* include/bits/atomic_base.h: Add atomic_char8_t.
* include/bits/basic_string.h: Add std::hash<u8string> and
operator""s(const char8_t*, size_t).
* include/bits/c++config: Define _GLIBCXX_USE_CHAR8_T and
__cpp_lib_char8_t.
* include/bits/char_traits.h: Add char_traits<char8_t>.
* include/bits/codecvt.h: Add
codecvt<char16_t, char8_t, mbstate_t>,
codecvt<char32_t, char8_t, mbstate_t>,
codecvt_byname<char16_t, char8_t, mbstate_t>, and
codecvt_byname<char32_t, char8_t, mbstate_t>.
* include/bits/cpp_type_traits.h: Add __is_integer<char8_t> to
recognize char8_t as an integral type.
* include/bits/fs_path.h: (path::__is_encoded_char): Recognize
char8_t.
(path::u8string): Return std::u8string when char8_t support is
enabled.
(path::generic_u8string): Likewise.
(path::_S_convert): Handle conversion from char8_t input.
(path::_S_str_convert): Likewise.
* include/bits/functional_hash.h: Add hash<char8_t>.
* include/bits/locale_conv.h (__str_codecvt_out): Add overloads for
char8_t.
* include/bits/locale_facets.h (_GLIBCXX_NUM_UNICODE_FACETS): Bump
for new char8_t specializations.
* include/bits/localefwd.h: Add missing declarations of
codecvt<char16_t, char, mbstate_t> and
codecvt<char32_t, char, mbstate_t>. Add char8_t declarations
codecvt<char16_t, char8_t, mbstate_t> and
codecvt<char32_t, char8_t, mbstate_t>.
* include/bits/postypes.h: Add u8streampos
* include/bits/stringfwd.h: Add declarations of
char_traits<char8_t> and u8string.
* include/c_global/cstddef: Add __byte_operand<char8_t>.
* include/experimental/bits/fs_path.h (path::__is_encoded_char):
Recognize char8_t.
(path::u8string): Return std::u8string when char8_t support is
enabled.
(path::generic_u8string): Likewise.
(path::_S_convert): Handle conversion from char8_t input.
(path::_S_str_convert): Likewise.
* include/experimental/string: Add u8string.
* include/experimental/string_view: Add u8string_view,
hash<experimental::u8string_view>, and
operator""sv(const char8_t*, size_t).
* include/std/atomic: Add atomic<char8_t> and atomic_char8_t.
* include/std/charconv (__is_int_to_chars_type): Recognize char8_t
as a character type.
* include/std/limits: Add numeric_limits<char8_t>.
* include/std/string_view: Add u8string_view,
hash<experimental::u8string_view>, and
operator""sv(const char8_t*, size_t).
* include/std/type_traits: Add __is_integral_helper<char8_t>,
__make_unsigned<char8_t>, and __make_signed<char8_t>.
* libsupc++/atomic_lockfree_defines.h: Define
ATOMIC_CHAR8_T_LOCK_FREE.
* src/c++11/Makefile.am: Compile with -fchar8_t when compiling
codecvt.cc and limits.cc so that char8_t specializations of
numeric_limits and codecvt and emitted.
* src/c++11/Makefile.in: Likewise.
* src/c++11/codecvt.cc: Define members of
codecvt<char16_t, char8_t, mbstate_t>,
codecvt<char32_t, char8_t, mbstate_t>,
codecvt_byname<char16_t, char8_t, mbstate_t>, and
codecvt_byname<char32_t, char8_t, mbstate_t>.
* src/c++11/limits.cc: Define members of
numeric_limits<char8_t>.
* src/c++98/Makefile.am: Compile with -fchar8_t when compiling
locale_init.cc and localename.cc.
* src/c++98/Makefile.in: Likewise.
* src/c++98/locale_init.cc: Add initialization for the
codecvt<char16_t, char8_t, mbstate_t> and
codecvt<char32_t, char8_t, mbstate_t> facets.
* src/c++98/localename.cc: Likewise.
* testsuite/util/testsuite_abi.cc: Validate ABI bump.
From-SVN: r269004
2019-02-19 03:54:42 +01:00
|
|
|
// atomic_char8_t char8_t
|
2011-11-06 15:55:48 +01:00
|
|
|
// atomic_char16_t char16_t
|
|
|
|
// atomic_char32_t char32_t
|
|
|
|
// atomic_wchar_t wchar_t
|
|
|
|
//
|
|
|
|
// NB: Assuming _ITp is an integral scalar type that is 1, 2, 4, or
|
|
|
|
// 8 bytes, since that is what GCC built-in functions for atomic
|
|
|
|
// memory access expect.
|
|
|
|
template<typename _ITp>
|
|
|
|
struct __atomic_base
|
|
|
|
{
|
Implement P0558R2 changes to std::atomic
The restrictions forbidding arithmetic on atomic pointer types are only
enabled for C++17 and later, retaining the GNU extension for older
standards. The new nested typedefs and changes to prevent scalar
parameters participating in template argument deduction are enabled
unconditionally.
PR libstdc++/69769
PR libstdc++/85886
* include/bits/atomic_base.h (__atomic_base::value_type)
(__atomic_base::difference_type): Add new typedefs.
* include/std/atomic (atomic<bool>::value_type, atomic<T>::value_type)
(atomic<T*>::value_type, atomic<T*>::difference_type): Likewise.
(atomic<T*>::operator++, atomic<T*>::operator--)
(atomic<T*>::operator+=, atomic<T*>::operator-=)
(atomic<T*>::fetch_add, atomic<T*>::fetch_sub): Add static assertion
to enforce C++17 requirement on pointer arithmetic.
(__atomic_val_t, __atomic_diff_t): New alias templates.
(atomic_init, atomic_store_explicit, atomic_exchange_explicit)
(atomic_compare_exchange_weak_explicit)
(atomic_compare_exchange_strong_explicit, atomic_store)
(atomic_exchange, atomic_compare_exchange_weak)
(atomic_compare_exchange_strong): Use __atomic_val_t to make
scalar parameters be non-deduced contexts.
(atomic_fetch_add_explicit, atomic_fetch_sub_explicit)
(atomic_fetch_add, atomic_fetch_sub): Change first parameter to be
atomic instead of __atomic_base, and use __atomic_diff_t for scalar
parameters.
(atomic_fetch_and_explicit, atomic_fetch_or_explicit)
(atomic_fetch_xor_explicit, atomic_fetch_and, atomic_fetch_or)
(atomic_fetch_xor): Use __atomic_val_t for scalar parameters.
(atomic_fetch_add_explicit, atomic_fetch_sub_explicit)
(atomic_fetch_add, atomic_fetch_sub): Remove overloads for atomic
address types.
* testsuite/29_atomics/atomic/60695.cc: Adjust dg-error lineno.
* testsuite/29_atomics/atomic/69769.cc: New test.
* testsuite/29_atomics/atomic/nonmembers.cc: New test.
* testsuite/29_atomics/atomic/operators/pointer_partial_void.cc:
Disable test for C++17 and later.
* testsuite/29_atomics/atomic/requirements/typedefs.cc: New test.
* testsuite/29_atomics/atomic_integral/nonmembers.cc: New test.
* testsuite/29_atomics/atomic_integral/requirements/typedefs.cc: New
test.
From-SVN: r260676
2018-05-24 17:28:26 +02:00
|
|
|
using value_type = _ITp;
|
|
|
|
using difference_type = value_type;
|
|
|
|
|
2011-11-06 15:55:48 +01:00
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private:
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typedef _ITp __int_type;
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2015-04-09 13:15:44 +02:00
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static constexpr int _S_alignment =
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sizeof(_ITp) > alignof(_ITp) ? sizeof(_ITp) : alignof(_ITp);
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alignas(_S_alignment) __int_type _M_i;
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2011-11-06 15:55:48 +01:00
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public:
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__atomic_base() noexcept = default;
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~__atomic_base() noexcept = default;
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__atomic_base(const __atomic_base&) = delete;
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__atomic_base& operator=(const __atomic_base&) = delete;
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__atomic_base& operator=(const __atomic_base&) volatile = delete;
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// Requires __int_type convertible to _M_i.
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constexpr __atomic_base(__int_type __i) noexcept : _M_i (__i) { }
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operator __int_type() const noexcept
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{ return load(); }
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operator __int_type() const volatile noexcept
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{ return load(); }
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__int_type
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operator=(__int_type __i) noexcept
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{
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store(__i);
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return __i;
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}
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__int_type
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operator=(__int_type __i) volatile noexcept
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{
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store(__i);
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return __i;
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}
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__int_type
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operator++(int) noexcept
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{ return fetch_add(1); }
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__int_type
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operator++(int) volatile noexcept
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{ return fetch_add(1); }
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__int_type
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operator--(int) noexcept
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{ return fetch_sub(1); }
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__int_type
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operator--(int) volatile noexcept
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{ return fetch_sub(1); }
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__int_type
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operator++() noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
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{ return __atomic_add_fetch(&_M_i, 1, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
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__int_type
|
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operator++() volatile noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_i, 1, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
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__int_type
|
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operator--() noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_i, 1, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
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__int_type
|
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operator--() volatile noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_i, 1, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
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|
__int_type
|
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operator+=(__int_type __i) noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
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|
__int_type
|
|
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|
operator+=(__int_type __i) volatile noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator-=(__int_type __i) noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator-=(__int_type __i) volatile noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator&=(__int_type __i) noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_and_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator&=(__int_type __i) volatile noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_and_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator|=(__int_type __i) noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_or_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator|=(__int_type __i) volatile noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_or_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator^=(__int_type __i) noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_xor_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator^=(__int_type __i) volatile noexcept
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
{ return __atomic_xor_fetch(&_M_i, __i, int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
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|
|
bool
|
|
|
|
is_lock_free() const noexcept
|
2015-03-26 19:31:11 +01:00
|
|
|
{
|
2015-09-17 17:46:04 +02:00
|
|
|
// Use a fake, minimally aligned pointer.
|
|
|
|
return __atomic_is_lock_free(sizeof(_M_i),
|
2018-11-11 23:20:19 +01:00
|
|
|
reinterpret_cast<void *>(-_S_alignment));
|
2015-03-26 19:31:11 +01:00
|
|
|
}
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const volatile noexcept
|
2015-03-26 19:31:11 +01:00
|
|
|
{
|
2015-09-17 17:46:04 +02:00
|
|
|
// Use a fake, minimally aligned pointer.
|
|
|
|
return __atomic_is_lock_free(sizeof(_M_i),
|
2018-11-11 23:20:19 +01:00
|
|
|
reinterpret_cast<void *>(-_S_alignment));
|
2015-03-26 19:31:11 +01:00
|
|
|
}
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
store(__int_type __i, memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
__atomic_store_n(&_M_i, __i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
store(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
__atomic_store_n(&_M_i, __i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
load(memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_release);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_load_n(&_M_i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
load(memory_order __m = memory_order_seq_cst) const volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_release);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_load_n(&_M_i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
exchange(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_exchange_n(&_M_i, __i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
exchange(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_exchange_n(&_M_i, __i, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_weak(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m1, memory_order __m2) noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_compare_exchange_n(&_M_i, &__i1, __i2, 1,
|
|
|
|
int(__m1), int(__m2));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_weak(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m1,
|
|
|
|
memory_order __m2) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_compare_exchange_n(&_M_i, &__i1, __i2, 1,
|
|
|
|
int(__m1), int(__m2));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_weak(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__i1, __i2, __m,
|
2011-12-08 10:44:57 +01:00
|
|
|
__cmpexch_failure_order(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_weak(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__i1, __i2, __m,
|
2011-12-08 10:44:57 +01:00
|
|
|
__cmpexch_failure_order(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m1, memory_order __m2) noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_compare_exchange_n(&_M_i, &__i1, __i2, 0,
|
|
|
|
int(__m1), int(__m2));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m1,
|
|
|
|
memory_order __m2) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
|
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_compare_exchange_n(&_M_i, &__i1, __i2, 0,
|
|
|
|
int(__m1), int(__m2));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__i1, __i2, __m,
|
2011-12-08 10:44:57 +01:00
|
|
|
__cmpexch_failure_order(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__i1, __i2, __m,
|
2011-12-08 10:44:57 +01:00
|
|
|
__cmpexch_failure_order(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_add(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_add(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_add(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_add(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_sub(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_sub(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_sub(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_sub(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_and(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_and(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_and(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_and(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_or(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_or(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_or(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_or(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_xor(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_xor(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_xor(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_xor(&_M_i, __i, int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/// Partial specialization for pointer types.
|
|
|
|
template<typename _PTp>
|
|
|
|
struct __atomic_base<_PTp*>
|
|
|
|
{
|
|
|
|
private:
|
|
|
|
typedef _PTp* __pointer_type;
|
|
|
|
|
|
|
|
__pointer_type _M_p;
|
|
|
|
|
2012-02-03 20:49:11 +01:00
|
|
|
// Factored out to facilitate explicit specialization.
|
|
|
|
constexpr ptrdiff_t
|
2014-04-15 20:28:41 +02:00
|
|
|
_M_type_size(ptrdiff_t __d) const { return __d * sizeof(_PTp); }
|
2012-02-03 20:49:11 +01:00
|
|
|
|
|
|
|
constexpr ptrdiff_t
|
2014-04-15 20:28:41 +02:00
|
|
|
_M_type_size(ptrdiff_t __d) const volatile { return __d * sizeof(_PTp); }
|
2012-02-03 20:49:11 +01:00
|
|
|
|
2011-11-06 15:55:48 +01:00
|
|
|
public:
|
|
|
|
__atomic_base() noexcept = default;
|
|
|
|
~__atomic_base() noexcept = default;
|
|
|
|
__atomic_base(const __atomic_base&) = delete;
|
|
|
|
__atomic_base& operator=(const __atomic_base&) = delete;
|
|
|
|
__atomic_base& operator=(const __atomic_base&) volatile = delete;
|
|
|
|
|
|
|
|
// Requires __pointer_type convertible to _M_p.
|
|
|
|
constexpr __atomic_base(__pointer_type __p) noexcept : _M_p (__p) { }
|
|
|
|
|
|
|
|
operator __pointer_type() const noexcept
|
|
|
|
{ return load(); }
|
|
|
|
|
|
|
|
operator __pointer_type() const volatile noexcept
|
|
|
|
{ return load(); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator=(__pointer_type __p) noexcept
|
|
|
|
{
|
|
|
|
store(__p);
|
|
|
|
return __p;
|
|
|
|
}
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator=(__pointer_type __p) volatile noexcept
|
|
|
|
{
|
|
|
|
store(__p);
|
|
|
|
return __p;
|
|
|
|
}
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator++(int) noexcept
|
|
|
|
{ return fetch_add(1); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator++(int) volatile noexcept
|
|
|
|
{ return fetch_add(1); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator--(int) noexcept
|
|
|
|
{ return fetch_sub(1); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator--(int) volatile noexcept
|
|
|
|
{ return fetch_sub(1); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator++() noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_p, _M_type_size(1),
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator++() volatile noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_p, _M_type_size(1),
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator--() noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_p, _M_type_size(1),
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator--() volatile noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_p, _M_type_size(1),
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator+=(ptrdiff_t __d) noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_p, _M_type_size(__d),
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator+=(ptrdiff_t __d) volatile noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_p, _M_type_size(__d),
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator-=(ptrdiff_t __d) noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_p, _M_type_size(__d),
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator-=(ptrdiff_t __d) volatile noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_p, _M_type_size(__d),
|
re PR libstdc++/89641 (std::atomic<T> no longer works)
PR libstdc++/89641
* include/std/atomic (atomic<T>::store, atomic<T>::load,
atomic<T>::exchange, atomic<T>::compare_exchange_weak,
atomic<T>::compare_exchange_strong): Cast __m or __s and __f to int.
* include/bits/atomic_base.h (__atomic_base<T>::operator++,
__atomic_base<T>::operator--, __atomic_base<T>::operator+=,
__atomic_base<T>::operator-=, __atomic_base<T>::operator&=,
__atomic_base<T>::operator|=, __atomic_base<T>::operator^=,
__atomic_base<T*>::operator++, __atomic_base<T*>::operator--,
__atomic_base<T*>::operator+=, __atomic_base<T*>::operator-=): Cast
memory_order_seq_cst to int.
From-SVN: r269582
2019-03-11 12:49:13 +01:00
|
|
|
int(memory_order_seq_cst)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const noexcept
|
2015-03-26 19:31:11 +01:00
|
|
|
{
|
|
|
|
// Produce a fake, minimally aligned pointer.
|
2015-09-17 17:46:04 +02:00
|
|
|
return __atomic_is_lock_free(sizeof(_M_p),
|
|
|
|
reinterpret_cast<void *>(-__alignof(_M_p)));
|
2015-03-26 19:31:11 +01:00
|
|
|
}
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const volatile noexcept
|
2015-03-26 19:31:11 +01:00
|
|
|
{
|
|
|
|
// Produce a fake, minimally aligned pointer.
|
2015-09-17 17:46:04 +02:00
|
|
|
return __atomic_is_lock_free(sizeof(_M_p),
|
|
|
|
reinterpret_cast<void *>(-__alignof(_M_p)));
|
2015-03-26 19:31:11 +01:00
|
|
|
}
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
store(__pointer_type __p,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
|
|
|
|
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
__atomic_store_n(&_M_p, __p, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
store(__pointer_type __p,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
__atomic_store_n(&_M_p, __p, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
load(memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_release);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_load_n(&_M_p, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
load(memory_order __m = memory_order_seq_cst) const volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_release);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_load_n(&_M_p, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
exchange(__pointer_type __p,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_exchange_n(&_M_p, __p, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
exchange(__pointer_type __p,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_exchange_n(&_M_p, __p, int(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__pointer_type& __p1, __pointer_type __p2,
|
|
|
|
memory_order __m1,
|
|
|
|
memory_order __m2) noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_compare_exchange_n(&_M_p, &__p1, __p2, 0,
|
|
|
|
int(__m1), int(__m2));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__pointer_type& __p1, __pointer_type __p2,
|
|
|
|
memory_order __m1,
|
|
|
|
memory_order __m2) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
|
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2019-03-04 21:11:14 +01:00
|
|
|
return __atomic_compare_exchange_n(&_M_p, &__p1, __p2, 0,
|
|
|
|
int(__m1), int(__m2));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_add(ptrdiff_t __d,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_add(&_M_p, _M_type_size(__d), int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_add(ptrdiff_t __d,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_add(&_M_p, _M_type_size(__d), int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_sub(ptrdiff_t __d,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_sub(&_M_p, _M_type_size(__d), int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_sub(ptrdiff_t __d,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
2019-03-04 21:11:14 +01:00
|
|
|
{ return __atomic_fetch_sub(&_M_p, _M_type_size(__d), int(__m)); }
|
2011-11-06 15:55:48 +01:00
|
|
|
};
|
|
|
|
|
2019-07-11 21:43:25 +02:00
|
|
|
#if __cplusplus > 201703L
|
|
|
|
// Implementation details of atomic_ref and atomic<floating-point>.
|
|
|
|
namespace __atomic_impl
|
|
|
|
{
|
|
|
|
// Remove volatile and create a non-deduced context for value arguments.
|
|
|
|
template<typename _Tp>
|
|
|
|
using _Val = remove_volatile_t<_Tp>;
|
|
|
|
|
|
|
|
// As above, but for difference_type arguments.
|
|
|
|
template<typename _Tp>
|
|
|
|
using _Diff = conditional_t<is_pointer_v<_Tp>, ptrdiff_t, _Val<_Tp>>;
|
|
|
|
|
|
|
|
template<size_t _Size, size_t _Align>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
|
|
|
is_lock_free() noexcept
|
|
|
|
{
|
|
|
|
// Produce a fake, minimally aligned pointer.
|
|
|
|
return __atomic_is_lock_free(_Size, reinterpret_cast<void *>(-_Align));
|
|
|
|
}
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
|
|
|
store(_Tp* __ptr, _Val<_Tp> __t, memory_order __m) noexcept
|
|
|
|
{ __atomic_store(__ptr, std::__addressof(__t), int(__m)); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
load(_Tp* __ptr, memory_order __m) noexcept
|
|
|
|
{
|
|
|
|
alignas(_Tp) unsigned char __buf[sizeof(_Tp)];
|
|
|
|
_Tp* __dest = reinterpret_cast<_Tp*>(__buf);
|
|
|
|
__atomic_load(__ptr, __dest, int(__m));
|
|
|
|
return *__dest;
|
|
|
|
}
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
exchange(_Tp* __ptr, _Val<_Tp> __desired, memory_order __m) noexcept
|
|
|
|
{
|
|
|
|
alignas(_Tp) unsigned char __buf[sizeof(_Tp)];
|
|
|
|
_Tp* __dest = reinterpret_cast<_Tp*>(__buf);
|
|
|
|
__atomic_exchange(__ptr, std::__addressof(__desired), __dest, int(__m));
|
|
|
|
return *__dest;
|
|
|
|
}
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
|
|
|
compare_exchange_weak(_Tp* __ptr, _Val<_Tp>& __expected,
|
|
|
|
_Val<_Tp> __desired, memory_order __success,
|
|
|
|
memory_order __failure) noexcept
|
|
|
|
{
|
|
|
|
return __atomic_compare_exchange(__ptr, std::__addressof(__expected),
|
|
|
|
std::__addressof(__desired), true,
|
|
|
|
int(__success), int(__failure));
|
|
|
|
}
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
|
|
|
compare_exchange_strong(_Tp* __ptr, _Val<_Tp>& __expected,
|
|
|
|
_Val<_Tp> __desired, memory_order __success,
|
|
|
|
memory_order __failure) noexcept
|
|
|
|
{
|
|
|
|
return __atomic_compare_exchange(__ptr, std::__addressof(__expected),
|
|
|
|
std::__addressof(__desired), false,
|
|
|
|
int(__success), int(__failure));
|
|
|
|
}
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
fetch_add(_Tp* __ptr, _Diff<_Tp> __i, memory_order __m) noexcept
|
|
|
|
{ return __atomic_fetch_add(__ptr, __i, int(__m)); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
fetch_sub(_Tp* __ptr, _Diff<_Tp> __i, memory_order __m) noexcept
|
|
|
|
{ return __atomic_fetch_sub(__ptr, __i, int(__m)); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
fetch_and(_Tp* __ptr, _Val<_Tp> __i, memory_order __m) noexcept
|
|
|
|
{ return __atomic_fetch_and(__ptr, __i, int(__m)); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
fetch_or(_Tp* __ptr, _Val<_Tp> __i, memory_order __m) noexcept
|
|
|
|
{ return __atomic_fetch_or(__ptr, __i, int(__m)); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
fetch_xor(_Tp* __ptr, _Val<_Tp> __i, memory_order __m) noexcept
|
|
|
|
{ return __atomic_fetch_xor(__ptr, __i, int(__m)); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
__add_fetch(_Tp* __ptr, _Diff<_Tp> __i) noexcept
|
|
|
|
{ return __atomic_add_fetch(__ptr, __i, __ATOMIC_SEQ_CST); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
__sub_fetch(_Tp* __ptr, _Diff<_Tp> __i) noexcept
|
|
|
|
{ return __atomic_sub_fetch(__ptr, __i, __ATOMIC_SEQ_CST); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
__and_fetch(_Tp* __ptr, _Val<_Tp> __i) noexcept
|
|
|
|
{ return __atomic_and_fetch(__ptr, __i, __ATOMIC_SEQ_CST); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
__or_fetch(_Tp* __ptr, _Val<_Tp> __i) noexcept
|
|
|
|
{ return __atomic_or_fetch(__ptr, __i, __ATOMIC_SEQ_CST); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_GLIBCXX_ALWAYS_INLINE _Tp
|
|
|
|
__xor_fetch(_Tp* __ptr, _Val<_Tp> __i) noexcept
|
|
|
|
{ return __atomic_xor_fetch(__ptr, __i, __ATOMIC_SEQ_CST); }
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_Tp
|
|
|
|
__fetch_add_flt(_Tp* __ptr, _Val<_Tp> __i, memory_order __m) noexcept
|
|
|
|
{
|
|
|
|
_Val<_Tp> __oldval = load(__ptr, memory_order_relaxed);
|
|
|
|
_Val<_Tp> __newval = __oldval + __i;
|
|
|
|
while (!compare_exchange_weak(__ptr, __oldval, __newval, __m,
|
|
|
|
memory_order_relaxed))
|
|
|
|
__newval = __oldval + __i;
|
|
|
|
return __oldval;
|
|
|
|
}
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_Tp
|
|
|
|
__fetch_sub_flt(_Tp* __ptr, _Val<_Tp> __i, memory_order __m) noexcept
|
|
|
|
{
|
|
|
|
_Val<_Tp> __oldval = load(__ptr, memory_order_relaxed);
|
|
|
|
_Val<_Tp> __newval = __oldval - __i;
|
|
|
|
while (!compare_exchange_weak(__ptr, __oldval, __newval, __m,
|
|
|
|
memory_order_relaxed))
|
|
|
|
__newval = __oldval - __i;
|
|
|
|
return __oldval;
|
|
|
|
}
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_Tp
|
|
|
|
__add_fetch_flt(_Tp* __ptr, _Val<_Tp> __i) noexcept
|
|
|
|
{
|
|
|
|
_Val<_Tp> __oldval = load(__ptr, memory_order_relaxed);
|
|
|
|
_Val<_Tp> __newval = __oldval + __i;
|
|
|
|
while (!compare_exchange_weak(__ptr, __oldval, __newval,
|
|
|
|
memory_order_seq_cst,
|
|
|
|
memory_order_relaxed))
|
|
|
|
__newval = __oldval + __i;
|
|
|
|
return __newval;
|
|
|
|
}
|
|
|
|
|
|
|
|
template<typename _Tp>
|
|
|
|
_Tp
|
|
|
|
__sub_fetch_flt(_Tp* __ptr, _Val<_Tp> __i) noexcept
|
|
|
|
{
|
|
|
|
_Val<_Tp> __oldval = load(__ptr, memory_order_relaxed);
|
|
|
|
_Val<_Tp> __newval = __oldval - __i;
|
|
|
|
while (!compare_exchange_weak(__ptr, __oldval, __newval,
|
|
|
|
memory_order_seq_cst,
|
|
|
|
memory_order_relaxed))
|
|
|
|
__newval = __oldval - __i;
|
|
|
|
return __newval;
|
|
|
|
}
|
|
|
|
} // namespace __atomic_impl
|
|
|
|
|
|
|
|
// base class for atomic<floating-point-type>
|
|
|
|
template<typename _Fp>
|
|
|
|
struct __atomic_float
|
|
|
|
{
|
|
|
|
static_assert(is_floating_point_v<_Fp>);
|
|
|
|
|
|
|
|
static constexpr size_t _S_alignment = __alignof__(_Fp);
|
|
|
|
|
|
|
|
public:
|
|
|
|
using value_type = _Fp;
|
|
|
|
using difference_type = value_type;
|
|
|
|
|
|
|
|
static constexpr bool is_always_lock_free
|
|
|
|
= __atomic_always_lock_free(sizeof(_Fp), 0);
|
|
|
|
|
|
|
|
__atomic_float() = default;
|
|
|
|
|
|
|
|
constexpr
|
|
|
|
__atomic_float(_Fp __t) : _M_fp(__t)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
__atomic_float(const __atomic_float&) = delete;
|
|
|
|
__atomic_float& operator=(const __atomic_float&) = delete;
|
|
|
|
__atomic_float& operator=(const __atomic_float&) volatile = delete;
|
|
|
|
|
|
|
|
_Fp
|
|
|
|
operator=(_Fp __t) volatile noexcept
|
|
|
|
{
|
|
|
|
this->store(__t);
|
|
|
|
return __t;
|
|
|
|
}
|
|
|
|
|
|
|
|
_Fp
|
|
|
|
operator=(_Fp __t) noexcept
|
|
|
|
{
|
|
|
|
this->store(__t);
|
|
|
|
return __t;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const volatile noexcept
|
|
|
|
{ return __atomic_impl::is_lock_free<sizeof(_Fp), _S_alignment>(); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const noexcept
|
|
|
|
{ return __atomic_impl::is_lock_free<sizeof(_Fp), _S_alignment>(); }
|
|
|
|
|
|
|
|
void
|
|
|
|
store(_Fp __t, memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{ __atomic_impl::store(&_M_fp, __t, __m); }
|
|
|
|
|
|
|
|
void
|
|
|
|
store(_Fp __t, memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{ __atomic_impl::store(&_M_fp, __t, __m); }
|
|
|
|
|
|
|
|
_Fp
|
|
|
|
load(memory_order __m = memory_order_seq_cst) const volatile noexcept
|
|
|
|
{ return __atomic_impl::load(&_M_fp, __m); }
|
|
|
|
|
|
|
|
_Fp
|
|
|
|
load(memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::load(&_M_fp, __m); }
|
|
|
|
|
|
|
|
operator _Fp() const volatile noexcept { return this->load(); }
|
|
|
|
operator _Fp() const noexcept { return this->load(); }
|
|
|
|
|
|
|
|
_Fp
|
|
|
|
exchange(_Fp __desired,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{ return __atomic_impl::exchange(&_M_fp, __desired, __m); }
|
|
|
|
|
|
|
|
_Fp
|
|
|
|
exchange(_Fp __desired,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{ return __atomic_impl::exchange(&_M_fp, __desired, __m); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_weak(&_M_fp,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) volatile noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_weak(&_M_fp,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_strong(&_M_fp,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) volatile noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_strong(&_M_fp,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
volatile noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
volatile noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_add(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{ return __atomic_impl::__fetch_add_flt(&_M_fp, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_add(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{ return __atomic_impl::__fetch_add_flt(&_M_fp, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_sub(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{ return __atomic_impl::__fetch_sub_flt(&_M_fp, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_sub(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{ return __atomic_impl::__fetch_sub_flt(&_M_fp, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator+=(value_type __i) noexcept
|
|
|
|
{ return __atomic_impl::__add_fetch_flt(&_M_fp, __i); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator+=(value_type __i) volatile noexcept
|
|
|
|
{ return __atomic_impl::__add_fetch_flt(&_M_fp, __i); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator-=(value_type __i) noexcept
|
|
|
|
{ return __atomic_impl::__sub_fetch_flt(&_M_fp, __i); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator-=(value_type __i) volatile noexcept
|
|
|
|
{ return __atomic_impl::__sub_fetch_flt(&_M_fp, __i); }
|
|
|
|
|
|
|
|
private:
|
|
|
|
alignas(_S_alignment) _Fp _M_fp;
|
|
|
|
};
|
|
|
|
|
|
|
|
template<typename _Tp,
|
|
|
|
bool = is_integral_v<_Tp>, bool = is_floating_point_v<_Tp>>
|
|
|
|
struct __atomic_ref;
|
|
|
|
|
|
|
|
// base class for non-integral, non-floating-point, non-pointer types
|
|
|
|
template<typename _Tp>
|
|
|
|
struct __atomic_ref<_Tp, false, false>
|
|
|
|
{
|
|
|
|
static_assert(is_trivially_copyable_v<_Tp>);
|
|
|
|
|
|
|
|
// 1/2/4/8/16-byte types must be aligned to at least their size.
|
|
|
|
static constexpr int _S_min_alignment
|
|
|
|
= (sizeof(_Tp) & (sizeof(_Tp) - 1)) || sizeof(_Tp) > 16
|
|
|
|
? 0 : sizeof(_Tp);
|
|
|
|
|
|
|
|
public:
|
|
|
|
using value_type = _Tp;
|
|
|
|
|
|
|
|
static constexpr bool is_always_lock_free
|
|
|
|
= __atomic_always_lock_free(sizeof(_Tp), 0);
|
|
|
|
|
|
|
|
static constexpr size_t required_alignment
|
|
|
|
= _S_min_alignment > alignof(_Tp) ? _S_min_alignment : alignof(_Tp);
|
|
|
|
|
|
|
|
__atomic_ref& operator=(const __atomic_ref&) = delete;
|
|
|
|
|
|
|
|
explicit
|
|
|
|
__atomic_ref(_Tp& __t) : _M_ptr(std::__addressof(__t))
|
|
|
|
{ __glibcxx_assert(((uintptr_t)_M_ptr % required_alignment) == 0); }
|
|
|
|
|
|
|
|
__atomic_ref(const __atomic_ref&) noexcept = default;
|
|
|
|
|
|
|
|
_Tp
|
|
|
|
operator=(_Tp __t) const noexcept
|
|
|
|
{
|
|
|
|
this->store(__t);
|
|
|
|
return __t;
|
|
|
|
}
|
|
|
|
|
|
|
|
operator _Tp() const noexcept { return this->load(); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const noexcept
|
|
|
|
{ return __atomic_impl::is_lock_free<sizeof(_Tp), required_alignment>(); }
|
|
|
|
|
|
|
|
void
|
|
|
|
store(_Tp __t, memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ __atomic_impl::store(_M_ptr, __t, __m); }
|
|
|
|
|
|
|
|
_Tp
|
|
|
|
load(memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::load(_M_ptr, __m); }
|
|
|
|
|
|
|
|
_Tp
|
|
|
|
exchange(_Tp __desired, memory_order __m = memory_order_seq_cst)
|
|
|
|
const noexcept
|
|
|
|
{ return __atomic_impl::exchange(_M_ptr, __desired, __m); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Tp& __expected, _Tp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_weak(_M_ptr,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Tp& __expected, _Tp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_strong(_M_ptr,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Tp& __expected, _Tp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
const noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Tp& __expected, _Tp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
const noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
|
|
|
_Tp* _M_ptr;
|
|
|
|
};
|
|
|
|
|
|
|
|
// base class for atomic_ref<integral-type>
|
|
|
|
template<typename _Tp>
|
|
|
|
struct __atomic_ref<_Tp, true, false>
|
|
|
|
{
|
|
|
|
static_assert(is_integral_v<_Tp>);
|
|
|
|
|
|
|
|
public:
|
|
|
|
using value_type = _Tp;
|
|
|
|
using difference_type = value_type;
|
|
|
|
|
|
|
|
static constexpr bool is_always_lock_free
|
|
|
|
= __atomic_always_lock_free(sizeof(_Tp), 0);
|
|
|
|
|
|
|
|
static constexpr size_t required_alignment
|
|
|
|
= sizeof(_Tp) > alignof(_Tp) ? sizeof(_Tp) : alignof(_Tp);
|
|
|
|
|
|
|
|
__atomic_ref() = delete;
|
|
|
|
__atomic_ref& operator=(const __atomic_ref&) = delete;
|
|
|
|
|
|
|
|
explicit
|
|
|
|
__atomic_ref(_Tp& __t) : _M_ptr(&__t)
|
|
|
|
{ __glibcxx_assert(((uintptr_t)_M_ptr % required_alignment) == 0); }
|
|
|
|
|
|
|
|
__atomic_ref(const __atomic_ref&) noexcept = default;
|
|
|
|
|
|
|
|
_Tp
|
|
|
|
operator=(_Tp __t) const noexcept
|
|
|
|
{
|
|
|
|
this->store(__t);
|
|
|
|
return __t;
|
|
|
|
}
|
|
|
|
|
|
|
|
operator _Tp() const noexcept { return this->load(); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::is_lock_free<sizeof(_Tp), required_alignment>();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
store(_Tp __t, memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ __atomic_impl::store(_M_ptr, __t, __m); }
|
|
|
|
|
|
|
|
_Tp
|
|
|
|
load(memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::load(_M_ptr, __m); }
|
|
|
|
|
|
|
|
_Tp
|
|
|
|
exchange(_Tp __desired,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::exchange(_M_ptr, __desired, __m); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Tp& __expected, _Tp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_weak(_M_ptr,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Tp& __expected, _Tp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_strong(_M_ptr,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Tp& __expected, _Tp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
const noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Tp& __expected, _Tp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
const noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_add(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::fetch_add(_M_ptr, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_sub(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::fetch_sub(_M_ptr, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_and(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::fetch_and(_M_ptr, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_or(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::fetch_or(_M_ptr, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_xor(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::fetch_xor(_M_ptr, __i, __m); }
|
|
|
|
|
|
|
|
_GLIBCXX_ALWAYS_INLINE value_type
|
|
|
|
operator++(int) const noexcept
|
|
|
|
{ return fetch_add(1); }
|
|
|
|
|
|
|
|
_GLIBCXX_ALWAYS_INLINE value_type
|
|
|
|
operator--(int) const noexcept
|
|
|
|
{ return fetch_sub(1); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator++() const noexcept
|
|
|
|
{ return __atomic_impl::__add_fetch(_M_ptr, value_type(1)); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator--() const noexcept
|
|
|
|
{ return __atomic_impl::__sub_fetch(_M_ptr, value_type(1)); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator+=(value_type __i) const noexcept
|
|
|
|
{ return __atomic_impl::__add_fetch(_M_ptr, __i); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator-=(value_type __i) const noexcept
|
|
|
|
{ return __atomic_impl::__sub_fetch(_M_ptr, __i); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator&=(value_type __i) const noexcept
|
|
|
|
{ return __atomic_impl::__and_fetch(_M_ptr, __i); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator|=(value_type __i) const noexcept
|
|
|
|
{ return __atomic_impl::__or_fetch(_M_ptr, __i); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator^=(value_type __i) const noexcept
|
|
|
|
{ return __atomic_impl::__xor_fetch(_M_ptr, __i); }
|
|
|
|
|
|
|
|
private:
|
|
|
|
_Tp* _M_ptr;
|
|
|
|
};
|
|
|
|
|
|
|
|
// base class for atomic_ref<floating-point-type>
|
|
|
|
template<typename _Fp>
|
|
|
|
struct __atomic_ref<_Fp, false, true>
|
|
|
|
{
|
|
|
|
static_assert(is_floating_point_v<_Fp>);
|
|
|
|
|
|
|
|
public:
|
|
|
|
using value_type = _Fp;
|
|
|
|
using difference_type = value_type;
|
|
|
|
|
|
|
|
static constexpr bool is_always_lock_free
|
|
|
|
= __atomic_always_lock_free(sizeof(_Fp), 0);
|
|
|
|
|
|
|
|
static constexpr size_t required_alignment = __alignof__(_Fp);
|
|
|
|
|
|
|
|
__atomic_ref() = delete;
|
|
|
|
__atomic_ref& operator=(const __atomic_ref&) = delete;
|
|
|
|
|
|
|
|
explicit
|
|
|
|
__atomic_ref(_Fp& __t) : _M_ptr(&__t)
|
|
|
|
{ __glibcxx_assert(((uintptr_t)_M_ptr % required_alignment) == 0); }
|
|
|
|
|
|
|
|
__atomic_ref(const __atomic_ref&) noexcept = default;
|
|
|
|
|
|
|
|
_Fp
|
|
|
|
operator=(_Fp __t) const noexcept
|
|
|
|
{
|
|
|
|
this->store(__t);
|
|
|
|
return __t;
|
|
|
|
}
|
|
|
|
|
|
|
|
operator _Fp() const noexcept { return this->load(); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::is_lock_free<sizeof(_Fp), required_alignment>();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
store(_Fp __t, memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ __atomic_impl::store(_M_ptr, __t, __m); }
|
|
|
|
|
|
|
|
_Fp
|
|
|
|
load(memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::load(_M_ptr, __m); }
|
|
|
|
|
|
|
|
_Fp
|
|
|
|
exchange(_Fp __desired,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::exchange(_M_ptr, __desired, __m); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_weak(_M_ptr,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_strong(_M_ptr,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
const noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Fp& __expected, _Fp __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
const noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_add(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::__fetch_add_flt(_M_ptr, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
fetch_sub(value_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::__fetch_sub_flt(_M_ptr, __i, __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator+=(value_type __i) const noexcept
|
|
|
|
{ return __atomic_impl::__add_fetch_flt(_M_ptr, __i); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator-=(value_type __i) const noexcept
|
|
|
|
{ return __atomic_impl::__sub_fetch_flt(_M_ptr, __i); }
|
|
|
|
|
|
|
|
private:
|
|
|
|
_Fp* _M_ptr;
|
|
|
|
};
|
|
|
|
|
|
|
|
// base class for atomic_ref<pointer-type>
|
|
|
|
template<typename _Tp>
|
|
|
|
struct __atomic_ref<_Tp*, false, false>
|
|
|
|
{
|
|
|
|
public:
|
|
|
|
using value_type = _Tp*;
|
|
|
|
using difference_type = ptrdiff_t;
|
|
|
|
|
|
|
|
static constexpr bool is_always_lock_free = ATOMIC_POINTER_LOCK_FREE == 2;
|
|
|
|
|
|
|
|
static constexpr size_t required_alignment = __alignof__(_Tp*);
|
|
|
|
|
|
|
|
__atomic_ref() = delete;
|
|
|
|
__atomic_ref& operator=(const __atomic_ref&) = delete;
|
|
|
|
|
|
|
|
explicit
|
|
|
|
__atomic_ref(_Tp*& __t) : _M_ptr(std::__addressof(__t))
|
|
|
|
{ __glibcxx_assert(((uintptr_t)_M_ptr % required_alignment) == 0); }
|
|
|
|
|
|
|
|
__atomic_ref(const __atomic_ref&) noexcept = default;
|
|
|
|
|
|
|
|
_Tp*
|
|
|
|
operator=(_Tp* __t) const noexcept
|
|
|
|
{
|
|
|
|
this->store(__t);
|
|
|
|
return __t;
|
|
|
|
}
|
|
|
|
|
|
|
|
operator _Tp*() const noexcept { return this->load(); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::is_lock_free<sizeof(_Tp*), required_alignment>();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
store(_Tp* __t, memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ __atomic_impl::store(_M_ptr, __t, __m); }
|
|
|
|
|
|
|
|
_Tp*
|
|
|
|
load(memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::load(_M_ptr, __m); }
|
|
|
|
|
|
|
|
_Tp*
|
|
|
|
exchange(_Tp* __desired,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::exchange(_M_ptr, __desired, __m); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Tp*& __expected, _Tp* __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_weak(_M_ptr,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Tp*& __expected, _Tp* __desired,
|
|
|
|
memory_order __success,
|
|
|
|
memory_order __failure) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::compare_exchange_strong(_M_ptr,
|
|
|
|
__expected, __desired,
|
|
|
|
__success, __failure);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_weak(_Tp*& __expected, _Tp* __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
const noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
compare_exchange_strong(_Tp*& __expected, _Tp* __desired,
|
|
|
|
memory_order __order = memory_order_seq_cst)
|
|
|
|
const noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__expected, __desired, __order,
|
|
|
|
__cmpexch_failure_order(__order));
|
|
|
|
}
|
|
|
|
|
|
|
|
_GLIBCXX_ALWAYS_INLINE value_type
|
|
|
|
fetch_add(difference_type __d,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::fetch_add(_M_ptr, _S_type_size(__d), __m); }
|
|
|
|
|
|
|
|
_GLIBCXX_ALWAYS_INLINE value_type
|
|
|
|
fetch_sub(difference_type __d,
|
|
|
|
memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{ return __atomic_impl::fetch_sub(_M_ptr, _S_type_size(__d), __m); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator++(int) const noexcept
|
|
|
|
{ return fetch_add(1); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator--(int) const noexcept
|
|
|
|
{ return fetch_sub(1); }
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator++() const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::__add_fetch(_M_ptr, _S_type_size(1));
|
|
|
|
}
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator--() const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::__sub_fetch(_M_ptr, _S_type_size(1));
|
|
|
|
}
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator+=(difference_type __d) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::__add_fetch(_M_ptr, _S_type_size(__d));
|
|
|
|
}
|
|
|
|
|
|
|
|
value_type
|
|
|
|
operator-=(difference_type __d) const noexcept
|
|
|
|
{
|
|
|
|
return __atomic_impl::__sub_fetch(_M_ptr, _S_type_size(__d));
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
|
|
|
static constexpr ptrdiff_t
|
|
|
|
_S_type_size(ptrdiff_t __d) noexcept
|
|
|
|
{
|
|
|
|
static_assert(is_object_v<_Tp>);
|
|
|
|
return __d * sizeof(_Tp);
|
|
|
|
}
|
|
|
|
|
|
|
|
_Tp** _M_ptr;
|
|
|
|
};
|
|
|
|
|
|
|
|
#endif // C++2a
|
|
|
|
|
2009-12-21 20:00:34 +01:00
|
|
|
// @} group atomics
|
|
|
|
|
PR libstdc++/36104 part four
2011-01-30 Benjamin Kosnik <bkoz@redhat.com>
PR libstdc++/36104 part four
* include/bits/c++config (_GLIBCXX_STD): Remove.
(_GLIBCXX_STD_D, _GLIBCXX_PR): Now _GLIBCXX_STD_C.
(_GLIBCXX_P): Now _GLIBCXX_STD_A.
(_GLIBCXX_NAMESPACE_DEBUG, _GLIBCXX_NAMESPACE_PARALLEL,
_GLIBCXX_NAMESPACE_PROFILE, _GLIBCXX_NAMESPACE_VERSION): Remove.
(_GLIBCXX_INLINE_DEBUG, _GLIBCXX_INLINE_PARALLEL,
_GLIBCXX_INLINE_PROFILE): Remove.
(_GLIBCXX_BEGIN_NAMESPACE(X)): Remove.
(_GLIBCXX_END_NAMESPACE): Remove.
(_GLIBCXX_BEGIN_NESTED_NAMESPACE(X, Y)): Remove.
(_GLIBCXX_END_NESTED_NAMESPACE): Remove.
(_GLIBCXX_BEGIN_NAMESPACE_ALGO): Add.
(_GLIBCXX_END_NAMESPACE_ALGO): Add.
(_GLIBCXX_BEGIN_NAMESPACE_CONTAINER): Add.
(_GLIBCXX_END_NAMESPACE_CONTAINER): Add.
(_GLIBCXX_BEGIN_NAMESPACE_VERSION): Add.
(_GLIBCXX_END_NAMESPACE_VERSION): Add.
(_GLIBCXX_BEGIN_LDBL_NAMESPACE): To _GLIBCXX_BEGIN_NAMESPACE_LDBL.
(_GLIBCXX_END_LDBL_NAMESPACE): To _GLIBCXX_END_NAMESPACE_LDBL.
(_GLIBCXX_VISIBILITY_ATTR): Revert to _GLIBCXX_VISIBILITY.
* include/*: Use new macros for namespace scope.
* config/*: Same.
* src/*: Same.
* src/Makefile.am (sources): Remove debug_list.cc, add
compatibility-debug_list-2.cc.
(parallel_sources): Remove parallel_list.cc, add
compatibility-parallel_list-2.cc.
(compatibility-parallel_list-2.[o,lo]): New rule.
* src/Makefile.in: Regenerate.
* src/debug_list.cc: Remove.
* src/parallel_list.cc: Remove.
* src/compatibility-list-2.cc: New.
* src/compatibility-debug_list-2.cc: New.
* src/compatibility-parallel_list-2.cc: New.
* doc/doxygen/user.cfg.in: Adjust macros.
* testsuite/20_util/auto_ptr/assign_neg.cc: Adjust line numbers, macros.
* testsuite/20_util/declval/requirements/1_neg.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg1.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg2.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg3.cc: Same.
* testsuite/20_util/forward/c_neg.cc: Same.
* testsuite/20_util/forward/f_neg.cc: Same.
* testsuite/20_util/make_signed/requirements/typedefs_neg.cc: Same.
* testsuite/20_util/make_unsigned/requirements/typedefs_neg.cc: Same.
* testsuite/20_util/ratio/cons/cons_overflow_neg.cc: Same.
* testsuite/20_util/ratio/operations/ops_overflow_neg.cc: Same.
* testsuite/20_util/shared_ptr/cons/43820_neg.cc: Same.
* testsuite/20_util/weak_ptr/comparison/cmp_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/insert_neg.cc: Same.
* testsuite/23_containers/forward_list/capacity/1.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
assign_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
insert_neg.cc: Same.
* testsuite/23_containers/list/capacity/29134.cc: Same.
* testsuite/23_containers/list/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/insert_neg.cc: Same.
* testsuite/23_containers/vector/bool/capacity/29134.cc: Same.
* testsuite/23_containers/vector/bool/modifiers/insert/31370.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/insert_neg.cc: Same.
* testsuite/25_algorithms/sort/35588.cc: Same.
* testsuite/27_io/ios_base/cons/assign_neg.cc: Same.
* testsuite/27_io/ios_base/cons/copy_neg.cc: Same.
* testsuite/ext/profile/mutex_extensions_neg.cc: Same.
* testsuite/ext/profile/profiler_algos.cc: Same.
* testsuite/ext/type_traits/add_unsigned_floating_neg.cc: Same.
* testsuite/ext/type_traits/add_unsigned_integer_neg.cc: Same.
* testsuite/ext/type_traits/remove_unsigned_floating_neg.cc: Same.
* testsuite/ext/type_traits/remove_unsigned_integer_neg.cc: Same.
* testsuite/tr1/2_general_utilities/shared_ptr/cons/43820_neg.cc: Same.
From-SVN: r169421
2011-01-30 23:39:36 +01:00
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_GLIBCXX_END_NAMESPACE_VERSION
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2011-02-16 20:01:51 +01:00
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} // namespace std
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2009-12-21 20:00:34 +01:00
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#endif
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