2010-11-02 03:35:28 +01:00
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// -*- C++ -*- header.
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2009-12-21 20:00:34 +01:00
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2017-01-01 13:07:43 +01:00
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// Copyright (C) 2008-2017 Free Software Foundation, Inc.
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2009-12-21 20:00:34 +01:00
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//
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// This file is part of the GNU ISO C++ Library. This library is free
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// software; you can redistribute it and/or modify it under the
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// terms of the GNU General Public License as published by the
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// Free Software Foundation; either version 3, or (at your option)
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// any later version.
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// Under Section 7 of GPL version 3, you are granted additional
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// permissions described in the GCC Runtime Library Exception, version
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// 3.1, as published by the Free Software Foundation.
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// You should have received a copy of the GNU General Public License and
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// a copy of the GCC Runtime Library Exception along with this program;
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// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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// <http://www.gnu.org/licenses/>.
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2011-02-16 20:01:51 +01:00
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/** @file bits/atomic_base.h
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2010-11-02 03:35:28 +01:00
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* This is an internal header file, included by other library headers.
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2010-12-19 10:21:16 +01:00
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* Do not attempt to use it directly. @headername{atomic}
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2009-12-21 20:00:34 +01:00
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*/
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#ifndef _GLIBCXX_ATOMIC_BASE_H
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#define _GLIBCXX_ATOMIC_BASE_H 1
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2010-11-02 03:35:28 +01:00
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#pragma GCC system_header
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#include <bits/c++config.h>
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#include <stdint.h>
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2011-12-01 03:20:32 +01:00
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#include <bits/atomic_lockfree_defines.h>
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2010-11-02 03:35:28 +01:00
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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#ifndef _GLIBCXX_ALWAYS_INLINE
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2015-01-29 13:47:20 +01:00
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#define _GLIBCXX_ALWAYS_INLINE inline __attribute__((__always_inline__))
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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#endif
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PR libstdc++/36104 part four
2011-01-30 Benjamin Kosnik <bkoz@redhat.com>
PR libstdc++/36104 part four
* include/bits/c++config (_GLIBCXX_STD): Remove.
(_GLIBCXX_STD_D, _GLIBCXX_PR): Now _GLIBCXX_STD_C.
(_GLIBCXX_P): Now _GLIBCXX_STD_A.
(_GLIBCXX_NAMESPACE_DEBUG, _GLIBCXX_NAMESPACE_PARALLEL,
_GLIBCXX_NAMESPACE_PROFILE, _GLIBCXX_NAMESPACE_VERSION): Remove.
(_GLIBCXX_INLINE_DEBUG, _GLIBCXX_INLINE_PARALLEL,
_GLIBCXX_INLINE_PROFILE): Remove.
(_GLIBCXX_BEGIN_NAMESPACE(X)): Remove.
(_GLIBCXX_END_NAMESPACE): Remove.
(_GLIBCXX_BEGIN_NESTED_NAMESPACE(X, Y)): Remove.
(_GLIBCXX_END_NESTED_NAMESPACE): Remove.
(_GLIBCXX_BEGIN_NAMESPACE_ALGO): Add.
(_GLIBCXX_END_NAMESPACE_ALGO): Add.
(_GLIBCXX_BEGIN_NAMESPACE_CONTAINER): Add.
(_GLIBCXX_END_NAMESPACE_CONTAINER): Add.
(_GLIBCXX_BEGIN_NAMESPACE_VERSION): Add.
(_GLIBCXX_END_NAMESPACE_VERSION): Add.
(_GLIBCXX_BEGIN_LDBL_NAMESPACE): To _GLIBCXX_BEGIN_NAMESPACE_LDBL.
(_GLIBCXX_END_LDBL_NAMESPACE): To _GLIBCXX_END_NAMESPACE_LDBL.
(_GLIBCXX_VISIBILITY_ATTR): Revert to _GLIBCXX_VISIBILITY.
* include/*: Use new macros for namespace scope.
* config/*: Same.
* src/*: Same.
* src/Makefile.am (sources): Remove debug_list.cc, add
compatibility-debug_list-2.cc.
(parallel_sources): Remove parallel_list.cc, add
compatibility-parallel_list-2.cc.
(compatibility-parallel_list-2.[o,lo]): New rule.
* src/Makefile.in: Regenerate.
* src/debug_list.cc: Remove.
* src/parallel_list.cc: Remove.
* src/compatibility-list-2.cc: New.
* src/compatibility-debug_list-2.cc: New.
* src/compatibility-parallel_list-2.cc: New.
* doc/doxygen/user.cfg.in: Adjust macros.
* testsuite/20_util/auto_ptr/assign_neg.cc: Adjust line numbers, macros.
* testsuite/20_util/declval/requirements/1_neg.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg1.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg2.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg3.cc: Same.
* testsuite/20_util/forward/c_neg.cc: Same.
* testsuite/20_util/forward/f_neg.cc: Same.
* testsuite/20_util/make_signed/requirements/typedefs_neg.cc: Same.
* testsuite/20_util/make_unsigned/requirements/typedefs_neg.cc: Same.
* testsuite/20_util/ratio/cons/cons_overflow_neg.cc: Same.
* testsuite/20_util/ratio/operations/ops_overflow_neg.cc: Same.
* testsuite/20_util/shared_ptr/cons/43820_neg.cc: Same.
* testsuite/20_util/weak_ptr/comparison/cmp_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/insert_neg.cc: Same.
* testsuite/23_containers/forward_list/capacity/1.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
assign_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
insert_neg.cc: Same.
* testsuite/23_containers/list/capacity/29134.cc: Same.
* testsuite/23_containers/list/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/insert_neg.cc: Same.
* testsuite/23_containers/vector/bool/capacity/29134.cc: Same.
* testsuite/23_containers/vector/bool/modifiers/insert/31370.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/insert_neg.cc: Same.
* testsuite/25_algorithms/sort/35588.cc: Same.
* testsuite/27_io/ios_base/cons/assign_neg.cc: Same.
* testsuite/27_io/ios_base/cons/copy_neg.cc: Same.
* testsuite/ext/profile/mutex_extensions_neg.cc: Same.
* testsuite/ext/profile/profiler_algos.cc: Same.
* testsuite/ext/type_traits/add_unsigned_floating_neg.cc: Same.
* testsuite/ext/type_traits/add_unsigned_integer_neg.cc: Same.
* testsuite/ext/type_traits/remove_unsigned_floating_neg.cc: Same.
* testsuite/ext/type_traits/remove_unsigned_integer_neg.cc: Same.
* testsuite/tr1/2_general_utilities/shared_ptr/cons/43820_neg.cc: Same.
From-SVN: r169421
2011-01-30 23:39:36 +01:00
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namespace std _GLIBCXX_VISIBILITY(default)
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{
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_GLIBCXX_BEGIN_NAMESPACE_VERSION
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2009-12-21 20:00:34 +01:00
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/**
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* @defgroup atomics Atomics
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*
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* Components for performing atomic operations.
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* @{
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*/
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/// Enumeration for memory_order
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typedef enum memory_order
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{
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memory_order_relaxed,
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memory_order_consume,
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memory_order_acquire,
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memory_order_release,
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memory_order_acq_rel,
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memory_order_seq_cst
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} memory_order;
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libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
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enum __memory_order_modifier
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{
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__memory_order_mask = 0x0ffff,
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__memory_order_modifier_mask = 0xffff0000,
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__memory_order_hle_acquire = 0x10000,
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__memory_order_hle_release = 0x20000
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};
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constexpr memory_order
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operator|(memory_order __m, __memory_order_modifier __mod)
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{
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return memory_order(__m | int(__mod));
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}
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constexpr memory_order
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operator&(memory_order __m, __memory_order_modifier __mod)
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{
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return memory_order(__m & int(__mod));
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}
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2011-12-08 10:44:57 +01:00
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// Drop release ordering as per [atomics.types.operations.req]/21
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constexpr memory_order
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libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
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__cmpexch_failure_order2(memory_order __m) noexcept
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2010-11-02 03:35:28 +01:00
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{
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2011-12-08 10:44:57 +01:00
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return __m == memory_order_acq_rel ? memory_order_acquire
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: __m == memory_order_release ? memory_order_relaxed : __m;
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2010-11-02 03:35:28 +01:00
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}
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libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
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constexpr memory_order
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__cmpexch_failure_order(memory_order __m) noexcept
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{
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return memory_order(__cmpexch_failure_order2(__m & __memory_order_mask)
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| (__m & __memory_order_modifier_mask));
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}
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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_GLIBCXX_ALWAYS_INLINE void
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2011-11-10 21:38:33 +01:00
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atomic_thread_fence(memory_order __m) noexcept
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2011-12-01 03:20:32 +01:00
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{ __atomic_thread_fence(__m); }
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2011-02-16 20:01:51 +01:00
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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_GLIBCXX_ALWAYS_INLINE void
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2011-11-10 21:38:33 +01:00
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atomic_signal_fence(memory_order __m) noexcept
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2012-10-09 20:40:02 +02:00
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{ __atomic_signal_fence(__m); }
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2011-02-16 20:01:51 +01:00
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2010-11-02 03:35:28 +01:00
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/// kill_dependency
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template<typename _Tp>
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inline _Tp
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2011-08-04 21:57:48 +02:00
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kill_dependency(_Tp __y) noexcept
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2010-11-02 03:35:28 +01:00
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{
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2011-01-28 17:59:49 +01:00
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_Tp __ret(__y);
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return __ret;
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2010-11-02 03:35:28 +01:00
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}
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// Base types for atomics.
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2011-11-06 15:55:48 +01:00
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template<typename _IntTp>
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struct __atomic_base;
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2010-11-02 03:35:28 +01:00
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#define ATOMIC_VAR_INIT(_VI) { _VI }
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template<typename _Tp>
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struct atomic;
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2009-12-21 20:00:34 +01:00
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2011-02-16 20:01:51 +01:00
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template<typename _Tp>
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struct atomic<_Tp*>;
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2013-02-27 00:46:21 +01:00
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/* The target's "set" value for test-and-set may not be exactly 1. */
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#if __GCC_ATOMIC_TEST_AND_SET_TRUEVAL == 1
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typedef bool __atomic_flag_data_type;
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#else
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typedef unsigned char __atomic_flag_data_type;
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#endif
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2011-11-06 15:55:48 +01:00
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/**
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* @brief Base type for atomic_flag.
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*
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* Base type is POD with data, allowing atomic_flag to derive from
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* it and meet the standard layout type requirement. In addition to
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2013-11-15 17:33:59 +01:00
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* compatibility with a C interface, this allows different
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2011-11-06 15:55:48 +01:00
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* implementations of atomic_flag to use the same atomic operation
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* functions, via a standard conversion to the __atomic_flag_base
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* argument.
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*/
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_GLIBCXX_BEGIN_EXTERN_C
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struct __atomic_flag_base
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{
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2013-02-27 00:46:21 +01:00
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__atomic_flag_data_type _M_i;
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2011-11-06 15:55:48 +01:00
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};
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_GLIBCXX_END_EXTERN_C
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2012-01-26 22:50:52 +01:00
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#define ATOMIC_FLAG_INIT { 0 }
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2011-11-06 15:55:48 +01:00
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/// atomic_flag
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struct atomic_flag : public __atomic_flag_base
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{
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atomic_flag() noexcept = default;
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|
~atomic_flag() noexcept = default;
|
|
|
|
atomic_flag(const atomic_flag&) = delete;
|
|
|
|
atomic_flag& operator=(const atomic_flag&) = delete;
|
|
|
|
atomic_flag& operator=(const atomic_flag&) volatile = delete;
|
|
|
|
|
|
|
|
// Conversion to ATOMIC_FLAG_INIT.
|
2012-01-26 22:50:52 +01:00
|
|
|
constexpr atomic_flag(bool __i) noexcept
|
2013-02-27 00:46:21 +01:00
|
|
|
: __atomic_flag_base{ _S_init(__i) }
|
2012-01-26 22:50:52 +01:00
|
|
|
{ }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
test_and_set(memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
2011-11-10 21:38:33 +01:00
|
|
|
return __atomic_test_and_set (&_M_i, __m);
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
test_and_set(memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
2011-11-10 21:38:33 +01:00
|
|
|
return __atomic_test_and_set (&_M_i, __m);
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
clear(memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2011-11-10 21:38:33 +01:00
|
|
|
__atomic_clear (&_M_i, __m);
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
clear(memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
2011-11-10 21:38:33 +01:00
|
|
|
__atomic_clear (&_M_i, __m);
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
2013-02-27 00:46:21 +01:00
|
|
|
|
|
|
|
private:
|
|
|
|
static constexpr __atomic_flag_data_type
|
|
|
|
_S_init(bool __i)
|
|
|
|
{ return __i ? __GCC_ATOMIC_TEST_AND_SET_TRUEVAL : 0; }
|
2011-11-06 15:55:48 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/// Base class for atomic integrals.
|
|
|
|
//
|
|
|
|
// For each of the integral types, define atomic_[integral type] struct
|
|
|
|
//
|
|
|
|
// atomic_bool bool
|
|
|
|
// atomic_char char
|
|
|
|
// atomic_schar signed char
|
|
|
|
// atomic_uchar unsigned char
|
|
|
|
// atomic_short short
|
|
|
|
// atomic_ushort unsigned short
|
|
|
|
// atomic_int int
|
|
|
|
// atomic_uint unsigned int
|
|
|
|
// atomic_long long
|
|
|
|
// atomic_ulong unsigned long
|
|
|
|
// atomic_llong long long
|
|
|
|
// atomic_ullong unsigned long long
|
|
|
|
// atomic_char16_t char16_t
|
|
|
|
// atomic_char32_t char32_t
|
|
|
|
// atomic_wchar_t wchar_t
|
|
|
|
//
|
|
|
|
// NB: Assuming _ITp is an integral scalar type that is 1, 2, 4, or
|
|
|
|
// 8 bytes, since that is what GCC built-in functions for atomic
|
|
|
|
// memory access expect.
|
|
|
|
template<typename _ITp>
|
|
|
|
struct __atomic_base
|
|
|
|
{
|
|
|
|
private:
|
|
|
|
typedef _ITp __int_type;
|
|
|
|
|
2015-04-09 13:15:44 +02:00
|
|
|
static constexpr int _S_alignment =
|
|
|
|
sizeof(_ITp) > alignof(_ITp) ? sizeof(_ITp) : alignof(_ITp);
|
|
|
|
|
|
|
|
alignas(_S_alignment) __int_type _M_i;
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
public:
|
|
|
|
__atomic_base() noexcept = default;
|
|
|
|
~__atomic_base() noexcept = default;
|
|
|
|
__atomic_base(const __atomic_base&) = delete;
|
|
|
|
__atomic_base& operator=(const __atomic_base&) = delete;
|
|
|
|
__atomic_base& operator=(const __atomic_base&) volatile = delete;
|
|
|
|
|
|
|
|
// Requires __int_type convertible to _M_i.
|
|
|
|
constexpr __atomic_base(__int_type __i) noexcept : _M_i (__i) { }
|
|
|
|
|
|
|
|
operator __int_type() const noexcept
|
|
|
|
{ return load(); }
|
|
|
|
|
|
|
|
operator __int_type() const volatile noexcept
|
|
|
|
{ return load(); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator=(__int_type __i) noexcept
|
|
|
|
{
|
|
|
|
store(__i);
|
|
|
|
return __i;
|
|
|
|
}
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator=(__int_type __i) volatile noexcept
|
|
|
|
{
|
|
|
|
store(__i);
|
|
|
|
return __i;
|
|
|
|
}
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator++(int) noexcept
|
|
|
|
{ return fetch_add(1); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator++(int) volatile noexcept
|
|
|
|
{ return fetch_add(1); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator--(int) noexcept
|
|
|
|
{ return fetch_sub(1); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator--(int) volatile noexcept
|
|
|
|
{ return fetch_sub(1); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator++() noexcept
|
|
|
|
{ return __atomic_add_fetch(&_M_i, 1, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator++() volatile noexcept
|
|
|
|
{ return __atomic_add_fetch(&_M_i, 1, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator--() noexcept
|
|
|
|
{ return __atomic_sub_fetch(&_M_i, 1, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator--() volatile noexcept
|
|
|
|
{ return __atomic_sub_fetch(&_M_i, 1, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator+=(__int_type __i) noexcept
|
|
|
|
{ return __atomic_add_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator+=(__int_type __i) volatile noexcept
|
|
|
|
{ return __atomic_add_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator-=(__int_type __i) noexcept
|
|
|
|
{ return __atomic_sub_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator-=(__int_type __i) volatile noexcept
|
|
|
|
{ return __atomic_sub_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator&=(__int_type __i) noexcept
|
|
|
|
{ return __atomic_and_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator&=(__int_type __i) volatile noexcept
|
|
|
|
{ return __atomic_and_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator|=(__int_type __i) noexcept
|
|
|
|
{ return __atomic_or_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator|=(__int_type __i) volatile noexcept
|
|
|
|
{ return __atomic_or_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator^=(__int_type __i) noexcept
|
|
|
|
{ return __atomic_xor_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
__int_type
|
|
|
|
operator^=(__int_type __i) volatile noexcept
|
|
|
|
{ return __atomic_xor_fetch(&_M_i, __i, memory_order_seq_cst); }
|
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const noexcept
|
2015-03-26 19:31:11 +01:00
|
|
|
{
|
2015-09-17 17:46:04 +02:00
|
|
|
// Use a fake, minimally aligned pointer.
|
|
|
|
return __atomic_is_lock_free(sizeof(_M_i),
|
|
|
|
reinterpret_cast<void *>(-__alignof(_M_i)));
|
2015-03-26 19:31:11 +01:00
|
|
|
}
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const volatile noexcept
|
2015-03-26 19:31:11 +01:00
|
|
|
{
|
2015-09-17 17:46:04 +02:00
|
|
|
// Use a fake, minimally aligned pointer.
|
|
|
|
return __atomic_is_lock_free(sizeof(_M_i),
|
|
|
|
reinterpret_cast<void *>(-__alignof(_M_i)));
|
2015-03-26 19:31:11 +01:00
|
|
|
}
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
store(__int_type __i, memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__atomic_store_n(&_M_i, __i, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
store(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__atomic_store_n(&_M_i, __i, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
load(memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_release);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_load_n(&_M_i, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
load(memory_order __m = memory_order_seq_cst) const volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_release);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_load_n(&_M_i, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
exchange(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
|
|
|
return __atomic_exchange_n(&_M_i, __i, __m);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
exchange(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
|
|
|
return __atomic_exchange_n(&_M_i, __i, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_weak(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m1, memory_order __m2) noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_compare_exchange_n(&_M_i, &__i1, __i2, 1, __m1, __m2);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_weak(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m1,
|
|
|
|
memory_order __m2) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_compare_exchange_n(&_M_i, &__i1, __i2, 1, __m1, __m2);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_weak(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__i1, __i2, __m,
|
2011-12-08 10:44:57 +01:00
|
|
|
__cmpexch_failure_order(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_weak(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_weak(__i1, __i2, __m,
|
2011-12-08 10:44:57 +01:00
|
|
|
__cmpexch_failure_order(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m1, memory_order __m2) noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_compare_exchange_n(&_M_i, &__i1, __i2, 0, __m1, __m2);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m1,
|
|
|
|
memory_order __m2) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
|
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_compare_exchange_n(&_M_i, &__i1, __i2, 0, __m1, __m2);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__i1, __i2, __m,
|
2011-12-08 10:44:57 +01:00
|
|
|
__cmpexch_failure_order(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__int_type& __i1, __int_type __i2,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
|
|
|
return compare_exchange_strong(__i1, __i2, __m,
|
2011-12-08 10:44:57 +01:00
|
|
|
__cmpexch_failure_order(__m));
|
2011-11-06 15:55:48 +01:00
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_add(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{ return __atomic_fetch_add(&_M_i, __i, __m); }
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_add(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{ return __atomic_fetch_add(&_M_i, __i, __m); }
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_sub(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{ return __atomic_fetch_sub(&_M_i, __i, __m); }
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_sub(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{ return __atomic_fetch_sub(&_M_i, __i, __m); }
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_and(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{ return __atomic_fetch_and(&_M_i, __i, __m); }
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_and(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{ return __atomic_fetch_and(&_M_i, __i, __m); }
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_or(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{ return __atomic_fetch_or(&_M_i, __i, __m); }
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_or(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{ return __atomic_fetch_or(&_M_i, __i, __m); }
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_xor(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{ return __atomic_fetch_xor(&_M_i, __i, __m); }
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __int_type
|
2011-11-06 15:55:48 +01:00
|
|
|
fetch_xor(__int_type __i,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{ return __atomic_fetch_xor(&_M_i, __i, __m); }
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/// Partial specialization for pointer types.
|
|
|
|
template<typename _PTp>
|
|
|
|
struct __atomic_base<_PTp*>
|
|
|
|
{
|
|
|
|
private:
|
|
|
|
typedef _PTp* __pointer_type;
|
|
|
|
|
|
|
|
__pointer_type _M_p;
|
|
|
|
|
2012-02-03 20:49:11 +01:00
|
|
|
// Factored out to facilitate explicit specialization.
|
|
|
|
constexpr ptrdiff_t
|
2014-04-15 20:28:41 +02:00
|
|
|
_M_type_size(ptrdiff_t __d) const { return __d * sizeof(_PTp); }
|
2012-02-03 20:49:11 +01:00
|
|
|
|
|
|
|
constexpr ptrdiff_t
|
2014-04-15 20:28:41 +02:00
|
|
|
_M_type_size(ptrdiff_t __d) const volatile { return __d * sizeof(_PTp); }
|
2012-02-03 20:49:11 +01:00
|
|
|
|
2011-11-06 15:55:48 +01:00
|
|
|
public:
|
|
|
|
__atomic_base() noexcept = default;
|
|
|
|
~__atomic_base() noexcept = default;
|
|
|
|
__atomic_base(const __atomic_base&) = delete;
|
|
|
|
__atomic_base& operator=(const __atomic_base&) = delete;
|
|
|
|
__atomic_base& operator=(const __atomic_base&) volatile = delete;
|
|
|
|
|
|
|
|
// Requires __pointer_type convertible to _M_p.
|
|
|
|
constexpr __atomic_base(__pointer_type __p) noexcept : _M_p (__p) { }
|
|
|
|
|
|
|
|
operator __pointer_type() const noexcept
|
|
|
|
{ return load(); }
|
|
|
|
|
|
|
|
operator __pointer_type() const volatile noexcept
|
|
|
|
{ return load(); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator=(__pointer_type __p) noexcept
|
|
|
|
{
|
|
|
|
store(__p);
|
|
|
|
return __p;
|
|
|
|
}
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator=(__pointer_type __p) volatile noexcept
|
|
|
|
{
|
|
|
|
store(__p);
|
|
|
|
return __p;
|
|
|
|
}
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator++(int) noexcept
|
|
|
|
{ return fetch_add(1); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator++(int) volatile noexcept
|
|
|
|
{ return fetch_add(1); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator--(int) noexcept
|
|
|
|
{ return fetch_sub(1); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator--(int) volatile noexcept
|
|
|
|
{ return fetch_sub(1); }
|
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator++() noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_p, _M_type_size(1),
|
|
|
|
memory_order_seq_cst); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator++() volatile noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_p, _M_type_size(1),
|
|
|
|
memory_order_seq_cst); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator--() noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_p, _M_type_size(1),
|
|
|
|
memory_order_seq_cst); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator--() volatile noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_p, _M_type_size(1),
|
|
|
|
memory_order_seq_cst); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator+=(ptrdiff_t __d) noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_p, _M_type_size(__d),
|
|
|
|
memory_order_seq_cst); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator+=(ptrdiff_t __d) volatile noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_add_fetch(&_M_p, _M_type_size(__d),
|
|
|
|
memory_order_seq_cst); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator-=(ptrdiff_t __d) noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_p, _M_type_size(__d),
|
|
|
|
memory_order_seq_cst); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__pointer_type
|
|
|
|
operator-=(ptrdiff_t __d) volatile noexcept
|
2012-02-03 20:49:11 +01:00
|
|
|
{ return __atomic_sub_fetch(&_M_p, _M_type_size(__d),
|
|
|
|
memory_order_seq_cst); }
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const noexcept
|
2015-03-26 19:31:11 +01:00
|
|
|
{
|
|
|
|
// Produce a fake, minimally aligned pointer.
|
2015-09-17 17:46:04 +02:00
|
|
|
return __atomic_is_lock_free(sizeof(_M_p),
|
|
|
|
reinterpret_cast<void *>(-__alignof(_M_p)));
|
2015-03-26 19:31:11 +01:00
|
|
|
}
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
bool
|
|
|
|
is_lock_free() const volatile noexcept
|
2015-03-26 19:31:11 +01:00
|
|
|
{
|
|
|
|
// Produce a fake, minimally aligned pointer.
|
2015-09-17 17:46:04 +02:00
|
|
|
return __atomic_is_lock_free(sizeof(_M_p),
|
|
|
|
reinterpret_cast<void *>(-__alignof(_M_p)));
|
2015-03-26 19:31:11 +01:00
|
|
|
}
|
2011-11-06 15:55:48 +01:00
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
store(__pointer_type __p,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
|
|
|
|
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__atomic_store_n(&_M_p, __p, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE void
|
2011-11-06 15:55:48 +01:00
|
|
|
store(__pointer_type __p,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_acquire);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b != memory_order_consume);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
__atomic_store_n(&_M_p, __p, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
load(memory_order __m = memory_order_seq_cst) const noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_release);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_load_n(&_M_p, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
load(memory_order __m = memory_order_seq_cst) const volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b = __m & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b != memory_order_release);
|
|
|
|
__glibcxx_assert(__b != memory_order_acq_rel);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_load_n(&_M_p, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
exchange(__pointer_type __p,
|
|
|
|
memory_order __m = memory_order_seq_cst) noexcept
|
|
|
|
{
|
|
|
|
return __atomic_exchange_n(&_M_p, __p, __m);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE __pointer_type
|
2011-11-06 15:55:48 +01:00
|
|
|
exchange(__pointer_type __p,
|
|
|
|
memory_order __m = memory_order_seq_cst) volatile noexcept
|
|
|
|
{
|
|
|
|
return __atomic_exchange_n(&_M_p, __p, __m);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__pointer_type& __p1, __pointer_type __p2,
|
|
|
|
memory_order __m1,
|
|
|
|
memory_order __m2) noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_compare_exchange_n(&_M_p, &__p1, __p2, 0, __m1, __m2);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
|
|
_GLIBCXX_ALWAYS_INLINE bool
|
2011-11-06 15:55:48 +01:00
|
|
|
compare_exchange_strong(__pointer_type& __p1, __pointer_type __p2,
|
|
|
|
memory_order __m1,
|
|
|
|
memory_order __m2) volatile noexcept
|
|
|
|
{
|
2017-02-11 22:08:06 +01:00
|
|
|
memory_order __b2 = __m2 & __memory_order_mask;
|
|
|
|
memory_order __b1 = __m1 & __memory_order_mask;
|
libstdc++: Add mem_order_hle_acquire/release to atomic.h v2
The underlying compiler supports additional __ATOMIC_HLE_ACQUIRE/RELEASE
memmodel flags for TSX, but this was not exposed to the C++ wrapper.
Handle it there.
These are additional flags, so some of assert checks need to mask
off the flags before checking the memory model type.
libstdc++-v3/:
2013-01-12 Andi Kleen <ak@linux.intel.com>
Jonathan Wakely <jwakely.gcc@gmail.com>
PR libstdc++/55223
* include/bits/atomic_base.h (__memory_order_modifier): Add
__memory_order_mask, __memory_order_modifier_mask,
__memory_order_hle_acquire, __memory_order_hle_release.
(operator|,operator&): Add.
(__cmpexch_failure_order): Rename to __cmpexch_failure_order2.
(__cmpexch_failure_order): Add.
(clear, store, load, compare_exchange_weak, compare_exchange_strong):
Handle flags.
* testsuite/29_atomics/atomic_flag/test_and_set/explicit-hle.cc:
Add.
Co-Authored-By: Jonathan Wakely <jwakely.gcc@gmail.com>
From-SVN: r195321
2013-01-20 20:03:22 +01:00
|
|
|
|
|
|
|
__glibcxx_assert(__b2 != memory_order_release);
|
|
|
|
__glibcxx_assert(__b2 != memory_order_acq_rel);
|
|
|
|
__glibcxx_assert(__b2 <= __b1);
|
2011-11-06 15:55:48 +01:00
|
|
|
|
|
|
|
return __atomic_compare_exchange_n(&_M_p, &__p1, __p2, 0, __m1, __m2);
|
|
|
|
}
|
|
|
|
|
Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
|
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_GLIBCXX_ALWAYS_INLINE __pointer_type
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2011-11-06 15:55:48 +01:00
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fetch_add(ptrdiff_t __d,
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memory_order __m = memory_order_seq_cst) noexcept
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2012-02-03 20:49:11 +01:00
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{ return __atomic_fetch_add(&_M_p, _M_type_size(__d), __m); }
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2011-11-06 15:55:48 +01:00
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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_GLIBCXX_ALWAYS_INLINE __pointer_type
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2011-11-06 15:55:48 +01:00
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fetch_add(ptrdiff_t __d,
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memory_order __m = memory_order_seq_cst) volatile noexcept
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2012-02-03 20:49:11 +01:00
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{ return __atomic_fetch_add(&_M_p, _M_type_size(__d), __m); }
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2011-11-06 15:55:48 +01:00
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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_GLIBCXX_ALWAYS_INLINE __pointer_type
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2011-11-06 15:55:48 +01:00
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fetch_sub(ptrdiff_t __d,
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memory_order __m = memory_order_seq_cst) noexcept
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2012-02-03 20:49:11 +01:00
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{ return __atomic_fetch_sub(&_M_p, _M_type_size(__d), __m); }
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2011-11-06 15:55:48 +01:00
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Mark all member functions with memory models always inline v2
When a non constant memory model is passed to __atomic_*
gcc falls back to seq_cst. This drops any HLE acquire or release bits.
This can happen when <atomic> is used with -O0
as the member functions are not always inlined then and the memory
argument passed in ends up being non-constant.
v2: Use _GLIBCXX_ALWAYS_INLINE
libstdc++-v3/:
2013-05-08 Andi Kleen <ak@linux.intel.com>
PR target/55947
* libstdc++-v3/include/bits/atomic_base.h
(_GLIBCXX_ALWAYS_INLINE): Add new macro.
(atomic_thread_fence, atomic_signal_fence, test_and_set,
clear, store, load, exchange, compare_exchange_weak)
compare_exchange_strong, fetch_add, fetch_sub, fetch_and,
fetch_or, fetch_xor): Mark _GLIBCXX_ALWAYS_INLINE.
From-SVN: r198733
2013-05-09 06:22:11 +02:00
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_GLIBCXX_ALWAYS_INLINE __pointer_type
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2011-11-06 15:55:48 +01:00
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fetch_sub(ptrdiff_t __d,
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memory_order __m = memory_order_seq_cst) volatile noexcept
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2012-02-03 20:49:11 +01:00
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{ return __atomic_fetch_sub(&_M_p, _M_type_size(__d), __m); }
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2011-11-06 15:55:48 +01:00
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};
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2009-12-21 20:00:34 +01:00
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// @} group atomics
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PR libstdc++/36104 part four
2011-01-30 Benjamin Kosnik <bkoz@redhat.com>
PR libstdc++/36104 part four
* include/bits/c++config (_GLIBCXX_STD): Remove.
(_GLIBCXX_STD_D, _GLIBCXX_PR): Now _GLIBCXX_STD_C.
(_GLIBCXX_P): Now _GLIBCXX_STD_A.
(_GLIBCXX_NAMESPACE_DEBUG, _GLIBCXX_NAMESPACE_PARALLEL,
_GLIBCXX_NAMESPACE_PROFILE, _GLIBCXX_NAMESPACE_VERSION): Remove.
(_GLIBCXX_INLINE_DEBUG, _GLIBCXX_INLINE_PARALLEL,
_GLIBCXX_INLINE_PROFILE): Remove.
(_GLIBCXX_BEGIN_NAMESPACE(X)): Remove.
(_GLIBCXX_END_NAMESPACE): Remove.
(_GLIBCXX_BEGIN_NESTED_NAMESPACE(X, Y)): Remove.
(_GLIBCXX_END_NESTED_NAMESPACE): Remove.
(_GLIBCXX_BEGIN_NAMESPACE_ALGO): Add.
(_GLIBCXX_END_NAMESPACE_ALGO): Add.
(_GLIBCXX_BEGIN_NAMESPACE_CONTAINER): Add.
(_GLIBCXX_END_NAMESPACE_CONTAINER): Add.
(_GLIBCXX_BEGIN_NAMESPACE_VERSION): Add.
(_GLIBCXX_END_NAMESPACE_VERSION): Add.
(_GLIBCXX_BEGIN_LDBL_NAMESPACE): To _GLIBCXX_BEGIN_NAMESPACE_LDBL.
(_GLIBCXX_END_LDBL_NAMESPACE): To _GLIBCXX_END_NAMESPACE_LDBL.
(_GLIBCXX_VISIBILITY_ATTR): Revert to _GLIBCXX_VISIBILITY.
* include/*: Use new macros for namespace scope.
* config/*: Same.
* src/*: Same.
* src/Makefile.am (sources): Remove debug_list.cc, add
compatibility-debug_list-2.cc.
(parallel_sources): Remove parallel_list.cc, add
compatibility-parallel_list-2.cc.
(compatibility-parallel_list-2.[o,lo]): New rule.
* src/Makefile.in: Regenerate.
* src/debug_list.cc: Remove.
* src/parallel_list.cc: Remove.
* src/compatibility-list-2.cc: New.
* src/compatibility-debug_list-2.cc: New.
* src/compatibility-parallel_list-2.cc: New.
* doc/doxygen/user.cfg.in: Adjust macros.
* testsuite/20_util/auto_ptr/assign_neg.cc: Adjust line numbers, macros.
* testsuite/20_util/declval/requirements/1_neg.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg1.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg2.cc: Same.
* testsuite/20_util/duration/requirements/typedefs_neg3.cc: Same.
* testsuite/20_util/forward/c_neg.cc: Same.
* testsuite/20_util/forward/f_neg.cc: Same.
* testsuite/20_util/make_signed/requirements/typedefs_neg.cc: Same.
* testsuite/20_util/make_unsigned/requirements/typedefs_neg.cc: Same.
* testsuite/20_util/ratio/cons/cons_overflow_neg.cc: Same.
* testsuite/20_util/ratio/operations/ops_overflow_neg.cc: Same.
* testsuite/20_util/shared_ptr/cons/43820_neg.cc: Same.
* testsuite/20_util/weak_ptr/comparison/cmp_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/deque/requirements/dr438/insert_neg.cc: Same.
* testsuite/23_containers/forward_list/capacity/1.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
assign_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/forward_list/requirements/dr438/
insert_neg.cc: Same.
* testsuite/23_containers/list/capacity/29134.cc: Same.
* testsuite/23_containers/list/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/list/requirements/dr438/insert_neg.cc: Same.
* testsuite/23_containers/vector/bool/capacity/29134.cc: Same.
* testsuite/23_containers/vector/bool/modifiers/insert/31370.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/assign_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/
constructor_1_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/
constructor_2_neg.cc: Same.
* testsuite/23_containers/vector/requirements/dr438/insert_neg.cc: Same.
* testsuite/25_algorithms/sort/35588.cc: Same.
* testsuite/27_io/ios_base/cons/assign_neg.cc: Same.
* testsuite/27_io/ios_base/cons/copy_neg.cc: Same.
* testsuite/ext/profile/mutex_extensions_neg.cc: Same.
* testsuite/ext/profile/profiler_algos.cc: Same.
* testsuite/ext/type_traits/add_unsigned_floating_neg.cc: Same.
* testsuite/ext/type_traits/add_unsigned_integer_neg.cc: Same.
* testsuite/ext/type_traits/remove_unsigned_floating_neg.cc: Same.
* testsuite/ext/type_traits/remove_unsigned_integer_neg.cc: Same.
* testsuite/tr1/2_general_utilities/shared_ptr/cons/43820_neg.cc: Same.
From-SVN: r169421
2011-01-30 23:39:36 +01:00
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_GLIBCXX_END_NAMESPACE_VERSION
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2011-02-16 20:01:51 +01:00
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} // namespace std
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2009-12-21 20:00:34 +01:00
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#endif
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