gcc/libgcc/config/lm32/_ashlsi3.S

114 lines
2.9 KiB
ArmAsm
Raw Normal View History

config.gcc: Add lm32 elf and uclinux targets. gcc/ 2009-11-11 Jon Beniston <jon@beniston.com> * config.gcc: Add lm32 elf and uclinux targets. * config/lm32: New directory. * config/lm32/lm32.c: New file. * config/lm32/lm32.h: New file. * config/lm32/lm32.md: New file. * config/lm32/lm32.opt: New file. * config/lm32/lm32-protos.h: New file. * config/lm32/constraints.md: New file. * config/lm32/predicates.md: New file. * config/lm32/sfp-machine.h: New file. * config/lm32/t-fprules-softfp: New file. * config/lm32/uclinux-elf.h: New file. * doc/invoke.texi: Document lm32 options. * doc/contrib.texi: Document lm32 porter. * doc/install.texi: Document lm32 targets. gcc/testsuite/ 2009-11-11 Jon Beniston <jon@beniston.com> * lib/target-supports.exp (check_profiling_available): lm32 target doesn't support profiling. * gcc.dg/20020312-2.c: Add lm32 support. * g++.dg/other/packed1.C: Expect to fail on lm32. * g++.old-deja/g++.jason/thunk3.C: Likewise. libgcc/ 2009-11-11 Jon Beniston <jon@beniston.com> * config.host: Add lm32 targets. * config/lm32: New directory. * config/lm32/libgcc_lm32.h: New file. * config/lm32/_mulsi3.c: New file. * config/lm32/_udivmodsi4.c: New file. * config/lm32/_divsi3.c: New file. * config/lm32/_modsi3.c: New file. * config/lm32/_udivsi3.c: New file. * config/lm32/_umodsi3.c: New file. * config/lm32/_lshrsi3.S: New file. * config/lm32/_ashrsi3.S: New file. * config/lm32/_ashlsi3.S: New file. * config/lm32/crti.S: New file. * config/lm32/crtn.S: New file. * config/lm32/t-lm32: New file. * config/lm32/t-elf: New file. * config/lm32/t-uclinux: New file. From-SVN: r154096
2009-11-11 17:43:06 +01:00
# _ashlsi3.S for Lattice Mico32
# Contributed by Jon Beniston <jon@beniston.com> and Richard Henderson.
#
# Copyright (C) 2009 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#
/* Arithmetic left shift. */
.text
.global __ashlsi3
.type __ashlsi3,@function
.align 4
__ashlsi3:
/* Only use 5 LSBs, as that's all the h/w shifter uses. */
andi r2, r2, 0x1f
/* Get address of offset into unrolled shift loop to jump to. */
#ifdef __PIC__
lw r3, (gp+got(__ashlsi3_0))
#else
mvhi r3, hi(__ashlsi3_0)
ori r3, r3, lo(__ashlsi3_0)
#endif
add r2, r2, r2
add r2, r2, r2
sub r3, r3, r2
b r3
__ashlsi3_31:
add r1, r1, r1
__ashlsi3_30:
add r1, r1, r1
__ashlsi3_29:
add r1, r1, r1
__ashlsi3_28:
add r1, r1, r1
__ashlsi3_27:
add r1, r1, r1
__ashlsi3_26:
add r1, r1, r1
__ashlsi3_25:
add r1, r1, r1
__ashlsi3_24:
add r1, r1, r1
__ashlsi3_23:
add r1, r1, r1
__ashlsi3_22:
add r1, r1, r1
__ashlsi3_21:
add r1, r1, r1
__ashlsi3_20:
add r1, r1, r1
__ashlsi3_19:
add r1, r1, r1
__ashlsi3_18:
add r1, r1, r1
__ashlsi3_17:
add r1, r1, r1
__ashlsi3_16:
add r1, r1, r1
__ashlsi3_15:
add r1, r1, r1
__ashlsi3_14:
add r1, r1, r1
__ashlsi3_13:
add r1, r1, r1
__ashlsi3_12:
add r1, r1, r1
__ashlsi3_11:
add r1, r1, r1
__ashlsi3_10:
add r1, r1, r1
__ashlsi3_9:
add r1, r1, r1
__ashlsi3_8:
add r1, r1, r1
__ashlsi3_7:
add r1, r1, r1
__ashlsi3_6:
add r1, r1, r1
__ashlsi3_5:
add r1, r1, r1
__ashlsi3_4:
add r1, r1, r1
__ashlsi3_3:
add r1, r1, r1
__ashlsi3_2:
add r1, r1, r1
__ashlsi3_1:
add r1, r1, r1
__ashlsi3_0:
ret