mips.md: Include 20kc.md.
2007-07-16 Sandra Loosemore <sandra@codesourcery.com>
Nigel Stephens <nigel@mips.com>
gcc/
* config/mips/mips.md: Include 20kc.md.
* config/mips/20kc.md: New file.
* config/mips/mips.c (mips_rtx_cost_data): Fill in 20Kc costs.
(mips_adjust_cost): Tweak for 20Kc.
(mips_issue_rate): Likewise.
* config/mips/mips.h (TUNE_20KC): Define.
Co-Authored-By: Nigel Stephens <nigel@mips.com>
From-SVN: r126687
This commit is contained in:
Sandra Loosemore
Sandra Loosemore
parent
0b11da6707
commit
0015c873f4
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@ -1,3 +1,13 @@
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2007-07-16 Sandra Loosemore <sandra@codesourcery.com>
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Nigel Stephens <nigel@mips.com>
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* config/mips/mips.md: Include 20kc.md.
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* config/mips/20kc.md: New file.
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* config/mips/mips.c (mips_rtx_cost_data): Fill in 20Kc costs.
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(mips_adjust_cost): Tweak for 20Kc.
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(mips_issue_rate): Likewise.
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* config/mips/mips.h (TUNE_20KC): Define.
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2007-07-16 David Edelsohn <edelsohn@gnu.og>
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* config/rs6000/rs6000.c (struct processor_cost): Add
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@ -0,0 +1,266 @@
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;; .........................
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;;
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;; DFA-based pipeline description for MIPS64 model R20Kc.
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;; Contributed by Jason Eckhardt (jle@cygnus.com).
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;;
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;; The R20Kc is a dual-issue processor that can generally bundle
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;; instructions as follows:
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;; 1. integer with integer
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;; 2. integer with fp
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;; 3. fp with fpload/fpstore
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;;
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;; Of course, there are various restrictions.
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;; Reference:
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;; "Ruby (R20K) Technical Specification Rev. 1.2, December 28, 1999."
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;;
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;; .........................
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;; Use three automata to isolate long latency operations, reducing space.
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(define_automaton "r20kc_other, r20kc_fdiv, r20kc_idiv")
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;;
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;; Describe the resources.
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;;
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;; Global.
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(define_cpu_unit "r20kc_iss0, r20kc_iss1" "r20kc_other")
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;; Integer execution unit (pipeline A).
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(define_cpu_unit "r20kc_ixua_addsub_agen" "r20kc_other")
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(define_cpu_unit "r20kc_ixua_shift" "r20kc_other")
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(exclusion_set "r20kc_ixua_addsub_agen" "r20kc_ixua_shift")
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;; Integer execution unit (pipeline B).
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(define_cpu_unit "r20kc_ixub_addsub" "r20kc_other")
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(define_cpu_unit "r20kc_ixub_branch" "r20kc_other")
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(define_cpu_unit "r20kc_ixub_mpydiv" "r20kc_other")
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(define_cpu_unit "r20kc_ixub_mpydiv_iter" "r20kc_idiv")
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(exclusion_set "r20kc_ixub_addsub" "r20kc_ixub_branch, r20kc_ixub_mpydiv")
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(exclusion_set "r20kc_ixub_branch" "r20kc_ixub_mpydiv")
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;; Cache / memory interface.
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(define_cpu_unit "r20kc_cache" "r20kc_other")
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;; Floating-point unit.
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(define_cpu_unit "r20kc_fpu_add" "r20kc_other")
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(define_cpu_unit "r20kc_fpu_mpy" "r20kc_other")
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(define_cpu_unit "r20kc_fpu_mpy_iter" "r20kc_fdiv")
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(define_cpu_unit "r20kc_fpu_divsqrt" "r20kc_other")
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(define_cpu_unit "r20kc_fpu_divsqrt_iter" "r20kc_fdiv")
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(exclusion_set "r20kc_fpu_add" "r20kc_fpu_mpy, r20kc_fpu_divsqrt")
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(exclusion_set "r20kc_fpu_mpy" "r20kc_fpu_divsqrt")
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;; After branch any insn can not be issued.
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(absence_set "r20kc_iss0,r20kc_iss1" "r20kc_ixub_branch")
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;;
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;; Define reservations for unit name mnemonics or combinations.
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;;
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(define_reservation "r20kc_iss"
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"r20kc_iss0|r20kc_iss1")
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(define_reservation "r20kc_single_dispatch"
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"r20kc_iss0+r20kc_iss1")
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(define_reservation "r20kc_iaddsub"
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"r20kc_iss+(r20kc_ixua_addsub_agen|r20kc_ixub_addsub)")
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(define_reservation "r20kc_ishift"
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"r20kc_iss+r20kc_ixua_shift")
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(define_reservation "r20kc_fpmove"
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"r20kc_iss+r20kc_ixua_addsub_agen")
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(define_reservation "r20kc_imem"
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"r20kc_iss+r20kc_ixua_addsub_agen+r20kc_cache")
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(define_reservation "r20kc_icache"
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"r20kc_cache")
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(define_reservation "r20kc_impydiv"
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"r20kc_iss+r20kc_ixub_mpydiv")
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(define_reservation "r20kc_impydiv_iter"
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"r20kc_ixub_mpydiv_iter")
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(define_reservation "r20kc_ibranch"
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"r20kc_iss+r20kc_ixub_branch")
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(define_reservation "r20kc_fpadd"
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"r20kc_iss+r20kc_fpu_add")
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(define_reservation "r20kc_fpmpy"
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"r20kc_iss+r20kc_fpu_mpy")
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(define_reservation "r20kc_fpmpy_iter"
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"r20kc_fpu_mpy_iter")
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(define_reservation "r20kc_fpdivsqrt"
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"r20kc_iss+r20kc_fpu_divsqrt")
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(define_reservation "r20kc_fpdivsqrt_iter"
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"r20kc_fpu_divsqrt_iter")
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;;
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;; Describe instruction reservations for integer operations.
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;;
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;; Conditional moves always force single-dispatch.
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(define_insn_reservation "r20kc_cond_move_int" 1
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "condmove")
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(eq_attr "mode" "!SF,DF")))
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"r20kc_single_dispatch")
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(define_insn_reservation "r20kc_cond_move_fp" 4
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "condmove")
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(eq_attr "mode" "SF,DF")))
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"r20kc_single_dispatch")
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(define_insn_reservation "r20kc_int_other" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "move,arith,const,nop"))
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"r20kc_iaddsub")
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;; Shifts can only execute on ixu pipeline A.
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(define_insn_reservation "r20kc_int_shift" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "shift"))
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"r20kc_ishift")
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(define_insn_reservation "r20kc_ld" 2
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "load,prefetch,prefetchx"))
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"r20kc_imem")
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;; A load immediately following a store will stall, so
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;; say that a store uses the cache for an extra cycle.
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(define_insn_reservation "r20kc_st" 2
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "store"))
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"r20kc_imem,r20kc_icache")
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(define_insn_reservation "r20kc_fld" 3
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "fpload"))
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"r20kc_imem")
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(define_insn_reservation "r20kc_ffst" 3
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "fpstore"))
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"r20kc_imem,r20kc_icache*2")
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;; Integer divide latency is between 13 and 42 cycles for DIV[U] and between
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;; 13 and 72 cycles for DDIV[U]. This depends on the value of the inputs
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;; so we just choose the worst case latency.
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(define_insn_reservation "r20kc_idiv_si" 42
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "SI")))
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"r20kc_impydiv+(r20kc_impydiv_iter*42)")
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(define_insn_reservation "r20kc_idiv_di" 72
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "DI")))
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"r20kc_impydiv+(r20kc_impydiv_iter*72)")
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;; Integer multiply latency is 4 or 7 cycles for word and double-word
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;; respectively.
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(define_insn_reservation "r20kc_impy_si" 4
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "imadd,imul,imul3")
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(eq_attr "mode" "SI")))
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"r20kc_impydiv+(r20kc_impydiv_iter*2)")
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(define_insn_reservation "r20kc_impy_di" 7
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "imadd,imul,imul3")
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(eq_attr "mode" "DI")))
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"r20kc_impydiv+(r20kc_impydiv_iter*7)")
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;; Move to/from HI/LO.
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;; Moving to HI/LO has a 3 cycle latency while moving from only has a 1
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;; cycle latency. Repeat rate is 3 for both.
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(define_insn_reservation "r20kc_imthilo" 3
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "mthilo"))
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"r20kc_impydiv+(r20kc_impydiv_iter*3)")
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(define_insn_reservation "r20kc_imfhilo" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "mfhilo"))
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"r20kc_impydiv+(r20kc_impydiv_iter*3)")
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;; Move to fp coprocessor.
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(define_insn_reservation "r20kc_ixfer_mt" 3
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "mtc"))
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"r20kc_fpmove")
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;; Move from fp coprocessor.
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(define_insn_reservation "r20kc_ixfer_mf" 2
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "mfc"))
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"r20kc_fpmove")
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;; Assume branch predicted correctly.
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(define_insn_reservation "r20kc_ibr" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "branch,jump,call"))
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"r20kc_ibranch")
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;;
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;; Describe instruction reservations for the floating-point operations.
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;;
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(define_insn_reservation "r20kc_fp_other" 4
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "fmove,fadd,fabs,fneg,fcmp"))
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"r20kc_fpadd")
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(define_insn_reservation "r20kc_fp_cvt_a" 4
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fcvt")
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(eq_attr "cnv_mode" "I2S,I2D,S2D")))
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"r20kc_fpadd")
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(define_insn_reservation "r20kc_fp_cvt_b" 5
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fcvt")
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(eq_attr "cnv_mode" "D2S,S2I")))
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"r20kc_fpadd")
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(define_insn_reservation "r20kc_fp_divsqrt_df" 32
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fdiv,fsqrt")
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(eq_attr "mode" "DF")))
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"r20kc_fpdivsqrt+(r20kc_fpdivsqrt_iter*32)")
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(define_insn_reservation "r20kc_fp_divsqrt_sf" 17
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fdiv,fsqrt")
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(eq_attr "mode" "SF")))
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"r20kc_fpdivsqrt+(r20kc_fpdivsqrt_iter*17)")
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(define_insn_reservation "r20kc_fp_rsqrt_df" 35
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "DF")))
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"r20kc_fpdivsqrt+(r20kc_fpdivsqrt_iter*35)")
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(define_insn_reservation "r20kc_fp_rsqrt_sf" 17
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "SF")))
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"r20kc_fpdivsqrt+(r20kc_fpdivsqrt_iter*17)")
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(define_insn_reservation "r20kc_fp_mpy_sf" 4
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"r20kc_fpmpy+r20kc_fpmpy_iter")
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(define_insn_reservation "r20kc_fp_mpy_df" 5
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"r20kc_fpmpy+(r20kc_fpmpy_iter*2)")
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;; Force single-dispatch for unknown or multi.
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(define_insn_reservation "r20kc_unknown" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "unknown,multi"))
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"r20kc_single_dispatch")
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@ -911,7 +911,17 @@ static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
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4 /* memory_latency */
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},
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{ /* 20KC */
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DEFAULT_COSTS
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COSTS_N_INSNS (4), /* fp_add */
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COSTS_N_INSNS (4), /* fp_mult_sf */
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COSTS_N_INSNS (5), /* fp_mult_df */
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COSTS_N_INSNS (17), /* fp_div_sf */
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COSTS_N_INSNS (32), /* fp_div_df */
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COSTS_N_INSNS (4), /* int_mult_si */
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COSTS_N_INSNS (7), /* int_mult_di */
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COSTS_N_INSNS (42), /* int_div_si */
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COSTS_N_INSNS (72), /* int_div_di */
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1, /* branch_cost */
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4 /* memory_latency */
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},
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{ /* 24KC */
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SOFT_FP_COSTS,
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@ -10866,12 +10876,16 @@ mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
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}
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/* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
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dependencies have no cost. */
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dependencies have no cost, except on the 20Kc where output-dependence
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is treated like input-dependence. */
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static int
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mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
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rtx dep ATTRIBUTE_UNUSED, int cost)
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{
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if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
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&& TUNE_20KC)
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return cost;
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if (REG_NOTE_KIND (link) != 0)
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return 0;
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return cost;
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@ -10894,6 +10908,7 @@ mips_issue_rate (void)
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floating point load/stores also require a slot in the AGEN pipe. */
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return 4;
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case PROCESSOR_20KC:
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case PROCESSOR_R4130:
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case PROCESSOR_R5400:
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case PROCESSOR_R5500:
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@ -254,6 +254,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
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|| mips_tune == PROCESSOR_74KF2_1 \
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|| mips_tune == PROCESSOR_74KF1_1 \
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|| mips_tune == PROCESSOR_74KF3_2)
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#define TUNE_20KC (mips_tune == PROCESSOR_20KC)
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/* True if the pre-reload scheduler should try to create chains of
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multiply-add or multiply-subtract instructions. For example,
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@ -640,6 +640,7 @@
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(include "4k.md")
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(include "5k.md")
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(include "20kc.md")
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(include "24k.md")
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(include "74k.md")
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(include "3000.md")
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