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alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Accept '(' for s/sv/svi. 

* alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Accept '(' for s/sv/svi.
* alpha.c (print_operand): Handle it.
* alpha.md (fix_truncsfdi2): Use it.  Add earlyclobber pattern
for ALPHA_TP_INSN.
(fix_truncdfdi2): Likewise.

From-SVN: r18996
This commit is contained in:
David Mosberger-Tang 1998-04-04 18:20:59 +00:00 committed by Richard Henderson
parent 092a4ef80c
commit 0022a94004
4 changed files with 56 additions and 6 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
Sat Apr 4 18:07:16 1998 David Mosberger-Tang (davidm@mostang.com)
* alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Accept '(' for s/sv/svi.
* alpha.c (print_operand): Handle it.
* alpha.md (fix_truncsfdi2): Use it. Add earlyclobber pattern
for ALPHA_TP_INSN.
(fix_truncdfdi2): Likewise.
Sat Apr 4 17:42:05 1998 Richard Henderson <rth@cygnus.com>
* tree.h (sizetype_tab[2], sbitsizetype, ubitsizetype): Merge all

19
gcc/config/alpha/alpha.c
View File

@ -2374,6 +2374,25 @@ print_operand (file, x, code)
fputs ("su", file);
break;
case '(':
/* Generates trap-mode suffix for instructions that accept the
v, sv, and svi suffix. The only instruction that needs this
is cvttq. */
switch (alpha_fptm)
{
case ALPHA_FPTM_N:
case ALPHA_FPTM_U:
fputs ("v", file);
break;
case ALPHA_FPTM_SU:
fputs ("sv", file);
break;
case ALPHA_FPTM_SUI:
fputs ("svi", file);
break;
}
break;
case ')':
/* Generates trap-mode suffix for instructions that accept the u, su,
and sui suffix. This is the bulk of the IEEE floating point

8
gcc/config/alpha/alpha.h
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@ -2139,6 +2139,10 @@ do { \
' Generates trap-mode suffix for instructions that accept the
su suffix only (cmpt et al).
( Generates trap-mode suffix for instructions that accept the
v, sv, and svi suffix. The only instruction that needs this
is cvttq.
) Generates trap-mode suffix for instructions that accept the
u, su, and sui suffix. This is the bulk of the IEEE floating
point instructions (addt et al).
@ -2154,8 +2158,8 @@ do { \
*/
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '&' || (CODE) == '\'' || (CODE) == ')' || (CODE) == '+' \
|| (CODE) == ',' || (CODE) == '-')
((CODE) == '&' || (CODE) == '\'' || (CODE) == '(' || (CODE) == ')' \
|| (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
/* Print a memory address as an operand to reference that memory location. */

27
gcc/config/alpha/alpha.md
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@ -1771,20 +1771,39 @@
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=&f")
(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
"TARGET_FP && alpha_tp == ALPHA_TP_INSN"
"cvt%-q%(c %R1,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
"TARGET_FP"
"cvt%-qc %R1,%0"
[(set_attr "type" "fadd")])
"cvt%-q%(c %R1,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=&f")
(fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
"TARGET_FP && alpha_tp == ALPHA_TP_INSN"
"cvt%-q%(c %R1,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
"TARGET_FP"
"cvt%-qc %R1,%0"
[(set_attr "type" "fadd")])
"cvt%-q%(c %R1,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")