re PR target/65105 ([i386] XMM registers are not used for 64bit computations on 32bit target)
gcc/ PR target/65105 * config/i386/i386.c: Include dbgcnt.h. (has_non_address_hard_reg): New. (convertible_comparison_p): New. (scalar_to_vector_candidate_p): New. (remove_non_convertible_regs): New. (scalar_chain): New. (scalar_chain::scalar_chain): New. (scalar_chain::~scalar_chain): New. (scalar_chain::add_to_queue): New. (scalar_chain::mark_dual_mode_def): New. (scalar_chain::analyze_register_chain): New. (scalar_chain::add_insn): New. (scalar_chain::build): New. (scalar_chain::compute_convert_gain): New. (scalar_chain::replace_with_subreg): New. (scalar_chain::replace_with_subreg_in_insn): New. (scalar_chain::emit_conversion_insns): New. (scalar_chain::make_vector_copies): New. (scalar_chain::convert_reg): New. (scalar_chain::convert_op): New. (scalar_chain::convert_insn): New. (scalar_chain::convert): New. (convert_scalars_to_vector): New. (pass_data_stv): New. (pass_stv): New. (make_pass_stv): New. (ix86_option_override): Created and register stv pass. (flag_opts): Add -mstv. (ix86_option_override_internal): Likewise. * config/i386/i386.md (SWIM1248x): New. (*movdi_internal): Add xmm to mem alternative for TARGET_STV. (and<mode>3): Use SWIM1248x iterator instead of SWIM. (*anddi3_doubleword): New. (*zext<mode>_doubleword): New. (*zextsi_doubleword): New. (<code><mode>3): Use SWIM1248x iterator instead of SWIM. (*<code>di3_doubleword): New. * config/i386/i386.opt (mstv): New. * dbgcnt.def (stv_conversion): New. gcc/testsuite/ PR target/65105 * gcc.target/i386/pr65105-1.c: New. * gcc.target/i386/pr65105-2.c: New. * gcc.target/i386/pr65105-3.c: New. * gcc.target/i386/pr65105-4.C: New. * gcc.dg/lower-subreg-1.c: Add -mno-stv options for ia32. From-SVN: r228231
This commit is contained in:
Ilya Enkovich
Ilya Enkovich
parent
2943f6f716
commit
006ba5047c
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@ -1,3 +1,46 @@
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2015-09-29 Ilya Enkovich <enkovich.gnu@gmail.com>
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PR target/65105
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* config/i386/i386.c: Include dbgcnt.h.
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(has_non_address_hard_reg): New.
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(convertible_comparison_p): New.
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(scalar_to_vector_candidate_p): New.
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(remove_non_convertible_regs): New.
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(scalar_chain): New.
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(scalar_chain::scalar_chain): New.
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(scalar_chain::~scalar_chain): New.
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(scalar_chain::add_to_queue): New.
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(scalar_chain::mark_dual_mode_def): New.
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(scalar_chain::analyze_register_chain): New.
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(scalar_chain::add_insn): New.
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(scalar_chain::build): New.
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(scalar_chain::compute_convert_gain): New.
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(scalar_chain::replace_with_subreg): New.
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(scalar_chain::replace_with_subreg_in_insn): New.
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(scalar_chain::emit_conversion_insns): New.
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(scalar_chain::make_vector_copies): New.
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(scalar_chain::convert_reg): New.
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(scalar_chain::convert_op): New.
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(scalar_chain::convert_insn): New.
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(scalar_chain::convert): New.
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(convert_scalars_to_vector): New.
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(pass_data_stv): New.
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(pass_stv): New.
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(make_pass_stv): New.
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(ix86_option_override): Created and register stv pass.
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(flag_opts): Add -mstv.
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(ix86_option_override_internal): Likewise.
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* config/i386/i386.md (SWIM1248x): New.
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(*movdi_internal): Add xmm to mem alternative for TARGET_STV.
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(and<mode>3): Use SWIM1248x iterator instead of SWIM.
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(*anddi3_doubleword): New.
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(*zext<mode>_doubleword): New.
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(*zextsi_doubleword): New.
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(<code><mode>3): Use SWIM1248x iterator instead of SWIM.
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(*<code>di3_doubleword): New.
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* config/i386/i386.opt (mstv): New.
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* dbgcnt.def (stv_conversion): New.
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2015-09-29 Tom de Vries <tom@codesourcery.com>
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* tree-cfg.c (dump_function_to_file): Dump function attributes.
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@ -87,6 +87,7 @@ along with GCC; see the file COPYING3. If not see
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#include "tree-iterator.h"
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#include "tree-chkp.h"
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#include "rtl-chkp.h"
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#include "dbgcnt.h"
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/* This file should be included last. */
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#include "target-def.h"
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@ -2602,6 +2603,908 @@ rest_of_handle_insert_vzeroupper (void)
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return 0;
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}
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/* Return 1 if INSN uses or defines a hard register.
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Hard register uses in a memory address are ignored.
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Clobbers and flags definitions are ignored. */
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static bool
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has_non_address_hard_reg (rtx_insn *insn)
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{
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df_ref ref;
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FOR_EACH_INSN_DEF (ref, insn)
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if (HARD_REGISTER_P (DF_REF_REAL_REG (ref))
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&& !DF_REF_FLAGS_IS_SET (ref, DF_REF_MUST_CLOBBER)
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&& DF_REF_REGNO (ref) != FLAGS_REG)
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return true;
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FOR_EACH_INSN_USE (ref, insn)
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if (!DF_REF_REG_MEM_P (ref) && HARD_REGISTER_P (DF_REF_REAL_REG (ref)))
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return true;
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return false;
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}
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/* Check if comparison INSN may be transformed
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into vector comparison. Currently we transform
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zero checks only which look like:
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(set (reg:CCZ 17 flags)
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(compare:CCZ (ior:SI (subreg:SI (reg:DI x) 4)
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(subreg:SI (reg:DI x) 0))
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(const_int 0 [0]))) */
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static bool
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convertible_comparison_p (rtx_insn *insn)
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{
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if (!TARGET_SSE4_1)
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return false;
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rtx def_set = single_set (insn);
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gcc_assert (def_set);
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rtx src = SET_SRC (def_set);
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rtx dst = SET_DEST (def_set);
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gcc_assert (GET_CODE (src) == COMPARE);
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if (GET_CODE (dst) != REG
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|| REGNO (dst) != FLAGS_REG
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|| GET_MODE (dst) != CCZmode)
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return false;
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rtx op1 = XEXP (src, 0);
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rtx op2 = XEXP (src, 1);
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if (op2 != CONST0_RTX (GET_MODE (op2)))
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return false;
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if (GET_CODE (op1) != IOR)
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return false;
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op2 = XEXP (op1, 1);
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op1 = XEXP (op1, 0);
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if (!SUBREG_P (op1)
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|| !SUBREG_P (op2)
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|| GET_MODE (op1) != SImode
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|| GET_MODE (op2) != SImode
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|| ((SUBREG_BYTE (op1) != 0
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|| SUBREG_BYTE (op2) != GET_MODE_SIZE (SImode))
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&& (SUBREG_BYTE (op2) != 0
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|| SUBREG_BYTE (op1) != GET_MODE_SIZE (SImode))))
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return false;
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op1 = SUBREG_REG (op1);
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op2 = SUBREG_REG (op2);
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if (op1 != op2
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|| !REG_P (op1)
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|| GET_MODE (op1) != DImode)
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return false;
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return true;
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}
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/* Return 1 if INSN may be converted into vector
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instruction. */
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static bool
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scalar_to_vector_candidate_p (rtx_insn *insn)
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{
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rtx def_set = single_set (insn);
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if (!def_set)
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return false;
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if (has_non_address_hard_reg (insn))
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return false;
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rtx src = SET_SRC (def_set);
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rtx dst = SET_DEST (def_set);
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if (GET_CODE (src) == COMPARE)
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return convertible_comparison_p (insn);
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/* We are interested in DImode promotion only. */
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if (GET_MODE (src) != DImode
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|| GET_MODE (dst) != DImode)
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return false;
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if (!REG_P (dst) && !MEM_P (dst))
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return false;
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switch (GET_CODE (src))
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{
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case PLUS:
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case MINUS:
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case IOR:
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case XOR:
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case AND:
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break;
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case REG:
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return true;
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case MEM:
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return REG_P (dst);
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default:
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return false;
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}
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if (!REG_P (XEXP (src, 0)) && !MEM_P (XEXP (src, 0)))
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return false;
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if (!REG_P (XEXP (src, 1)) && !MEM_P (XEXP (src, 1)))
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return false;
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if (GET_MODE (XEXP (src, 0)) != DImode
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|| GET_MODE (XEXP (src, 1)) != DImode)
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return false;
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return true;
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}
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/* For a given bitmap of insn UIDs scans all instruction and
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remove insn from CANDIDATES in case it has both convertible
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and not convertible definitions.
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All insns in a bitmap are conversion candidates according to
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scalar_to_vector_candidate_p. Currently it implies all insns
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are single_set. */
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static void
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remove_non_convertible_regs (bitmap candidates)
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{
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bitmap_iterator bi;
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unsigned id;
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bitmap regs = BITMAP_ALLOC (NULL);
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EXECUTE_IF_SET_IN_BITMAP (candidates, 0, id, bi)
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{
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rtx def_set = single_set (DF_INSN_UID_GET (id)->insn);
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rtx reg = SET_DEST (def_set);
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if (!REG_P (reg)
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|| bitmap_bit_p (regs, REGNO (reg))
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|| HARD_REGISTER_P (reg))
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continue;
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for (df_ref def = DF_REG_DEF_CHAIN (REGNO (reg));
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def;
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def = DF_REF_NEXT_REG (def))
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{
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if (!bitmap_bit_p (candidates, DF_REF_INSN_UID (def)))
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{
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if (dump_file)
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fprintf (dump_file,
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"r%d has non convertible definition in insn %d\n",
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REGNO (reg), DF_REF_INSN_UID (def));
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bitmap_set_bit (regs, REGNO (reg));
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break;
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}
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}
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}
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EXECUTE_IF_SET_IN_BITMAP (regs, 0, id, bi)
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{
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for (df_ref def = DF_REG_DEF_CHAIN (id);
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def;
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def = DF_REF_NEXT_REG (def))
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if (bitmap_bit_p (candidates, DF_REF_INSN_UID (def)))
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{
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if (dump_file)
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fprintf (dump_file, "Removing insn %d from candidates list\n",
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DF_REF_INSN_UID (def));
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bitmap_clear_bit (candidates, DF_REF_INSN_UID (def));
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}
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}
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BITMAP_FREE (regs);
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}
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class scalar_chain
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{
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public:
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scalar_chain ();
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~scalar_chain ();
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static unsigned max_id;
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/* ID of a chain. */
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unsigned int chain_id;
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/* A queue of instructions to be included into a chain. */
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bitmap queue;
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/* Instructions included into a chain. */
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bitmap insns;
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/* All registers defined by a chain. */
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bitmap defs;
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/* Registers used in both vector and sclar modes. */
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bitmap defs_conv;
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void build (bitmap candidates, unsigned insn_uid);
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int compute_convert_gain ();
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int convert ();
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private:
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void add_insn (bitmap candidates, unsigned insn_uid);
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void add_to_queue (unsigned insn_uid);
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void mark_dual_mode_def (df_ref def);
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void analyze_register_chain (bitmap candidates, df_ref ref);
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rtx replace_with_subreg (rtx x, rtx reg, rtx subreg);
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void emit_conversion_insns (rtx insns, rtx_insn *pos);
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void replace_with_subreg_in_insn (rtx_insn *insn, rtx reg, rtx subreg);
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void convert_insn (rtx_insn *insn);
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void convert_op (rtx *op, rtx_insn *insn);
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void convert_reg (unsigned regno);
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void make_vector_copies (unsigned regno);
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};
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unsigned scalar_chain::max_id = 0;
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/* Initialize new chain. */
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scalar_chain::scalar_chain ()
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{
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chain_id = ++max_id;
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if (dump_file)
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fprintf (dump_file, "Created a new instruction chain #%d\n", chain_id);
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bitmap_obstack_initialize (NULL);
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insns = BITMAP_ALLOC (NULL);
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defs = BITMAP_ALLOC (NULL);
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defs_conv = BITMAP_ALLOC (NULL);
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queue = NULL;
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}
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/* Free chain's data. */
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scalar_chain::~scalar_chain ()
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{
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BITMAP_FREE (insns);
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BITMAP_FREE (defs);
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BITMAP_FREE (defs_conv);
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bitmap_obstack_release (NULL);
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}
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/* Add instruction into chains' queue. */
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void
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scalar_chain::add_to_queue (unsigned insn_uid)
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{
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if (bitmap_bit_p (insns, insn_uid)
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|| bitmap_bit_p (queue, insn_uid))
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return;
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if (dump_file)
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fprintf (dump_file, " Adding insn %d into chain's #%d queue\n",
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insn_uid, chain_id);
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bitmap_set_bit (queue, insn_uid);
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}
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/* Mark register defined by DEF as requiring conversion. */
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void
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scalar_chain::mark_dual_mode_def (df_ref def)
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{
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gcc_assert (DF_REF_REG_DEF_P (def));
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if (bitmap_bit_p (defs_conv, DF_REF_REGNO (def)))
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return;
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if (dump_file)
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fprintf (dump_file,
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" Mark r%d def in insn %d as requiring both modes in chain #%d\n",
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DF_REF_REGNO (def), DF_REF_INSN_UID (def), chain_id);
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bitmap_set_bit (defs_conv, DF_REF_REGNO (def));
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}
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/* Check REF's chain to add new insns into a queue
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and find registers requiring conversion. */
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void
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scalar_chain::analyze_register_chain (bitmap candidates, df_ref ref)
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{
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df_link *chain;
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gcc_assert (bitmap_bit_p (insns, DF_REF_INSN_UID (ref))
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|| bitmap_bit_p (candidates, DF_REF_INSN_UID (ref)));
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add_to_queue (DF_REF_INSN_UID (ref));
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for (chain = DF_REF_CHAIN (ref); chain; chain = chain->next)
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{
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unsigned uid = DF_REF_INSN_UID (chain->ref);
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if (!DF_REF_REG_MEM_P (chain->ref))
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{
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if (bitmap_bit_p (insns, uid))
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continue;
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if (bitmap_bit_p (candidates, uid))
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{
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add_to_queue (uid);
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continue;
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}
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}
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if (DF_REF_REG_DEF_P (chain->ref))
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{
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if (dump_file)
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fprintf (dump_file, " r%d def in insn %d isn't convertible\n",
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DF_REF_REGNO (chain->ref), uid);
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mark_dual_mode_def (chain->ref);
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}
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else
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{
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if (dump_file)
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fprintf (dump_file, " r%d use in insn %d isn't convertible\n",
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DF_REF_REGNO (chain->ref), uid);
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mark_dual_mode_def (ref);
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}
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}
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}
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/* Add instruction into a chain. */
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void
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scalar_chain::add_insn (bitmap candidates, unsigned int insn_uid)
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{
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if (bitmap_bit_p (insns, insn_uid))
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return;
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if (dump_file)
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fprintf (dump_file, " Adding insn %d to chain #%d\n", insn_uid, chain_id);
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bitmap_set_bit (insns, insn_uid);
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rtx_insn *insn = DF_INSN_UID_GET (insn_uid)->insn;
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rtx def_set = single_set (insn);
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if (def_set && REG_P (SET_DEST (def_set))
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&& !HARD_REGISTER_P (SET_DEST (def_set)))
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bitmap_set_bit (defs, REGNO (SET_DEST (def_set)));
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df_ref ref;
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df_ref def;
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for (ref = DF_INSN_UID_DEFS (insn_uid); ref; ref = DF_REF_NEXT_LOC (ref))
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if (!HARD_REGISTER_P (DF_REF_REG (ref)))
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for (def = DF_REG_DEF_CHAIN (DF_REF_REGNO (ref));
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def;
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def = DF_REF_NEXT_REG (def))
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analyze_register_chain (candidates, def);
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for (ref = DF_INSN_UID_USES (insn_uid); ref; ref = DF_REF_NEXT_LOC (ref))
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if (!DF_REF_REG_MEM_P (ref))
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analyze_register_chain (candidates, ref);
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}
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|
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/* Build new chain starting from insn INSN_UID recursively
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adding all dependent uses and definitions. */
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void
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scalar_chain::build (bitmap candidates, unsigned insn_uid)
|
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{
|
||||
queue = BITMAP_ALLOC (NULL);
|
||||
bitmap_set_bit (queue, insn_uid);
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file, "Building chain #%d...\n", chain_id);
|
||||
|
||||
while (!bitmap_empty_p (queue))
|
||||
{
|
||||
insn_uid = bitmap_first_set_bit (queue);
|
||||
bitmap_clear_bit (queue, insn_uid);
|
||||
bitmap_clear_bit (candidates, insn_uid);
|
||||
add_insn (candidates, insn_uid);
|
||||
}
|
||||
|
||||
if (dump_file)
|
||||
{
|
||||
fprintf (dump_file, "Collected chain #%d...\n", chain_id);
|
||||
fprintf (dump_file, " insns: ");
|
||||
dump_bitmap (dump_file, insns);
|
||||
if (!bitmap_empty_p (defs_conv))
|
||||
{
|
||||
bitmap_iterator bi;
|
||||
unsigned id;
|
||||
const char *comma = "";
|
||||
fprintf (dump_file, " defs to convert: ");
|
||||
EXECUTE_IF_SET_IN_BITMAP (defs_conv, 0, id, bi)
|
||||
{
|
||||
fprintf (dump_file, "%sr%d", comma, id);
|
||||
comma = ", ";
|
||||
}
|
||||
fprintf (dump_file, "\n");
|
||||
}
|
||||
}
|
||||
|
||||
BITMAP_FREE (queue);
|
||||
}
|
||||
|
||||
/* Compute a gain for chain conversion. */
|
||||
|
||||
int
|
||||
scalar_chain::compute_convert_gain ()
|
||||
{
|
||||
bitmap_iterator bi;
|
||||
unsigned insn_uid;
|
||||
int gain = 0;
|
||||
int cost = 0;
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file, "Computing gain for chain #%d...\n", chain_id);
|
||||
|
||||
EXECUTE_IF_SET_IN_BITMAP (insns, 0, insn_uid, bi)
|
||||
{
|
||||
rtx_insn *insn = DF_INSN_UID_GET (insn_uid)->insn;
|
||||
rtx def_set = single_set (insn);
|
||||
rtx src = SET_SRC (def_set);
|
||||
rtx dst = SET_DEST (def_set);
|
||||
|
||||
if (REG_P (src) && REG_P (dst))
|
||||
gain += COSTS_N_INSNS (2) - ix86_cost->sse_move;
|
||||
else if (REG_P (src) && MEM_P (dst))
|
||||
gain += 2 * ix86_cost->int_store[2] - ix86_cost->sse_store[1];
|
||||
else if (MEM_P (src) && REG_P (dst))
|
||||
gain += 2 * ix86_cost->int_load[2] - ix86_cost->sse_load[1];
|
||||
else if (GET_CODE (src) == PLUS
|
||||
|| GET_CODE (src) == MINUS
|
||||
|| GET_CODE (src) == IOR
|
||||
|| GET_CODE (src) == XOR
|
||||
|| GET_CODE (src) == AND)
|
||||
gain += ix86_cost->add;
|
||||
else if (GET_CODE (src) == COMPARE)
|
||||
{
|
||||
/* Assume comparison cost is the same. */
|
||||
}
|
||||
else
|
||||
gcc_unreachable ();
|
||||
}
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file, " Instruction convertion gain: %d\n", gain);
|
||||
|
||||
EXECUTE_IF_SET_IN_BITMAP (defs_conv, 0, insn_uid, bi)
|
||||
cost += DF_REG_DEF_COUNT (insn_uid) * ix86_cost->mmxsse_to_integer;
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file, " Registers convertion cost: %d\n", cost);
|
||||
|
||||
gain -= cost;
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file, " Total gain: %d\n", gain);
|
||||
|
||||
return gain;
|
||||
}
|
||||
|
||||
/* Replace REG in X with a V2DI subreg of NEW_REG. */
|
||||
|
||||
rtx
|
||||
scalar_chain::replace_with_subreg (rtx x, rtx reg, rtx new_reg)
|
||||
{
|
||||
if (x == reg)
|
||||
return gen_rtx_SUBREG (V2DImode, new_reg, 0);
|
||||
|
||||
const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
|
||||
int i, j;
|
||||
for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
|
||||
{
|
||||
if (fmt[i] == 'e')
|
||||
XEXP (x, i) = replace_with_subreg (XEXP (x, i), reg, new_reg);
|
||||
else if (fmt[i] == 'E')
|
||||
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
|
||||
XVECEXP (x, i, j) = replace_with_subreg (XVECEXP (x, i, j),
|
||||
reg, new_reg);
|
||||
}
|
||||
|
||||
return x;
|
||||
}
|
||||
|
||||
/* Replace REG in INSN with a V2DI subreg of NEW_REG. */
|
||||
|
||||
void
|
||||
scalar_chain::replace_with_subreg_in_insn (rtx_insn *insn, rtx reg, rtx new_reg)
|
||||
{
|
||||
replace_with_subreg (single_set (insn), reg, new_reg);
|
||||
}
|
||||
|
||||
/* Insert generated conversion instruction sequence INSNS
|
||||
after instruction AFTER. New BB may be required in case
|
||||
instruction has EH region attached. */
|
||||
|
||||
void
|
||||
scalar_chain::emit_conversion_insns (rtx insns, rtx_insn *after)
|
||||
{
|
||||
if (!control_flow_insn_p (after))
|
||||
{
|
||||
emit_insn_after (insns, after);
|
||||
return;
|
||||
}
|
||||
|
||||
basic_block bb = BLOCK_FOR_INSN (after);
|
||||
edge e = find_fallthru_edge (bb->succs);
|
||||
gcc_assert (e);
|
||||
|
||||
basic_block new_bb = split_edge (e);
|
||||
emit_insn_after (insns, BB_HEAD (new_bb));
|
||||
}
|
||||
|
||||
/* Make vector copies for all register REGNO definitions
|
||||
and replace its uses in a chain. */
|
||||
|
||||
void
|
||||
scalar_chain::make_vector_copies (unsigned regno)
|
||||
{
|
||||
rtx reg = regno_reg_rtx[regno];
|
||||
rtx vreg = gen_reg_rtx (DImode);
|
||||
df_ref ref;
|
||||
|
||||
for (ref = DF_REG_DEF_CHAIN (regno); ref; ref = DF_REF_NEXT_REG (ref))
|
||||
if (!bitmap_bit_p (insns, DF_REF_INSN_UID (ref)))
|
||||
{
|
||||
rtx_insn *insn = DF_REF_INSN (ref);
|
||||
|
||||
start_sequence ();
|
||||
if (TARGET_SSE4_1)
|
||||
{
|
||||
emit_insn (gen_sse2_loadld (gen_rtx_SUBREG (V4SImode, vreg, 0),
|
||||
CONST0_RTX (V4SImode),
|
||||
gen_rtx_SUBREG (SImode, reg, 0)));
|
||||
emit_insn (gen_sse4_1_pinsrd (gen_rtx_SUBREG (V4SImode, vreg, 0),
|
||||
gen_rtx_SUBREG (V4SImode, vreg, 0),
|
||||
gen_rtx_SUBREG (SImode, reg, 4),
|
||||
GEN_INT (2)));
|
||||
}
|
||||
else if (TARGET_INTER_UNIT_MOVES_TO_VEC)
|
||||
{
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_insn (gen_sse2_loadld (gen_rtx_SUBREG (V4SImode, vreg, 0),
|
||||
CONST0_RTX (V4SImode),
|
||||
gen_rtx_SUBREG (SImode, reg, 0)));
|
||||
emit_insn (gen_sse2_loadld (gen_rtx_SUBREG (V4SImode, tmp, 0),
|
||||
CONST0_RTX (V4SImode),
|
||||
gen_rtx_SUBREG (SImode, reg, 4)));
|
||||
emit_insn (gen_vec_interleave_lowv4si
|
||||
(gen_rtx_SUBREG (V4SImode, vreg, 0),
|
||||
gen_rtx_SUBREG (V4SImode, vreg, 0),
|
||||
gen_rtx_SUBREG (V4SImode, tmp, 0)));
|
||||
}
|
||||
else
|
||||
{
|
||||
rtx tmp = assign_386_stack_local (DImode, SLOT_TEMP);
|
||||
emit_move_insn (adjust_address (tmp, SImode, 0),
|
||||
gen_rtx_SUBREG (SImode, reg, 0));
|
||||
emit_move_insn (adjust_address (tmp, SImode, 4),
|
||||
gen_rtx_SUBREG (SImode, reg, 4));
|
||||
emit_move_insn (vreg, tmp);
|
||||
}
|
||||
emit_conversion_insns (get_insns (), insn);
|
||||
end_sequence ();
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file,
|
||||
" Copied r%d to a vector register r%d for insn %d\n",
|
||||
regno, REGNO (vreg), DF_REF_INSN_UID (ref));
|
||||
}
|
||||
|
||||
for (ref = DF_REG_USE_CHAIN (regno); ref; ref = DF_REF_NEXT_REG (ref))
|
||||
if (bitmap_bit_p (insns, DF_REF_INSN_UID (ref)))
|
||||
{
|
||||
replace_with_subreg_in_insn (DF_REF_INSN (ref), reg, vreg);
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file, " Replaced r%d with r%d in insn %d\n",
|
||||
regno, REGNO (vreg), DF_REF_INSN_UID (ref));
|
||||
}
|
||||
}
|
||||
|
||||
/* Convert all definitions of register REGNO
|
||||
and fix its uses. Scalar copies may be created
|
||||
in case register is used in not convertible insn. */
|
||||
|
||||
void
|
||||
scalar_chain::convert_reg (unsigned regno)
|
||||
{
|
||||
bool scalar_copy = bitmap_bit_p (defs_conv, regno);
|
||||
rtx reg = regno_reg_rtx[regno];
|
||||
rtx scopy = NULL_RTX;
|
||||
df_ref ref;
|
||||
bitmap conv;
|
||||
|
||||
conv = BITMAP_ALLOC (NULL);
|
||||
bitmap_copy (conv, insns);
|
||||
|
||||
if (scalar_copy)
|
||||
scopy = gen_reg_rtx (DImode);
|
||||
|
||||
for (ref = DF_REG_DEF_CHAIN (regno); ref; ref = DF_REF_NEXT_REG (ref))
|
||||
{
|
||||
rtx_insn *insn = DF_REF_INSN (ref);
|
||||
rtx def_set = single_set (insn);
|
||||
rtx src = SET_SRC (def_set);
|
||||
rtx reg = DF_REF_REG (ref);
|
||||
|
||||
if (!MEM_P (src))
|
||||
{
|
||||
replace_with_subreg_in_insn (insn, reg, reg);
|
||||
bitmap_clear_bit (conv, INSN_UID (insn));
|
||||
}
|
||||
|
||||
if (scalar_copy)
|
||||
{
|
||||
rtx vcopy = gen_reg_rtx (V2DImode);
|
||||
|
||||
start_sequence ();
|
||||
if (TARGET_INTER_UNIT_MOVES_FROM_VEC)
|
||||
{
|
||||
emit_move_insn (vcopy, gen_rtx_SUBREG (V2DImode, reg, 0));
|
||||
emit_move_insn (gen_rtx_SUBREG (SImode, scopy, 0),
|
||||
gen_rtx_SUBREG (SImode, vcopy, 0));
|
||||
emit_move_insn (vcopy,
|
||||
gen_rtx_LSHIFTRT (V2DImode, vcopy, GEN_INT (32)));
|
||||
emit_move_insn (gen_rtx_SUBREG (SImode, scopy, 4),
|
||||
gen_rtx_SUBREG (SImode, vcopy, 0));
|
||||
}
|
||||
else
|
||||
{
|
||||
rtx tmp = assign_386_stack_local (DImode, SLOT_TEMP);
|
||||
emit_move_insn (tmp, reg);
|
||||
emit_move_insn (gen_rtx_SUBREG (SImode, scopy, 0),
|
||||
adjust_address (tmp, SImode, 0));
|
||||
emit_move_insn (gen_rtx_SUBREG (SImode, scopy, 4),
|
||||
adjust_address (tmp, SImode, 4));
|
||||
}
|
||||
emit_conversion_insns (get_insns (), insn);
|
||||
end_sequence ();
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file,
|
||||
" Copied r%d to a scalar register r%d for insn %d\n",
|
||||
regno, REGNO (scopy), INSN_UID (insn));
|
||||
}
|
||||
}
|
||||
|
||||
for (ref = DF_REG_USE_CHAIN (regno); ref; ref = DF_REF_NEXT_REG (ref))
|
||||
if (bitmap_bit_p (insns, DF_REF_INSN_UID (ref)))
|
||||
{
|
||||
if (bitmap_bit_p (conv, DF_REF_INSN_UID (ref)))
|
||||
{
|
||||
rtx def_set = single_set (DF_REF_INSN (ref));
|
||||
if (!MEM_P (SET_DEST (def_set))
|
||||
|| !REG_P (SET_SRC (def_set)))
|
||||
replace_with_subreg_in_insn (DF_REF_INSN (ref), reg, reg);
|
||||
bitmap_clear_bit (conv, DF_REF_INSN_UID (ref));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
replace_rtx (DF_REF_INSN (ref), reg, scopy);
|
||||
df_insn_rescan (DF_REF_INSN (ref));
|
||||
}
|
||||
|
||||
BITMAP_FREE (conv);
|
||||
}
|
||||
|
||||
/* Convert operand OP in INSN. All register uses
|
||||
are converted during registers conversion.
|
||||
Therefore we should just handle memory operands. */
|
||||
|
||||
void
|
||||
scalar_chain::convert_op (rtx *op, rtx_insn *insn)
|
||||
{
|
||||
*op = copy_rtx_if_shared (*op);
|
||||
|
||||
if (MEM_P (*op))
|
||||
{
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
|
||||
emit_insn_before (gen_move_insn (tmp, *op), insn);
|
||||
*op = gen_rtx_SUBREG (V2DImode, tmp, 0);
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file, " Preloading operand for insn %d into r%d\n",
|
||||
INSN_UID (insn), REGNO (tmp));
|
||||
}
|
||||
else
|
||||
{
|
||||
gcc_assert (SUBREG_P (*op));
|
||||
gcc_assert (GET_MODE (*op) == V2DImode);
|
||||
}
|
||||
}
|
||||
|
||||
/* Convert INSN to vector mode. */
|
||||
|
||||
void
|
||||
scalar_chain::convert_insn (rtx_insn *insn)
|
||||
{
|
||||
rtx def_set = single_set (insn);
|
||||
rtx src = SET_SRC (def_set);
|
||||
rtx dst = SET_DEST (def_set);
|
||||
rtx subreg;
|
||||
|
||||
if (MEM_P (dst) && !REG_P (src))
|
||||
{
|
||||
/* There are no scalar integer instructions and therefore
|
||||
temporary register usage is required. */
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_conversion_insns (gen_move_insn (dst, tmp), insn);
|
||||
dst = gen_rtx_SUBREG (V2DImode, tmp, 0);
|
||||
}
|
||||
|
||||
switch (GET_CODE (src))
|
||||
{
|
||||
case PLUS:
|
||||
case MINUS:
|
||||
case IOR:
|
||||
case XOR:
|
||||
case AND:
|
||||
convert_op (&XEXP (src, 0), insn);
|
||||
convert_op (&XEXP (src, 1), insn);
|
||||
PUT_MODE (src, V2DImode);
|
||||
break;
|
||||
|
||||
case MEM:
|
||||
if (!REG_P (dst))
|
||||
convert_op (&src, insn);
|
||||
break;
|
||||
|
||||
case REG:
|
||||
break;
|
||||
|
||||
case SUBREG:
|
||||
gcc_assert (GET_MODE (src) == V2DImode);
|
||||
break;
|
||||
|
||||
case COMPARE:
|
||||
src = SUBREG_REG (XEXP (XEXP (src, 0), 0));
|
||||
|
||||
gcc_assert ((REG_P (src) && GET_MODE (src) == DImode)
|
||||
|| (SUBREG_P (src) && GET_MODE (src) == V2DImode));
|
||||
|
||||
if (REG_P (src))
|
||||
subreg = gen_rtx_SUBREG (V2DImode, src, 0);
|
||||
else
|
||||
subreg = copy_rtx_if_shared (src);
|
||||
emit_insn_before (gen_vec_interleave_lowv2di (copy_rtx_if_shared (subreg),
|
||||
copy_rtx_if_shared (subreg),
|
||||
copy_rtx_if_shared (subreg)),
|
||||
insn);
|
||||
dst = gen_rtx_REG (CCmode, FLAGS_REG);
|
||||
src = gen_rtx_UNSPEC (CCmode, gen_rtvec (2, copy_rtx_if_shared (src),
|
||||
copy_rtx_if_shared (src)),
|
||||
UNSPEC_PTEST);
|
||||
break;
|
||||
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
|
||||
SET_SRC (def_set) = src;
|
||||
SET_DEST (def_set) = dst;
|
||||
|
||||
/* Drop possible dead definitions. */
|
||||
PATTERN (insn) = def_set;
|
||||
|
||||
INSN_CODE (insn) = -1;
|
||||
recog_memoized (insn);
|
||||
df_insn_rescan (insn);
|
||||
}
|
||||
|
||||
/* Convert whole chain creating required register
|
||||
conversions and copies. */
|
||||
|
||||
int
|
||||
scalar_chain::convert ()
|
||||
{
|
||||
bitmap_iterator bi;
|
||||
unsigned id;
|
||||
int converted_insns = 0;
|
||||
|
||||
if (!dbg_cnt (stv_conversion))
|
||||
return 0;
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file, "Converting chain #%d...\n", chain_id);
|
||||
|
||||
EXECUTE_IF_SET_IN_BITMAP (defs, 0, id, bi)
|
||||
convert_reg (id);
|
||||
|
||||
EXECUTE_IF_AND_COMPL_IN_BITMAP (defs_conv, defs, 0, id, bi)
|
||||
make_vector_copies (id);
|
||||
|
||||
EXECUTE_IF_SET_IN_BITMAP (insns, 0, id, bi)
|
||||
{
|
||||
convert_insn (DF_INSN_UID_GET (id)->insn);
|
||||
converted_insns++;
|
||||
}
|
||||
|
||||
return converted_insns;
|
||||
}
|
||||
|
||||
/* Main STV pass function. Find and convert scalar
|
||||
instructions into vector mode when profitable. */
|
||||
|
||||
static unsigned int
|
||||
convert_scalars_to_vector ()
|
||||
{
|
||||
basic_block bb;
|
||||
bitmap candidates;
|
||||
int converted_insns = 0;
|
||||
|
||||
bitmap_obstack_initialize (NULL);
|
||||
candidates = BITMAP_ALLOC (NULL);
|
||||
|
||||
calculate_dominance_info (CDI_DOMINATORS);
|
||||
df_set_flags (DF_DEFER_INSN_RESCAN);
|
||||
df_chain_add_problem (DF_DU_CHAIN | DF_UD_CHAIN);
|
||||
df_md_add_problem ();
|
||||
df_analyze ();
|
||||
|
||||
/* Find all instructions we want to convert into vector mode. */
|
||||
if (dump_file)
|
||||
fprintf (dump_file, "Searching for mode convertion candidates...\n");
|
||||
|
||||
FOR_EACH_BB_FN (bb, cfun)
|
||||
{
|
||||
rtx_insn *insn;
|
||||
FOR_BB_INSNS (bb, insn)
|
||||
if (scalar_to_vector_candidate_p (insn))
|
||||
{
|
||||
if (dump_file)
|
||||
fprintf (dump_file, " insn %d is marked as a candidate\n",
|
||||
INSN_UID (insn));
|
||||
|
||||
bitmap_set_bit (candidates, INSN_UID (insn));
|
||||
}
|
||||
}
|
||||
|
||||
remove_non_convertible_regs (candidates);
|
||||
|
||||
if (bitmap_empty_p (candidates))
|
||||
if (dump_file)
|
||||
fprintf (dump_file, "There are no candidates for optimization.\n");
|
||||
|
||||
while (!bitmap_empty_p (candidates))
|
||||
{
|
||||
unsigned uid = bitmap_first_set_bit (candidates);
|
||||
scalar_chain chain;
|
||||
|
||||
/* Find instructions chain we want to convert to vector mode.
|
||||
Check all uses and definitions to estimate all required
|
||||
conversions. */
|
||||
chain.build (candidates, uid);
|
||||
|
||||
if (chain.compute_convert_gain () > 0)
|
||||
converted_insns += chain.convert ();
|
||||
else
|
||||
if (dump_file)
|
||||
fprintf (dump_file, "Chain #%d conversion is not profitable\n",
|
||||
chain.chain_id);
|
||||
}
|
||||
|
||||
if (dump_file)
|
||||
fprintf (dump_file, "Total insns converted: %d\n", converted_insns);
|
||||
|
||||
BITMAP_FREE (candidates);
|
||||
bitmap_obstack_release (NULL);
|
||||
df_process_deferred_rescans ();
|
||||
|
||||
/* Conversion means we may have 128bit register spills/fills
|
||||
which require aligned stack. */
|
||||
if (converted_insns)
|
||||
{
|
||||
if (crtl->stack_alignment_needed < 128)
|
||||
crtl->stack_alignment_needed = 128;
|
||||
if (crtl->stack_alignment_estimated < 128)
|
||||
crtl->stack_alignment_estimated = 128;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
namespace {
|
||||
|
||||
const pass_data pass_data_insert_vzeroupper =
|
||||
|
|
@ -2639,6 +3542,39 @@ public:
|
|||
|
||||
}; // class pass_insert_vzeroupper
|
||||
|
||||
const pass_data pass_data_stv =
|
||||
{
|
||||
RTL_PASS, /* type */
|
||||
"stv", /* name */
|
||||
OPTGROUP_NONE, /* optinfo_flags */
|
||||
TV_NONE, /* tv_id */
|
||||
0, /* properties_required */
|
||||
0, /* properties_provided */
|
||||
0, /* properties_destroyed */
|
||||
0, /* todo_flags_start */
|
||||
TODO_df_finish, /* todo_flags_finish */
|
||||
};
|
||||
|
||||
class pass_stv : public rtl_opt_pass
|
||||
{
|
||||
public:
|
||||
pass_stv (gcc::context *ctxt)
|
||||
: rtl_opt_pass (pass_data_stv, ctxt)
|
||||
{}
|
||||
|
||||
/* opt_pass methods: */
|
||||
virtual bool gate (function *)
|
||||
{
|
||||
return !TARGET_64BIT && TARGET_STV && TARGET_SSE2 && optimize > 1;
|
||||
}
|
||||
|
||||
virtual unsigned int execute (function *)
|
||||
{
|
||||
return convert_scalars_to_vector ();
|
||||
}
|
||||
|
||||
}; // class pass_stv
|
||||
|
||||
} // anon namespace
|
||||
|
||||
rtl_opt_pass *
|
||||
|
|
@ -2647,6 +3583,12 @@ make_pass_insert_vzeroupper (gcc::context *ctxt)
|
|||
return new pass_insert_vzeroupper (ctxt);
|
||||
}
|
||||
|
||||
rtl_opt_pass *
|
||||
make_pass_stv (gcc::context *ctxt)
|
||||
{
|
||||
return new pass_stv (ctxt);
|
||||
}
|
||||
|
||||
/* Return true if a red-zone is in use. */
|
||||
|
||||
static inline bool
|
||||
|
|
@ -2756,6 +3698,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
|
|||
{ "-mvect8-ret-in-mem", MASK_VECT8_RETURNS },
|
||||
{ "-m8bit-idiv", MASK_USE_8BIT_IDIV },
|
||||
{ "-mvzeroupper", MASK_VZEROUPPER },
|
||||
{ "-mstv", MASK_STV},
|
||||
{ "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD},
|
||||
{ "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE},
|
||||
{ "-mprefer-avx128", MASK_PREFER_AVX128},
|
||||
|
|
@ -4372,6 +5315,8 @@ ix86_option_override_internal (bool main_args_p,
|
|||
|
||||
if (!(opts_set->x_target_flags & MASK_VZEROUPPER))
|
||||
opts->x_target_flags |= MASK_VZEROUPPER;
|
||||
if (!(opts_set->x_target_flags & MASK_STV))
|
||||
opts->x_target_flags |= MASK_STV;
|
||||
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL]
|
||||
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_LOAD))
|
||||
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_LOAD;
|
||||
|
|
@ -4485,12 +5430,18 @@ ix86_option_override (void)
|
|||
= { pass_insert_vzeroupper, "reload",
|
||||
1, PASS_POS_INSERT_AFTER
|
||||
};
|
||||
opt_pass *pass_stv = make_pass_stv (g);
|
||||
struct register_pass_info stv_info
|
||||
= { pass_stv, "combine",
|
||||
1, PASS_POS_INSERT_AFTER
|
||||
};
|
||||
|
||||
ix86_option_override_internal (true, &global_options, &global_options_set);
|
||||
|
||||
|
||||
/* This needs to be done at start up. It's convenient to do it here. */
|
||||
register_pass (&insert_vzeroupper_info);
|
||||
register_pass (&stv_info);
|
||||
}
|
||||
|
||||
/* Implement the TARGET_OFFLOAD_OPTIONS hook. */
|
||||
|
|
|
|||
|
|
@ -981,6 +981,11 @@
|
|||
(HI "TARGET_HIMODE_MATH")
|
||||
SI])
|
||||
|
||||
;; Math-dependant integer modes with DImode.
|
||||
(define_mode_iterator SWIM1248x [(QI "TARGET_QIMODE_MATH")
|
||||
(HI "TARGET_HIMODE_MATH")
|
||||
SI (DI "(TARGET_STV && TARGET_SSE2) || TARGET_64BIT")])
|
||||
|
||||
;; Math-dependant single word integer modes without QImode.
|
||||
(define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")
|
||||
SI (DI "TARGET_64BIT")])
|
||||
|
|
@ -2097,9 +2102,9 @@
|
|||
|
||||
(define_insn "*movdi_internal"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand"
|
||||
"=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r ,?*Ym,*v,*v,*v,m ,?r ,?r,?*Yi,?*Ym,?*Yi,*k,*k ,*r ,*m")
|
||||
"=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r ,?*Ym,*v,*v,*v,m ,m,?r ,?r,?*Yi,?*Ym,?*Yi,*k,*k ,*r ,*m")
|
||||
(match_operand:DI 1 "general_operand"
|
||||
"riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*Yn,r ,C ,*v,m ,*v,*Yj,*v,r ,*Yj ,*Yn ,*r ,*km,*k,*k"))]
|
||||
"riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*Yn,r ,C ,*v,m ,*v,v,*Yj,*v,r ,*Yj ,*Yn ,*r ,*km,*k,*k"))]
|
||||
"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
{
|
||||
switch (get_attr_type (insn))
|
||||
|
|
@ -2177,9 +2182,9 @@
|
|||
[(set (attr "isa")
|
||||
(cond [(eq_attr "alternative" "0,1")
|
||||
(const_string "nox64")
|
||||
(eq_attr "alternative" "2,3,4,5,10,11,16,18,21,23")
|
||||
(eq_attr "alternative" "2,3,4,5,10,11,17,19,22,24")
|
||||
(const_string "x64")
|
||||
(eq_attr "alternative" "17")
|
||||
(eq_attr "alternative" "18")
|
||||
(const_string "x64_sse4")
|
||||
]
|
||||
(const_string "*")))
|
||||
|
|
@ -2190,13 +2195,13 @@
|
|||
(const_string "mmx")
|
||||
(eq_attr "alternative" "7,8,9,10,11")
|
||||
(const_string "mmxmov")
|
||||
(eq_attr "alternative" "12,17")
|
||||
(eq_attr "alternative" "12,18")
|
||||
(const_string "sselog1")
|
||||
(eq_attr "alternative" "13,14,15,16,18")
|
||||
(eq_attr "alternative" "13,14,15,16,17,19")
|
||||
(const_string "ssemov")
|
||||
(eq_attr "alternative" "19,20")
|
||||
(eq_attr "alternative" "20,21")
|
||||
(const_string "ssecvt")
|
||||
(eq_attr "alternative" "21,22,23,24")
|
||||
(eq_attr "alternative" "22,23,24,25")
|
||||
(const_string "mskmov")
|
||||
(and (match_operand 0 "register_operand")
|
||||
(match_operand 1 "pic_32bit_operand"))
|
||||
|
|
@ -2211,16 +2216,16 @@
|
|||
(set (attr "length_immediate")
|
||||
(cond [(and (eq_attr "alternative" "4") (eq_attr "type" "imov"))
|
||||
(const_string "8")
|
||||
(eq_attr "alternative" "17")
|
||||
(eq_attr "alternative" "18")
|
||||
(const_string "1")
|
||||
]
|
||||
(const_string "*")))
|
||||
(set (attr "prefix_rex")
|
||||
(if_then_else (eq_attr "alternative" "10,11,16,17,18")
|
||||
(if_then_else (eq_attr "alternative" "10,11,17,18,19")
|
||||
(const_string "1")
|
||||
(const_string "*")))
|
||||
(set (attr "prefix_extra")
|
||||
(if_then_else (eq_attr "alternative" "17")
|
||||
(if_then_else (eq_attr "alternative" "18")
|
||||
(const_string "1")
|
||||
(const_string "*")))
|
||||
(set (attr "prefix")
|
||||
|
|
@ -2248,13 +2253,26 @@
|
|||
]
|
||||
(const_string "TI"))
|
||||
|
||||
(and (eq_attr "alternative" "14,15")
|
||||
(and (eq_attr "alternative" "14,15,16")
|
||||
(not (match_test "TARGET_SSE2")))
|
||||
(const_string "V2SF")
|
||||
(eq_attr "alternative" "17")
|
||||
(eq_attr "alternative" "18")
|
||||
(const_string "TI")
|
||||
]
|
||||
(const_string "DI")))])
|
||||
(const_string "DI")))
|
||||
(set (attr "enabled")
|
||||
(cond [(eq_attr "alternative" "15")
|
||||
(if_then_else
|
||||
(match_test "TARGET_STV && TARGET_SSE2")
|
||||
(symbol_ref "false")
|
||||
(const_string "*"))
|
||||
(eq_attr "alternative" "16")
|
||||
(if_then_else
|
||||
(match_test "TARGET_STV && TARGET_SSE2")
|
||||
(symbol_ref "true")
|
||||
(symbol_ref "false"))
|
||||
]
|
||||
(const_string "*")))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand")
|
||||
|
|
@ -3814,6 +3832,26 @@
|
|||
"movz{bl|x}\t{%1, %k0|%k0, %1}"
|
||||
[(set_attr "type" "imovx")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn_and_split "*zext<mode>_doubleword"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(zero_extend:DI (match_operand:SWI12 1 "nonimmediate_operand" "<r>m")))]
|
||||
"!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
|
||||
"#"
|
||||
"&& reload_completed && GENERAL_REG_P (operands[0])"
|
||||
[(set (match_dup 0) (zero_extend:SI (match_dup 1)))
|
||||
(set (match_dup 2) (const_int 0))]
|
||||
"split_double_mode (DImode, &operands[0], 1, &operands[0], &operands[2]);")
|
||||
|
||||
(define_insn_and_split "*zextsi_doubleword"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
|
||||
"!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
|
||||
"#"
|
||||
"&& reload_completed && GENERAL_REG_P (operands[0])"
|
||||
[(set (match_dup 0) (match_dup 1))
|
||||
(set (match_dup 2) (const_int 0))]
|
||||
"split_double_mode (DImode, &operands[0], 1, &operands[0], &operands[2]);")
|
||||
|
||||
;; Sign extension instructions
|
||||
|
||||
|
|
@ -7863,9 +7901,9 @@
|
|||
;; it should be done with splitters.
|
||||
|
||||
(define_expand "and<mode>3"
|
||||
[(set (match_operand:SWIM 0 "nonimmediate_operand")
|
||||
(and:SWIM (match_operand:SWIM 1 "nonimmediate_operand")
|
||||
(match_operand:SWIM 2 "<general_szext_operand>")))]
|
||||
[(set (match_operand:SWIM1248x 0 "nonimmediate_operand")
|
||||
(and:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")
|
||||
(match_operand:SWIM1248x 2 "<general_szext_operand>")))]
|
||||
""
|
||||
{
|
||||
machine_mode mode = <MODE>mode;
|
||||
|
|
@ -7943,6 +7981,23 @@
|
|||
(const_string "*")))
|
||||
(set_attr "mode" "SI,DI,DI,SI,DI")])
|
||||
|
||||
(define_insn_and_split "*anddi3_doubleword"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
|
||||
(and:DI
|
||||
(match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
|
||||
(match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"!TARGET_64BIT && TARGET_STV && TARGET_SSE2 && ix86_binary_operator_ok (AND, DImode, operands)"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(and:SI (match_dup 1) (match_dup 2)))
|
||||
(clobber (reg:CC FLAGS_REG))])
|
||||
(parallel [(set (match_dup 3)
|
||||
(and:SI (match_dup 4) (match_dup 5)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);")
|
||||
|
||||
(define_insn "*andsi_1"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya,!k")
|
||||
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm,k")
|
||||
|
|
@ -8430,9 +8485,9 @@
|
|||
;; If this is considered useful, it should be done with splitters.
|
||||
|
||||
(define_expand "<code><mode>3"
|
||||
[(set (match_operand:SWIM 0 "nonimmediate_operand")
|
||||
(any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand")
|
||||
(match_operand:SWIM 2 "<general_operand>")))]
|
||||
[(set (match_operand:SWIM1248x 0 "nonimmediate_operand")
|
||||
(any_or:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")
|
||||
(match_operand:SWIM1248x 2 "<general_operand>")))]
|
||||
""
|
||||
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
|
||||
|
||||
|
|
@ -8450,6 +8505,23 @@
|
|||
[(set_attr "type" "alu,alu,msklog")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn_and_split "*<code>di3_doubleword"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
|
||||
(any_or:DI
|
||||
(match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
|
||||
(match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"!TARGET_64BIT && TARGET_STV && TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, DImode, operands)"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(any_or:SI (match_dup 1) (match_dup 2)))
|
||||
(clobber (reg:CC FLAGS_REG))])
|
||||
(parallel [(set (match_dup 3)
|
||||
(any_or:SI (match_dup 4) (match_dup 5)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);")
|
||||
|
||||
(define_insn "*<code>hi_1"
|
||||
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,!k")
|
||||
(any_or:HI
|
||||
|
|
|
|||
|
|
@ -567,6 +567,11 @@ Target Report Mask(VZEROUPPER) Save
|
|||
Generate vzeroupper instruction before a transfer of control flow out of
|
||||
the function.
|
||||
|
||||
mstv
|
||||
Target Report Mask(STV) Save
|
||||
Disable Scalar to Vector optimization pass transforming 64-bit integer
|
||||
computations into a vector ones.
|
||||
|
||||
mdispatch-scheduler
|
||||
Target RejectNegative Var(flag_dispatch_scheduler)
|
||||
Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 or bdver4 and Haifa scheduling
|
||||
|
|
|
|||
|
|
@ -186,6 +186,7 @@ DEBUG_COUNTER (sel_sched_region_cnt)
|
|||
DEBUG_COUNTER (sms_sched_loop)
|
||||
DEBUG_COUNTER (split_for_sched2)
|
||||
DEBUG_COUNTER (store_motion)
|
||||
DEBUG_COUNTER (stv_conversion)
|
||||
DEBUG_COUNTER (tail_call)
|
||||
DEBUG_COUNTER (treepre_insert)
|
||||
DEBUG_COUNTER (tree_sra)
|
||||
|
|
|
|||
|
|
@ -1,3 +1,12 @@
|
|||
2015-09-29 Ilya Enkovich <enkovich.gnu@gmail.com>
|
||||
|
||||
PR target/65105
|
||||
* gcc.target/i386/pr65105-1.c: New.
|
||||
* gcc.target/i386/pr65105-2.c: New.
|
||||
* gcc.target/i386/pr65105-3.c: New.
|
||||
* gcc.target/i386/pr65105-4.C: New.
|
||||
* gcc.dg/lower-subreg-1.c: Add -mno-stv options for ia32.
|
||||
|
||||
2015-09-28 Segher Boessenkool <segher@kernel.crashing.org>
|
||||
|
||||
* gcc.dg/asm-4.c: Use braced words for the regular expressions.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */
|
||||
/* { dg-options "-O -fdump-rtl-subreg1" } */
|
||||
/* { dg-additional-options "-mno-stv" { target ia32 } } */
|
||||
/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target ilp32 } */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,50 @@
|
|||
/* PR target/pr65105 */
|
||||
/* { dg-do run { target { ia32 } } } */
|
||||
/* { dg-options "-O2 -march=slm" } */
|
||||
/* { dg-final { scan-assembler "por" } } */
|
||||
/* { dg-final { scan-assembler "pand" } } */
|
||||
|
||||
#include "stdlib.h"
|
||||
|
||||
static int count = 0;
|
||||
|
||||
void __attribute__((noinline))
|
||||
counter (long long l)
|
||||
{
|
||||
count++;
|
||||
if (!l || count > 5)
|
||||
exit (1);
|
||||
}
|
||||
|
||||
void __attribute__((noinline))
|
||||
test (long long *arr)
|
||||
{
|
||||
register unsigned long long tmp;
|
||||
|
||||
tmp = arr[0] | arr[1] & arr[2];
|
||||
while (tmp)
|
||||
{
|
||||
counter (tmp);
|
||||
tmp = *(arr++) & tmp;
|
||||
}
|
||||
}
|
||||
|
||||
void __attribute__((noinline))
|
||||
fill_data (long long *arr)
|
||||
{
|
||||
arr[0] = 0x00ffffffL;
|
||||
arr[1] = 0xffffff00L;
|
||||
arr[2] = 0x00ffffffL;
|
||||
arr[3] = 0x0000ff00L;
|
||||
arr[4] = 0x00ff0000L;
|
||||
arr[5] = 0xff000000L;
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, const char **argv)
|
||||
{
|
||||
long long arr[6];
|
||||
fill_data (arr);
|
||||
test (arr);
|
||||
return count - 5;
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* PR target/pr65105 */
|
||||
/* { dg-do compile { target { ia32 } } } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-final { scan-assembler "por" } } */
|
||||
|
||||
long long i1, i2, res;
|
||||
|
||||
void
|
||||
test ()
|
||||
{
|
||||
res = i1 | i2;
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* PR target/pr65105 */
|
||||
/* { dg-do compile { target { ia32 } } } */
|
||||
/* { dg-options "-O2 -march=slm -msse4.2" } */
|
||||
/* { dg-final { scan-assembler "pand" } } */
|
||||
/* { dg-final { scan-assembler "por" } } */
|
||||
/* { dg-final { scan-assembler "ptest" } } */
|
||||
|
||||
long long i1, i2, i3, res;
|
||||
|
||||
void
|
||||
test ()
|
||||
{
|
||||
res = i1 | i2;
|
||||
if (res)
|
||||
res &= i3;
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* PR target/pr65105 */
|
||||
/* { dg-do run { target { ia32 } } } */
|
||||
/* { dg-options "-O2 -march=slm" } */
|
||||
|
||||
struct s {
|
||||
long long l1, l2, l3, l4, l5;
|
||||
} *a;
|
||||
long long b;
|
||||
long long fn1()
|
||||
{
|
||||
try
|
||||
{
|
||||
b = (a->l1 | a->l2 | a->l3 | a->l4 | a->l5);
|
||||
return a->l1;
|
||||
}
|
||||
catch (int)
|
||||
{
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue