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arm.md (attribute "type"): Rename "simple_alu_imm" to "arlo_imm". 

* config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to
	"arlo_imm".  Rename "alu_reg" to "arlo_reg".  Rename "simple_alu_shift" to
	"extend".  Split "alu_shift" into "shift" and "arlo_shift".  Split
	"alu_shift_reg" into "shift_reg" and "arlo_shift_reg".  List types
	in alphabetical order.
	(attribute "core_cycles"): Update for attribute changes.
	(arm_addsi3): Likewise.
	(addsi3_compare0): Likewise.
	(addsi3_compare0_scratch): Likewise.
	(addsi3_compare_op1): Likewise.
	(addsi3_compare_op2): Likewise.
	(compare_addsi2_op0): Likewise.
	(compare_addsi2_op1): Likewise.
	(addsi3_carryin_shift_<optab>): Likewise.
	(subsi3_carryin_shift): Likewise.
	(rsbsi3_carryin_shift): Likewise.
	(arm_subsi3_insn): Likewise.
	(subsi3_compare0): Likewise.
	(subsi3_compare): Likewise.
	(arm_andsi3_insn): Likewise.
	(thumb1_andsi3_insn): Likewise.
	(andsi3_compare0): Likewise.
	(andsi3_compare0_scratch): Likewise.
	(zeroextractsi_compare0_scratch
	(andsi_not_shiftsi_si): Likewise.
	(iorsi3_insn): Likewise.
	(iorsi3_compare0): Likewise.
	(iorsi3_compare0_scratch): Likewise.
	(arm_xorsi3): Likewise.
	(thumb1_xorsi3_insn): Likewise.
	(xorsi3_compare0): Likewise.
	(xorsi3_compare0_scratch): Likewise.
	(satsi_<SAT:code>_shift): Likewise.
	(rrx): Likewise.
	(arm_shiftsi3): Likewise.
	(shiftsi3_compare0): Likewise.
	(not_shiftsi): Likewise.
	(not_shiftsi_compare0): Likewise.
	(not_shiftsi_compare0_scratch): Likewise.
	(arm_one_cmplsi2): Likewise.
	(thumb_one_complsi2): Likewise.
	(notsi_compare0): Likewise.
	(notsi_compare0_scratch): Likewise.
	(thumb1_zero_extendhisi2): Likewise.
	(arm_zero_extendhisi2): Likewise.
	(arm_zero_extendhisi2_v6): Likewise.
	(arm_zero_extendhisi2addsi): Likewise.
	(thumb1_zero_extendqisi2): Likewise.
	(thumb1_zero_extendqisi2_v6): Likewise.
	(arm_zero_extendqisi2): Likewise.
	(arm_zero_extendqisi2_v6): Likewise.
	(arm_zero_extendqisi2addsi): Likewise.
	(thumb1_extendhisi2): Likewise.
	(arm_extendhisi2): Likewise.
	(arm_extendhisi2_v6): Likewise.
	(arm_extendqisi): Likewise.
	(arm_extendqisi_v6): Likewise.
	(arm_extendqisi2addsi): Likewise.
	(thumb1_extendqisi2): Likewise.
	(thumb1_movdi_insn): Likewise.
	(arm_movsi_insn): Likewise.
	(movsi_compare0): Likewise.
	(movhi_insn_arch4): Likewise.
	(movhi_bytes): Likewise.
	(arm_movqi_insn): Likewise.
	(thumb1_movqi_insn): Likewise.
	(arm32_movhf): Likewise.
	(thumb1_movhf): Likewise.
	(arm_movsf_soft_insn): Likewise.
	(thumb1_movsf_insn): Likewise.
	(movdf_soft_insn): Likewise.
	(thumb_movdf_insn): Likewise.
	(arm_cmpsi_insn): Likewise.
	(cmpsi_shiftsi): Likewise.
	(cmpsi_shiftsi_swp): Likewise.
	(arm_cmpsi_negshiftsi_si): Likewise.
	(movsicc_insn): Likewise.
	(movsfcc_soft_insn): Likewise.
	(arith_shiftsi): Likewise.
	(arith_shiftsi_compare0
	(arith_shiftsi_compare0_scratch
	(sub_shiftsi): Likewise.
	(sub_shiftsi_compare0
	(sub_shiftsi_compare0_scratch
	(and_scc): Likewise.
	(cond_move): Likewise.
	(if_plus_move): Likewise.
	(if_move_plus): Likewise.
	(if_move_not): Likewise.
	(if_not_move): Likewise.
	(if_shift_move): Likewise.
	(if_move_shift): Likewise.
	(if_shift_shift): Likewise.
	(if_not_arith): Likewise.
	(if_arith_not): Likewise.
	(cond_move_not): Likewise.
	(thumb1_ashlsi3): Set type attribute.
	(thumb1_ashrsi3): Likewise.
	(thumb1_lshrsi3): Likewise.
	(thumb1_rotrsi3): Likewise.
	(shiftsi3_compare0_scratch): Likewise.
	* config/arm/neon.md (neon_mov<mode>): Update for attribute changes.
	(neon_mov<mode>): Likewise.
	* config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Update for attribute
	changes.
	(thumb2_movsi_insn): Likewise.
	(thumb2_cmpsi_neg_shiftsi): Likewise.
	(thumb2_extendqisi_v6): Likewise.
	(thumb2_zero_extendhisi2_v6): Likewise.
	(thumb2_zero_extendqisi2_v6): Likewise.
	(thumb2_shiftsi3_short): Likewise.
	(thumb2_addsi3_compare0_scratch): Likewise.
	(orsi_not_shiftsi_si): Likewise.
	* config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes.
	* config/arm/arm-fixed.md (arm_ssatsihi_shift): Update for attribute
	changes.
	* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
	(1020alu_shift_op): Likewise.
	(1020alu_shift_reg_op): Likewise.
	* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
	(alu_shift_op): Likewise.
	(alu_shift_reg_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Update for attribute changes.
	(11_alu_shift_op): Likewise.
	(11_alu_shift_reg_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
	(9_alu_shift_reg_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute changes.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute changes.
	(cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_alu) : Update for attribute
	changes.
	(cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute
	changes.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute changes.
	(cortex_a8_alu_shift): Likewise.
	(cortex_a8_alu_shift_reg): Likewise.
	(cortex_a8_mov): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute changes.
	(cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute changes.
	* config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute changes.
	(cortex_r4_mov): Likewise.
	(cortex_r4_alu_shift): Likewise.
	(cortex_r4_alu_shift_reg): Likewise.
	* config/arm/fa526.md (526_alu_op): Update for attribute changes.
	(526_alu_shift_op): Likewise.
	* config/arm/fa606te.md (606te_alu_op): Update for attribute changes.
	* config/arm/fa626te.md (626te_alu_op): Update for attribute changes.
	(626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md (726te_shift_op): Update for attribute changes.
	(726te_alu_op): Likewise.
	(726te_alu_shift_op): Likewise.
	(726te_alu_shift_reg_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
	(mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute changes.
	(pj4_alu_e1_conds): Likewise.
	(pj4_alu): Likewise.
	(pj4_alu_conds): Likewise.
	(pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.
	* config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute changes.
	(cortexa7_older_only): Likewise.
	(cortexa7_younger): Likewise.

From-SVN: r201024
This commit is contained in:
Sofiane Naci 2013-07-18 09:08:56 +00:00 committed by Sofiane Naci
parent 651df1b26a
commit 006bd0062b
25 changed files with 444 additions and 261 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

175
gcc/ChangeLog
View File

@ -1,3 +1,178 @@
2013-07-18 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to
"arlo_imm". Rename "alu_reg" to "arlo_reg". Rename "simple_alu_shift" to
"extend". Split "alu_shift" into "shift" and "arlo_shift". Split
"alu_shift_reg" into "shift_reg" and "arlo_shift_reg". List types
in alphabetical order.
(attribute "core_cycles"): Update for attribute changes.
(arm_addsi3): Likewise.
(addsi3_compare0): Likewise.
(addsi3_compare0_scratch): Likewise.
(addsi3_compare_op1): Likewise.
(addsi3_compare_op2): Likewise.
(compare_addsi2_op0): Likewise.
(compare_addsi2_op1): Likewise.
(addsi3_carryin_shift_<optab>): Likewise.
(subsi3_carryin_shift): Likewise.
(rsbsi3_carryin_shift): Likewise.
(arm_subsi3_insn): Likewise.
(subsi3_compare0): Likewise.
(subsi3_compare): Likewise.
(arm_andsi3_insn): Likewise.
(thumb1_andsi3_insn): Likewise.
(andsi3_compare0): Likewise.
(andsi3_compare0_scratch): Likewise.
(zeroextractsi_compare0_scratch
(andsi_not_shiftsi_si): Likewise.
(iorsi3_insn): Likewise.
(iorsi3_compare0): Likewise.
(iorsi3_compare0_scratch): Likewise.
(arm_xorsi3): Likewise.
(thumb1_xorsi3_insn): Likewise.
(xorsi3_compare0): Likewise.
(xorsi3_compare0_scratch): Likewise.
(satsi_<SAT:code>_shift): Likewise.
(rrx): Likewise.
(arm_shiftsi3): Likewise.
(shiftsi3_compare0): Likewise.
(not_shiftsi): Likewise.
(not_shiftsi_compare0): Likewise.
(not_shiftsi_compare0_scratch): Likewise.
(arm_one_cmplsi2): Likewise.
(thumb_one_complsi2): Likewise.
(notsi_compare0): Likewise.
(notsi_compare0_scratch): Likewise.
(thumb1_zero_extendhisi2): Likewise.
(arm_zero_extendhisi2): Likewise.
(arm_zero_extendhisi2_v6): Likewise.
(arm_zero_extendhisi2addsi): Likewise.
(thumb1_zero_extendqisi2): Likewise.
(thumb1_zero_extendqisi2_v6): Likewise.
(arm_zero_extendqisi2): Likewise.
(arm_zero_extendqisi2_v6): Likewise.
(arm_zero_extendqisi2addsi): Likewise.
(thumb1_extendhisi2): Likewise.
(arm_extendhisi2): Likewise.
(arm_extendhisi2_v6): Likewise.
(arm_extendqisi): Likewise.
(arm_extendqisi_v6): Likewise.
(arm_extendqisi2addsi): Likewise.
(thumb1_extendqisi2): Likewise.
(thumb1_movdi_insn): Likewise.
(arm_movsi_insn): Likewise.
(movsi_compare0): Likewise.
(movhi_insn_arch4): Likewise.
(movhi_bytes): Likewise.
(arm_movqi_insn): Likewise.
(thumb1_movqi_insn): Likewise.
(arm32_movhf): Likewise.
(thumb1_movhf): Likewise.
(arm_movsf_soft_insn): Likewise.
(thumb1_movsf_insn): Likewise.
(movdf_soft_insn): Likewise.
(thumb_movdf_insn): Likewise.
(arm_cmpsi_insn): Likewise.
(cmpsi_shiftsi): Likewise.
(cmpsi_shiftsi_swp): Likewise.
(arm_cmpsi_negshiftsi_si): Likewise.
(movsicc_insn): Likewise.
(movsfcc_soft_insn): Likewise.
(arith_shiftsi): Likewise.
(arith_shiftsi_compare0
(arith_shiftsi_compare0_scratch
(sub_shiftsi): Likewise.
(sub_shiftsi_compare0
(sub_shiftsi_compare0_scratch
(and_scc): Likewise.
(cond_move): Likewise.
(if_plus_move): Likewise.
(if_move_plus): Likewise.
(if_move_not): Likewise.
(if_not_move): Likewise.
(if_shift_move): Likewise.
(if_move_shift): Likewise.
(if_shift_shift): Likewise.
(if_not_arith): Likewise.
(if_arith_not): Likewise.
(cond_move_not): Likewise.
(thumb1_ashlsi3): Set type attribute.
(thumb1_ashrsi3): Likewise.
(thumb1_lshrsi3): Likewise.
(thumb1_rotrsi3): Likewise.
(shiftsi3_compare0_scratch): Likewise.
* config/arm/neon.md (neon_mov<mode>): Update for attribute changes.
(neon_mov<mode>): Likewise.
* config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Update for attribute
changes.
(thumb2_movsi_insn): Likewise.
(thumb2_cmpsi_neg_shiftsi): Likewise.
(thumb2_extendqisi_v6): Likewise.
(thumb2_zero_extendhisi2_v6): Likewise.
(thumb2_zero_extendqisi2_v6): Likewise.
(thumb2_shiftsi3_short): Likewise.
(thumb2_addsi3_compare0_scratch): Likewise.
(orsi_not_shiftsi_si): Likewise.
* config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes.
* config/arm/arm-fixed.md (arm_ssatsihi_shift): Update for attribute
changes.
* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
(1020alu_shift_op): Likewise.
(1020alu_shift_reg_op): Likewise.
* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
(alu_shift_op): Likewise.
(alu_shift_reg_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_op): Update for attribute changes.
(11_alu_shift_op): Likewise.
(11_alu_shift_reg_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
(9_alu_shift_reg_op): Likewise.
* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute changes.
(cortex_a15_alu_shift): Likewise.
(cortex_a15_alu_shift_reg): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute changes.
(cortex_a5_alu_shift): Likewise.
* config/arm/cortex-a53.md (cortex_a53_alu) : Update for attribute
changes.
(cortex_a53_alu_shift): Likewise.
* config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute
changes.
(cortex_a7_alu_reg): Likewise.
(cortex_a7_alu_shift): Likewise.
* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute changes.
(cortex_a8_alu_shift): Likewise.
(cortex_a8_alu_shift_reg): Likewise.
(cortex_a8_mov): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute changes.
(cortex_a9_dp_shift): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute changes.
* config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute changes.
(cortex_r4_mov): Likewise.
(cortex_r4_alu_shift): Likewise.
(cortex_r4_alu_shift_reg): Likewise.
* config/arm/fa526.md (526_alu_op): Update for attribute changes.
(526_alu_shift_op): Likewise.
* config/arm/fa606te.md (606te_alu_op): Update for attribute changes.
* config/arm/fa626te.md (626te_alu_op): Update for attribute changes.
(626te_alu_shift_op): Likewise.
* config/arm/fa726te.md (726te_shift_op): Update for attribute changes.
(726te_alu_op): Likewise.
(726te_alu_shift_op): Likewise.
(726te_alu_shift_reg_op): Likewise.
* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
(mp626_alu_shift_op): Likewise.
* config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute changes.
(pj4_alu_e1_conds): Likewise.
(pj4_alu): Likewise.
(pj4_alu_conds): Likewise.
(pj4_shift): Likewise.
(pj4_shift_conds): Likewise.
(pj4_alu_shift): Likewise.
(pj4_alu_shift_conds): Likewise.
* config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute changes.
(cortexa7_older_only): Likewise.
(cortexa7_younger): Likewise.
2013-07-18 David Malcolm <dmalcolm@redhat.com>
* ipa-pure-const.c (generate_summary): Rename to...

2
gcc/config/arm/arm-fixed.md
View File

@ -385,7 +385,7 @@
(set_attr "predicable_short_it" "no")
(set_attr "insn" "sat")
(set_attr "shift" "1")
(set_attr "type" "alu_shift")])
(set_attr "type" "arlo_shift")])
(define_insn "arm_usatsihi"
[(set (match_operand:HI 0 "s_register_operand" "=r")

10
gcc/config/arm/arm.c
View File

@ -8653,7 +8653,7 @@ xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
instruction we depend on is another ALU instruction, then we may
have to account for an additional stall. */
if (shift_opnum != 0
&& (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
&& (attr_type == TYPE_ARLO_SHIFT || attr_type == TYPE_ARLO_SHIFT_REG))
{
rtx shifted_operand;
int opno;
@ -8939,7 +8939,9 @@ cortexa7_older_only (rtx insn)
switch (get_attr_type (insn))
{
case TYPE_ALU_REG:
case TYPE_ARLO_REG:
case TYPE_SHIFT:
case TYPE_SHIFT_REG:
case TYPE_LOAD_BYTE:
case TYPE_LOAD1:
case TYPE_STORE1:
@ -8985,8 +8987,8 @@ cortexa7_younger (FILE *file, int verbose, rtx insn)
switch (get_attr_type (insn))
{
case TYPE_SIMPLE_ALU_IMM:
case TYPE_SIMPLE_ALU_SHIFT:
case TYPE_ARLO_IMM:
case TYPE_EXTEND:
case TYPE_BRANCH:
case TYPE_CALL:
return true;

386
gcc/config/arm/arm.md
View File

@ -257,15 +257,21 @@
;
; Instruction classification:
;
; alu_reg any alu instruction that doesn't hit memory or fp
; regs or have a shifted source operand and does not have
; an immediate operand. This is also the default.
; alu_shift any data instruction that doesn't hit memory or fp.
; regs, but has a source operand shifted by a constant.
; alu_shift_reg any data instruction that doesn't hit memory or fp.
; arlo_imm any arithmetic or logical instruction that doesn't have
; a shifted operand and has an immediate operand. This
; excludes MOV, MVN and RSB(S) immediate.
; arlo_reg any arithmetic or logical instruction that doesn't have
; a shifted or an immediate operand. This excludes
; MOV and MVN but includes MOVT. This is also the default.
; arlo_shift any arithmetic or logical instruction that has a source
; operand shifted by a constant. This excludes
; simple shifts.
; arlo_shift_reg as arlo_shift, with the shift amount specified in a
; register.
; block blockage insn, this blocks all functional units.
; branch branch.
; call subroutine call.
; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
; f_2_r transfer from float to core (no memory needed).
; f_cvt conversion between float and integral.
; f_flag transfer of co-processor flags to the CPSR.
@ -296,11 +302,9 @@
; muls integer multiply, flag setting.
; r_2_f transfer from core to float.
; sdiv signed division.
; simple_alu_imm simple alu instruction that doesn't hit memory or fp
; regs or have a shifted source operand and has an
; immediate operand. This currently only tracks very basic
; immediate alu operations.
; simple_alu_shift simple alu instruction with a shifted source operand.
; shift simple shift operation (LSL, LSR, ASR, ROR) with an
; immediate.
; shift_reg simple shift by a register.
; smlad signed multiply accumulate dual.
; smladx signed multiply accumulate dual reverse.
; smlal signed multiply accumulate long.
@ -401,89 +405,92 @@
; wmmx_wxor
(define_attr "type"
"simple_alu_imm,\
alu_reg,\
simple_alu_shift,\
alu_shift,\
alu_shift_reg,\
"arlo_imm,\
arlo_reg,\
arlo_shift,\
arlo_shift_reg,\
block,\
float,\
fdivd,\
fdivs,\
fmuls,\
fmuld,\
fmacs,\
fmacd,\
ffmas,\
ffmad,\
f_rints,\
f_rintd,\
f_minmaxs,\
f_minmaxd,\
f_flag,\
f_loads,\
f_loadd,\
f_stores,\
f_stored,\
f_2_r,\
r_2_f,\
f_cvt,\
f_sels,\
f_seld,\
branch,\
call,\
complex,\
extend,\
f_2_r,\
f_cvt,\
f_flag,\
f_loadd,\
f_loads,\
f_minmaxd,\
f_minmaxs,\
f_rintd,\
f_rints,\
f_seld,\
f_sels,\
f_stored,\
f_stores,\
faddd,\
fadds,\
fcmpd,\
fcmps,\
fconstd,\
fconsts,\
fcpys,\
fdivd,\
fdivs,\
ffarithd,\
ffariths,\
ffmad,\
ffmas,\
float,\
fmacd,\
fmacs,\
fmuld,\
fmuls,\
load_byte,\
load1,\
load2,\
load3,\
load4,\
mla,\
mlas,\
mul,\
muls,\
r_2_f,\
sdiv,\
shift,\
shift_reg,\
smlad,\
smladx,\
smlal,\
smlald,\
smlals,\
smlalxy,\
smlawx,\
smlawy,\
smlaxy,\
smlsd,\
smlsdx,\
smlsld,\
smmla,\
smmul,\
smmulr,\
smuad,\
smuadx,\
smull,\
smulls,\
smulwy,\
smulxy,\
smusd,\
smusdx,\
store1,\
store2,\
store3,\
store4,\
fconsts,\
fconstd,\
fadds,\
faddd,\
ffariths,\
ffarithd,\
fcmps,\
fcmpd,\
fcpys,\
smulxy,\
smlaxy,\
smlalxy,\
smulwy,\
smlawx,\
mul,\
muls,\
mla,\
mlas,\
umull,\
umulls,\
udiv,\
umaal,\
umlal,\
umlals,\
smull,\
smulls,\
smlal,\
smlals,\
smlawy,\
smuad,\
smuadx,\
smlad,\
smladx,\
smusd,\
smusdx,\
smlsd,\
smlsdx,\
smmul,\
smmulr,\
smmla,\
umaal,\
smlald,\
smlsld,\
sdiv,\
udiv,\
umull,\
umulls,\
wmmx_tandc,\
wmmx_tbcst,\
wmmx_textrc,\
@ -543,7 +550,7 @@
wmmx_wunpckih,\
wmmx_wunpckil,\
wmmx_wxor"
(const_string "alu_reg"))
(const_string "arlo_reg"))
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
(define_attr "mul32" "no,yes"
@ -686,8 +693,8 @@
; than one on the main cpu execution unit.
(define_attr "core_cycles" "single,multi"
(if_then_else (eq_attr "type"
"simple_alu_imm, alu_reg,\
simple_alu_shift, alu_shift, float, fdivd, fdivs,\
"arlo_imm, arlo_reg,\
extend, shift, arlo_shift, float, fdivd, fdivs,\
wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\
wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\
wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\
@ -968,8 +975,8 @@
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "simple_alu_imm")
(const_string "alu_reg")))
(const_string "arlo_imm")
(const_string "arlo_reg")))
]
)
@ -1050,7 +1057,7 @@
sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm, simple_alu_imm, *")]
(set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*addsi3_compare0_scratch"
@ -1066,7 +1073,7 @@
cmn%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "type" "simple_alu_imm, simple_alu_imm, *")
(set_attr "type" "arlo_imm,arlo_imm,*")
]
)
@ -1153,7 +1160,7 @@
sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
(set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*addsi3_compare_op2"
@ -1170,7 +1177,7 @@
add%.\\t%0, %1, %2
sub%.\\t%0, %1, #%n2"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
(set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*compare_addsi2_op0"
@ -1186,7 +1193,7 @@
cmn%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
(set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*compare_addsi2_op1"
@ -1202,7 +1209,7 @@
cmn%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
(set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*addsi3_carryin_<optab>"
@ -1244,8 +1251,8 @@
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
)
(define_insn "*addsi3_carryin_clobercc_<optab>"
@ -1322,8 +1329,8 @@
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
)
(define_insn "*rsbsi3_carryin_shift"
@ -1339,8 +1346,8 @@
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
)
; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant.
@ -1607,7 +1614,7 @@
"
[(set_attr "length" "4,4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "type" "*,simple_alu_imm,*,*,*")]
(set_attr "type" "*,arlo_imm,*,*,*")]
)
(define_peephole2
@ -1637,7 +1644,7 @@
sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm,*,*")]
(set_attr "type" "arlo_imm,*,*")]
)
(define_insn "subsi3_compare"
@ -1652,7 +1659,7 @@
sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm,*,*")]
(set_attr "type" "arlo_imm,*,*")]
)
(define_expand "subsf3"
@ -2588,7 +2595,7 @@
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no,no")
(set_attr "type"
"simple_alu_imm,simple_alu_imm,*,*,simple_alu_imm")]
"arlo_imm,arlo_imm,*,*,arlo_imm")]
)
(define_insn "*thumb1_andsi3_insn"
@ -2598,7 +2605,7 @@
"TARGET_THUMB1"
"and\\t%0, %2"
[(set_attr "length" "2")
(set_attr "type" "simple_alu_imm")
(set_attr "type" "arlo_imm")
(set_attr "conds" "set")])
(define_insn "*andsi3_compare0"
@ -2615,7 +2622,7 @@
bic%.\\t%0, %1, #%B2
and%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
(set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*andsi3_compare0_scratch"
@ -2631,7 +2638,7 @@
bic%.\\t%2, %0, #%B1
tst%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm,simple_alu_imm,*")]
(set_attr "type" "arlo_imm,arlo_imm,*")]
)
(define_insn "*zeroextractsi_compare0_scratch"
@ -2655,7 +2662,7 @@
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "type" "simple_alu_imm")]
(set_attr "type" "arlo_imm")]
)
(define_insn_and_split "*ne_zeroextractsi"
@ -3205,8 +3212,8 @@
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
)
(define_insn "*andsi_notsi_si_compare0"
@ -3365,7 +3372,7 @@
(set_attr "arch" "32,t2,t2,32,32")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no,no")
(set_attr "type" "simple_alu_imm,*,simple_alu_imm,*,*")]
(set_attr "type" "arlo_imm,*,arlo_imm,*,*")]
)
(define_insn "*thumb1_iorsi3_insn"
@ -3400,7 +3407,7 @@
"TARGET_32BIT"
"orr%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm,*")]
(set_attr "type" "arlo_imm,*")]
)
(define_insn "*iorsi3_compare0_scratch"
@ -3412,7 +3419,7 @@
"TARGET_32BIT"
"orr%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm, *")]
(set_attr "type" "arlo_imm,*")]
)
(define_expand "xordi3"
@ -3538,7 +3545,7 @@
[(set_attr "length" "4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no")
(set_attr "type" "simple_alu_imm,*,*,*")]
(set_attr "type" "arlo_imm,*,*,*")]
)
(define_insn "*thumb1_xorsi3_insn"
@ -3549,7 +3556,7 @@
"eor\\t%0, %2"
[(set_attr "length" "2")
(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm")]
(set_attr "type" "arlo_imm")]
)
(define_insn "*xorsi3_compare0"
@ -3562,7 +3569,7 @@
"TARGET_32BIT"
"eor%.\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm,*")]
(set_attr "type" "arlo_imm,*")]
)
(define_insn "*xorsi3_compare0_scratch"
@ -3573,7 +3580,7 @@
"TARGET_32BIT"
"teq%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm, *")]
(set_attr "type" "arlo_imm,*")]
)
; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C),
@ -4057,7 +4064,7 @@
[(set_attr "predicable" "yes")
(set_attr "insn" "sat")
(set_attr "shift" "3")
(set_attr "type" "alu_shift")])
(set_attr "type" "arlo_shift")])
;; Shift and rotation insns
@ -4160,6 +4167,7 @@
"TARGET_THUMB1"
"lsl\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "type" "shift,shift_reg")
(set_attr "conds" "set")])
(define_expand "ashrdi3"
@ -4243,7 +4251,7 @@
"mov\\t%0, %1, rrx"
[(set_attr "conds" "use")
(set_attr "insn" "mov")
(set_attr "type" "alu_shift")]
(set_attr "type" "arlo_shift")]
)
(define_expand "ashrsi3"
@ -4265,6 +4273,7 @@
"TARGET_THUMB1"
"asr\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "type" "shift,shift_reg")
(set_attr "conds" "set")])
(define_expand "lshrdi3"
@ -4361,6 +4370,7 @@
"TARGET_THUMB1"
"lsr\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "type" "shift,shift_reg")
(set_attr "conds" "set")])
(define_expand "rotlsi3"
@ -4406,68 +4416,64 @@
(match_operand:SI 2 "register_operand" "l")))]
"TARGET_THUMB1"
"ror\\t%0, %0, %2"
[(set_attr "length" "2")]
[(set_attr "type" "shift_reg")
(set_attr "length" "2")]
)
(define_insn "*arm_shiftsi3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "reg_or_int_operand" "rM")]))]
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "reg_or_int_operand" "M,r")]))]
"TARGET_32BIT"
"* return arm_output_shift(operands, 0);"
[(set_attr "predicable" "yes")
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(set_attr "type" "arlo_shift,arlo_shift_reg")]
)
(define_insn "*shiftsi3_compare"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")])
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r")
(set (match_operand:SI 0 "s_register_operand" "=r,r")
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))]
"TARGET_32BIT"
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(set_attr "type" "arlo_shift,arlo_shift_reg")]
)
(define_insn "*shiftsi3_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")])
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r")
(set (match_operand:SI 0 "s_register_operand" "=r,r")
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))]
"TARGET_32BIT"
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(set_attr "type" "arlo_shift,arlo_shift_reg")]
)
(define_insn "*shiftsi3_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rM")])
[(match_operand:SI 1 "s_register_operand" "r,r")
(match_operand:SI 2 "arm_rhs_operand" "M,r")])
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
(clobber (match_scratch:SI 0 "=r,r"))]
"TARGET_32BIT"
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")]
(set_attr "shift" "1")
(set_attr "type" "shift,shift_reg")]
)
(define_insn "*not_shiftsi"
@ -4482,7 +4488,7 @@
(set_attr "shift" "1")
(set_attr "insn" "mvn")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*not_shiftsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
@ -4499,7 +4505,7 @@
(set_attr "shift" "1")
(set_attr "insn" "mvn")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*not_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
@ -4515,7 +4521,7 @@
(set_attr "shift" "1")
(set_attr "insn" "mvn")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
;; We don't really have extzv, but defining this using shifts helps
;; to reduce register pressure later on.
@ -5536,7 +5542,7 @@
[(if_then_else (eq_attr "is_arch6" "yes")
(const_int 2) (const_int 4))
(const_int 4)])
(set_attr "type" "simple_alu_shift, load_byte")]
(set_attr "type" "extend,load_byte")]
)
(define_insn "*arm_zero_extendhisi2"
@ -5546,7 +5552,7 @@
"@
#
ldr%(h%)\\t%0, %1"
[(set_attr "type" "alu_shift,load_byte")
[(set_attr "type" "arlo_shift,load_byte")
(set_attr "predicable" "yes")]
)
@ -5558,7 +5564,7 @@
uxth%?\\t%0, %1
ldr%(h%)\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "type" "simple_alu_shift,load_byte")]
(set_attr "type" "extend,load_byte")]
)
(define_insn "*arm_zero_extendhisi2addsi"
@ -5567,7 +5573,7 @@
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_INT_SIMD"
"uxtah%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift")
[(set_attr "type" "arlo_shift")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
)
@ -5617,7 +5623,7 @@
#
ldrb\\t%0, %1"
[(set_attr "length" "4,2")
(set_attr "type" "alu_shift,load_byte")
(set_attr "type" "arlo_shift,load_byte")
(set_attr "pool_range" "*,32")]
)
@ -5629,7 +5635,7 @@
uxtb\\t%0, %1
ldrb\\t%0, %1"
[(set_attr "length" "2")
(set_attr "type" "simple_alu_shift,load_byte")]
(set_attr "type" "extend,load_byte")]
)
(define_insn "*arm_zero_extendqisi2"
@ -5640,7 +5646,7 @@
#
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "length" "8,4")
(set_attr "type" "alu_shift,load_byte")
(set_attr "type" "arlo_shift,load_byte")
(set_attr "predicable" "yes")]
)
@ -5651,7 +5657,7 @@
"@
uxtb%(%)\\t%0, %1
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "type" "simple_alu_shift,load_byte")
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")]
)
@ -5664,7 +5670,7 @@
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "insn" "xtab")
(set_attr "type" "alu_shift")]
(set_attr "type" "arlo_shift")]
)
(define_split
@ -5827,7 +5833,7 @@
[(if_then_else (eq_attr "is_arch6" "yes")
(const_int 2) (const_int 4))
(const_int 4)])
(set_attr "type" "simple_alu_shift,load_byte")
(set_attr "type" "extend,load_byte")
(set_attr "pool_range" "*,1018")]
)
@ -5886,7 +5892,7 @@
#
ldr%(sh%)\\t%0, %1"
[(set_attr "length" "8,4")
(set_attr "type" "alu_shift,load_byte")
(set_attr "type" "arlo_shift,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
@ -5900,7 +5906,7 @@
"@
sxth%?\\t%0, %1
ldr%(sh%)\\t%0, %1"
[(set_attr "type" "simple_alu_shift,load_byte")
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,256")
@ -5987,7 +5993,7 @@
#
ldr%(sb%)\\t%0, %1"
[(set_attr "length" "8,4")
(set_attr "type" "alu_shift,load_byte")
(set_attr "type" "arlo_shift,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
@ -6001,7 +6007,7 @@
"@
sxtb%?\\t%0, %1
ldr%(sb%)\\t%0, %1"
[(set_attr "type" "simple_alu_shift,load_byte")
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
@ -6013,7 +6019,7 @@
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_INT_SIMD"
"sxtab%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift")
[(set_attr "type" "arlo_shift")
(set_attr "insn" "xtab")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
@ -6115,7 +6121,7 @@
(const_int 2)
(if_then_else (eq_attr "is_arch6" "yes")
(const_int 4) (const_int 6))])
(set_attr "type" "simple_alu_shift,load_byte,load_byte")]
(set_attr "type" "extend,load_byte,load_byte")]
)
(define_expand "extendsfdf2"
@ -6490,7 +6496,7 @@
movw%?\\t%0, %1
ldr%?\\t%0, %1
str%?\\t%1, %0"
[(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,load1,store1")
[(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,load1,store1")
(set_attr "insn" "mov,mov,mvn,mov,*,*")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,*,*,*,4096,*")
@ -6793,7 +6799,7 @@
cmp%?\\t%0, #0
sub%.\\t%0, %1, #0"
[(set_attr "conds" "set")
(set_attr "type" "simple_alu_imm,simple_alu_imm")]
(set_attr "type" "arlo_imm,arlo_imm")]
)
;; Subroutine to store a half word from a register into memory.
@ -7212,9 +7218,9 @@
(set_attr "neg_pool_range" "*,*,*,244")
(set_attr_alternative "type"
[(if_then_else (match_operand 1 "const_int_operand" "")
(const_string "simple_alu_imm" )
(const_string "arlo_imm" )
(const_string "*"))
(const_string "simple_alu_imm")
(const_string "arlo_imm")
(const_string "store1")
(const_string "load1")])]
)
@ -7229,7 +7235,7 @@
mvn%?\\t%0, #%B1\\t%@ movhi"
[(set_attr "predicable" "yes")
(set_attr "insn" "mov, mov,mvn")
(set_attr "type" "simple_alu_imm,*,simple_alu_imm")]
(set_attr "type" "arlo_imm,*,arlo_imm")]
)
(define_expand "thumb_movhi_clobber"
@ -7368,7 +7374,7 @@
str%(b%)\\t%1, %0
ldr%(b%)\\t%0, %1
str%(b%)\\t%1, %0"
[(set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,simple_alu_imm,load1, store1, load1, store1")
[(set_attr "type" "*,*,arlo_imm,arlo_imm,arlo_imm,load1, store1, load1, store1")
(set_attr "insn" "mov,mov,mov,mov,mvn,*,*,*,*")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,yes,yes,no,no,no,no,no,no")
@ -7390,7 +7396,7 @@
mov\\t%0, %1
mov\\t%0, %1"
[(set_attr "length" "2")
(set_attr "type" "simple_alu_imm,load1,store1,*,*,simple_alu_imm")
(set_attr "type" "arlo_imm,load1,store1,*,*,arlo_imm")
(set_attr "insn" "*,*,*,mov,mov,mov")
(set_attr "pool_range" "*,32,*,*,*,*")
(set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
@ -8481,7 +8487,7 @@
(set_attr "arch" "t2,t2,any,any")
(set_attr "length" "2,2,4,4")
(set_attr "predicable" "yes")
(set_attr "type" "*,*,*,simple_alu_imm")]
(set_attr "type" "*,*,*,arlo_imm")]
)
(define_insn "*cmpsi_shiftsi"
@ -8495,7 +8501,7 @@
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*cmpsi_shiftsi_swp"
[(set (reg:CC_SWP CC_REGNUM)
@ -8508,7 +8514,7 @@
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*arm_cmpsi_negshiftsi_si"
[(set (reg:CC_Z CC_REGNUM)
@ -8521,8 +8527,8 @@
"cmn%?\\t%0, %2%S1"
[(set_attr "conds" "set")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))
(set_attr "predicable" "yes")]
)
@ -9174,13 +9180,13 @@
(set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn")
(set_attr_alternative "type"
[(if_then_else (match_operand 2 "const_int_operand" "")
(const_string "simple_alu_imm")
(const_string "arlo_imm")
(const_string "*"))
(const_string "simple_alu_imm")
(const_string "arlo_imm")
(if_then_else (match_operand 1 "const_int_operand" "")
(const_string "simple_alu_imm")
(const_string "arlo_imm")
(const_string "*"))
(const_string "simple_alu_imm")
(const_string "arlo_imm")
(const_string "*")
(const_string "*")
(const_string "*")
@ -10062,7 +10068,7 @@
(if_then_else
(match_operand:SI 3 "mult_operator" "")
(const_string "no") (const_string "yes"))])
(set_attr "type" "alu_shift,alu_shift,alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift,arlo_shift,arlo_shift_reg")])
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
@ -10099,7 +10105,7 @@
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*arith_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
@ -10116,7 +10122,7 @@
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*sub_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@ -10129,7 +10135,7 @@
[(set_attr "predicable" "yes")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*sub_shiftsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
@ -10147,7 +10153,7 @@
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn "*sub_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
@ -10163,7 +10169,7 @@
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
(set_attr "type" "alu_shift,alu_shift_reg")])
(set_attr "type" "arlo_shift,arlo_shift_reg")])
(define_insn_and_split "*and_scc"
@ -11171,9 +11177,9 @@
(set_attr "length" "4,4,8,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
(const_string "simple_alu_imm" )
(const_string "arlo_imm" )
(const_string "*"))
(const_string "simple_alu_imm")
(const_string "arlo_imm")
(const_string "*")
(const_string "*")])]
)
@ -11213,9 +11219,9 @@
(set_attr "length" "4,4,8,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
(const_string "simple_alu_imm" )
(const_string "arlo_imm" )
(const_string "*"))
(const_string "simple_alu_imm")
(const_string "arlo_imm")
(const_string "*")
(const_string "*")])]
)
@ -11474,8 +11480,8 @@
(set_attr "length" "4,8,8")
(set_attr "insn" "mov")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
)
(define_insn "*ifcompare_move_shift"
@ -11514,8 +11520,8 @@
(set_attr "length" "4,8,8")
(set_attr "insn" "mov")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
)
(define_insn "*ifcompare_shift_shift"
@ -11557,8 +11563,8 @@
(set (attr "type") (if_then_else
(and (match_operand 2 "const_int_operand" "")
(match_operand 4 "const_int_operand" ""))
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
)
(define_insn "*ifcompare_not_arith"

6
gcc/config/arm/arm1020e.md
View File

@ -66,13 +66,13 @@
;; ALU operations with no shifted operand
(define_insn_reservation "1020alu_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "alu_reg,simple_alu_imm"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "1020alu_shift_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "simple_alu_shift,alu_shift"))
(eq_attr "type" "extend,arlo_shift"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-register operand
@ -81,7 +81,7 @@
;; the execute stage.
(define_insn_reservation "1020alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1020e,arm1022e")
(eq_attr "type" "alu_shift_reg"))
(eq_attr "type" "arlo_shift_reg"))
"1020a_e*2,1020a_m,1020a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

6
gcc/config/arm/arm1026ejs.md
View File

@ -66,13 +66,13 @@
;; ALU operations with no shifted operand
(define_insn_reservation "alu_op" 1
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "alu_reg,simple_alu_imm"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "alu_shift_op" 1
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "simple_alu_shift,alu_shift"))
(eq_attr "type" "extend,arlo_shift"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-register operand
@ -81,7 +81,7 @@
;; the execute stage.
(define_insn_reservation "alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1026ejs")
(eq_attr "type" "alu_shift_reg"))
(eq_attr "type" "arlo_shift_reg"))
"a_e*2,a_m,a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

6
gcc/config/arm/arm1136jfs.md
View File

@ -75,13 +75,13 @@
;; ALU operations with no shifted operand
(define_insn_reservation "11_alu_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "alu_reg,simple_alu_imm"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "11_alu_shift_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "simple_alu_shift,alu_shift"))
(eq_attr "type" "extend,arlo_shift"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-register operand
@ -90,7 +90,7 @@
;; the shift stage.
(define_insn_reservation "11_alu_shift_reg_op" 3
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "alu_shift_reg"))
(eq_attr "type" "arlo_shift_reg"))
"e_1*2,e_2,e_3,e_wb")
;; alu_ops can start sooner, if there is no shifter dependency

4
gcc/config/arm/arm926ejs.md
View File

@ -58,7 +58,7 @@
;; ALU operations with no shifted operand
(define_insn_reservation "9_alu_op" 1
(and (eq_attr "tune" "arm926ejs")
(eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift"))
"e,m,w")
;; ALU operations with a shift-by-register operand
@ -67,7 +67,7 @@
;; the execute stage.
(define_insn_reservation "9_alu_shift_reg_op" 2
(and (eq_attr "tune" "arm926ejs")
(eq_attr "type" "alu_shift_reg"))
(eq_attr "type" "arlo_shift_reg"))
"e*2,m,w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

6
gcc/config/arm/cortex-a15.md
View File

@ -61,14 +61,14 @@
;; Simple ALU without shift
(define_insn_reservation "cortex_a15_alu" 2
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "alu_reg,simple_alu_imm")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none")))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
(define_insn_reservation "cortex_a15_alu_shift" 3
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "simple_alu_shift,alu_shift")
(and (eq_attr "type" "extend,arlo_shift")
(eq_attr "neon_type" "none")))
"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
|(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
@ -76,7 +76,7 @@
;; ALU ops with register controlled shift
(define_insn_reservation "cortex_a15_alu_shift_reg" 3
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "alu_shift_reg")
(and (eq_attr "type" "arlo_shift_reg")
(eq_attr "neon_type" "none")))
"(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
|(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\

4
gcc/config/arm/cortex-a5.md
View File

@ -58,12 +58,12 @@
(define_insn_reservation "cortex_a5_alu" 2
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "alu_reg,simple_alu_imm"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_alu_shift" 2
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
"cortex_a5_ex1")
;; Forwarding path for unshifted operands.

4
gcc/config/arm/cortex-a53.md
View File

@ -67,12 +67,12 @@
(define_insn_reservation "cortex_a53_alu" 2
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "alu_reg,simple_alu_imm"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift" 2
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "alu_shift,alu_shift_reg"))
(eq_attr "type" "arlo_shift,arlo_shift_reg"))
"cortex_a53_slot_any")
;; Forwarding path for unshifted operands.

8
gcc/config/arm/cortex-a7.md
View File

@ -88,8 +88,8 @@
;; ALU instruction with an immediate operand can dual-issue.
(define_insn_reservation "cortex_a7_alu_imm" 2
(and (eq_attr "tune" "cortexa7")
(and (ior (eq_attr "type" "simple_alu_imm")
(ior (eq_attr "type" "simple_alu_shift")
(and (ior (eq_attr "type" "arlo_imm")
(ior (eq_attr "type" "extend")
(and (eq_attr "insn" "mov")
(not (eq_attr "length" "8")))))
(eq_attr "neon_type" "none")))
@ -99,13 +99,13 @@
;; with a younger immediate-based instruction.
(define_insn_reservation "cortex_a7_alu_reg" 2
(and (eq_attr "tune" "cortexa7")
(and (eq_attr "type" "alu_reg")
(and (eq_attr "type" "arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none")))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_alu_shift" 2
(and (eq_attr "tune" "cortexa7")
(and (eq_attr "type" "alu_shift,alu_shift_reg")
(and (eq_attr "type" "arlo_shift,arlo_shift_reg")
(eq_attr "neon_type" "none")))
"cortex_a7_ex1")

8
gcc/config/arm/cortex-a8.md
View File

@ -85,7 +85,7 @@
;; (source read in E2 and destination available at the end of that cycle).
(define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8")
(ior (and (and (eq_attr "type" "alu_reg,simple_alu_imm")
(ior (and (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none"))
(not (eq_attr "insn" "mov,mvn")))
(eq_attr "insn" "clz")))
@ -93,13 +93,13 @@
(define_insn_reservation "cortex_a8_alu_shift" 2
(and (eq_attr "tune" "cortexa8")
(and (eq_attr "type" "simple_alu_shift,alu_shift")
(and (eq_attr "type" "extend,arlo_shift")
(not (eq_attr "insn" "mov,mvn"))))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift_reg" 2
(and (eq_attr "tune" "cortexa8")
(and (eq_attr "type" "alu_shift_reg")
(and (eq_attr "type" "arlo_shift_reg")
(not (eq_attr "insn" "mov,mvn"))))
"cortex_a8_default")
@ -107,7 +107,7 @@
(define_insn_reservation "cortex_a8_mov" 1
(and (eq_attr "tune" "cortexa8")
(and (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,arlo_shift_reg")
(eq_attr "insn" "mov,mvn")))
"cortex_a8_default")

6
gcc/config/arm/cortex-a9.md
View File

@ -80,9 +80,9 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
;; which can go down E2 without any problem.
(define_insn_reservation "cortex_a9_dp" 2
(and (eq_attr "tune" "cortexa9")
(ior (and (eq_attr "type" "alu_reg,simple_alu_imm")
(ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "neon_type" "none"))
(and (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
(and (and (eq_attr "type" "arlo_shift_reg,extend,arlo_shift")
(eq_attr "insn" "mov"))
(eq_attr "neon_type" "none"))))
"cortex_a9_p0_default|cortex_a9_p1_default")
@ -90,7 +90,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
;; An instruction using the shifter will go down E1.
(define_insn_reservation "cortex_a9_dp_shift" 3
(and (eq_attr "tune" "cortexa9")
(and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
(and (eq_attr "type" "arlo_shift_reg,extend,arlo_shift")
(not (eq_attr "insn" "mov"))))
"cortex_a9_p0_shift | cortex_a9_p1_shift")

4
gcc/config/arm/cortex-m4.md
View File

@ -31,8 +31,8 @@
;; ALU and multiply is one cycle.
(define_insn_reservation "cortex_m4_alu" 1
(and (eq_attr "tune" "cortexm4")
(ior (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,\
alu_shift,alu_shift_reg")
(ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\
arlo_shift,arlo_shift_reg")
(ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes"))))
"cortex_m4_ex")

8
gcc/config/arm/cortex-r4.md
View File

@ -78,24 +78,24 @@
;; for the purposes of the dual-issue constraints above.
(define_insn_reservation "cortex_r4_alu" 2
(and (eq_attr "tune_cortexr4" "yes")
(and (eq_attr "type" "alu_reg,simple_alu_imm")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "insn" "mov"))))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_mov" 2
(and (eq_attr "tune_cortexr4" "yes")
(and (eq_attr "type" "alu_reg,simple_alu_imm")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "insn" "mov")))
"cortex_r4_mov")
(define_insn_reservation "cortex_r4_alu_shift" 2
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "simple_alu_shift,alu_shift"))
(eq_attr "type" "extend,arlo_shift"))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_alu_shift_reg" 2
(and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "alu_shift_reg"))
(eq_attr "type" "arlo_shift_reg"))
"cortex_r4_alu_shift_reg")
;; An ALU instruction followed by an ALU instruction with no early dep.

4
gcc/config/arm/fa526.md
View File

@ -62,12 +62,12 @@
;; ALU operations
(define_insn_reservation "526_alu_op" 1
(and (eq_attr "tune" "fa526")
(eq_attr "type" "alu_reg,simple_alu_imm"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"fa526_core")
(define_insn_reservation "526_alu_shift_op" 2
(and (eq_attr "tune" "fa526")
(eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
"fa526_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

2
gcc/config/arm/fa606te.md
View File

@ -62,7 +62,7 @@
;; ALU operations
(define_insn_reservation "606te_alu_op" 1
(and (eq_attr "tune" "fa606te")
(eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,arlo_shift_reg"))
"fa606te_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

4
gcc/config/arm/fa626te.md
View File

@ -68,12 +68,12 @@
;; ALU operations
(define_insn_reservation "626te_alu_op" 1
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "type" "alu_reg,simple_alu_imm"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"fa626te_core")
(define_insn_reservation "626te_alu_shift_op" 2
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
"fa626te_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

6
gcc/config/arm/fa726te.md
View File

@ -85,7 +85,7 @@
;; Other ALU instructions 2 cycles.
(define_insn_reservation "726te_alu_op" 1
(and (eq_attr "tune" "fa726te")
(and (eq_attr "type" "alu_reg,simple_alu_imm")
(and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "insn" "mov,mvn"))))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
@ -95,13 +95,13 @@
;; it takes 3 cycles.
(define_insn_reservation "726te_alu_shift_op" 3
(and (eq_attr "tune" "fa726te")
(and (eq_attr "type" "simple_alu_shift,alu_shift")
(and (eq_attr "type" "extend,arlo_shift")
(not (eq_attr "insn" "mov,mvn"))))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
(define_insn_reservation "726te_alu_shift_reg_op" 3
(and (eq_attr "tune" "fa726te")
(and (eq_attr "type" "alu_shift_reg")
(and (eq_attr "type" "arlo_shift_reg")
(not (eq_attr "insn" "mov,mvn"))))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

4
gcc/config/arm/fmp626.md
View File

@ -63,12 +63,12 @@
;; ALU operations
(define_insn_reservation "mp626_alu_op" 1
(and (eq_attr "tune" "fmp626")
(eq_attr "type" "alu_reg,simple_alu_imm"))
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
"fmp626_core")
(define_insn_reservation "mp626_alu_shift_op" 2
(and (eq_attr "tune" "fmp626")
(eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
(eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
"fmp626_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

16
gcc/config/arm/marvell-pj4.md
View File

@ -41,54 +41,54 @@
(define_insn_reservation "pj4_alu_e1" 1
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "simple_alu_imm,alu_reg")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "conds" "set"))
(eq_attr "insn" "mov,mvn"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_e1_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "simple_alu_imm,alu_reg")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "conds" "set")
(eq_attr "insn" "mov,mvn"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu" 1
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "simple_alu_imm,alu_reg")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(not (eq_attr "conds" "set"))
(not (eq_attr "insn" "mov,mvn")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "simple_alu_imm,alu_reg")
(eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
(eq_attr "conds" "set")
(not (eq_attr "insn" "mov,mvn")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend")
(not (eq_attr "conds" "set"))
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend")
(eq_attr "conds" "set")
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(not (eq_attr "conds" "set"))
(eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "conds" "set")
(eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
(eq_attr "type" "arlo_shift,arlo_shift_reg,extend"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_bypass 2 "pj4_alu_shift,pj4_shift"

4
gcc/config/arm/neon.md
View File

@ -61,7 +61,7 @@
}
}
[(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*")
(set_attr "type" "*,f_stored,*,f_loadd,*,*,alu_reg,load2,store2")
(set_attr "type" "*,f_stored,*,f_loadd,*,*,arlo_reg,load2,store2")
(set_attr "insn" "*,*,*,*,*,*,mov,*,*")
(set_attr "length" "4,4,4,4,4,4,8,8,8")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
@ -107,7 +107,7 @@
}
[(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\
neon_mrrc,neon_mcr_2_mcrr,*,*,*")
(set_attr "type" "*,*,*,*,*,*,alu_reg,load4,store4")
(set_attr "type" "*,*,*,*,*,*,arlo_reg,load4,store4")
(set_attr "insn" "*,*,*,*,*,*,mov,*,*")
(set_attr "length" "4,8,4,8,8,8,16,8,16")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")

20
gcc/config/arm/thumb2.md
View File

@ -35,7 +35,7 @@
"bic%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
(set_attr "type" "alu_shift")]
(set_attr "type" "arlo_shift")]
)
(define_insn_and_split "*thumb2_smaxsi3"
@ -283,7 +283,7 @@
ldr%?\\t%0, %1
str%?\\t%1, %0
str%?\\t%1, %0"
[(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,*,load1,load1,store1,store1")
[(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,*,load1,load1,store1,store1")
(set_attr "length" "2,4,2,4,4,4,4,4,4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
@ -336,7 +336,7 @@
"cmn%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
(set_attr "type" "alu_shift")]
(set_attr "type" "arlo_shift")]
)
(define_insn_and_split "*thumb2_mov_scc"
@ -815,7 +815,7 @@
"@
sxtb%?\\t%0, %1
ldr%(sb%)\\t%0, %1"
[(set_attr "type" "simple_alu_shift,load_byte")
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
@ -828,7 +828,7 @@
"@
uxth%?\\t%0, %1
ldr%(h%)\\t%0, %1"
[(set_attr "type" "simple_alu_shift,load_byte")
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
@ -841,7 +841,7 @@
"@
uxtb%(%)\\t%0, %1
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "type" "simple_alu_shift,load_byte")
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
@ -933,8 +933,8 @@
(set_attr "shift" "1")
(set_attr "length" "2")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(const_string "arlo_shift")
(const_string "arlo_shift_reg")))]
)
(define_insn "*thumb2_mov<mode>_shortim"
@ -1056,7 +1056,7 @@
"
[(set_attr "conds" "set")
(set_attr "length" "2,2,4,4")
(set_attr "type" "simple_alu_imm,*,simple_alu_imm,*")]
(set_attr "type" "arlo_imm,*,arlo_imm,*")]
)
(define_insn "*thumb2_mulsi_short"
@ -1180,7 +1180,7 @@
"orn%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
(set_attr "type" "alu_shift")]
(set_attr "type" "arlo_shift")]
)
(define_peephole2

2
gcc/config/arm/vfp.md
View File

@ -53,7 +53,7 @@
}
"
[(set_attr "predicable" "yes")
(set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "type" "*,*,arlo_imm,arlo_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
(set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
(set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
(set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")