i386.md (sse_mov?fcc*): New patterns and splitters.
* i386.md (sse_mov?fcc*): New patterns and splitters. * i386.c (ix86_expand_movcc): Work post-reload; recognize the SSE based conditional moves. From-SVN: r40133
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
2b04e52b0b
commit
0073023dde
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@ -1,3 +1,9 @@
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Wed Feb 28 19:28:06 CET 2001 Jan Hubicka <jh@suse.cz>
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* i386.md (sse_mov?fcc*): New patterns and splitters.
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* i386.c (ix86_expand_movcc): Work post-reload; recognize
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the SSE based conditional moves.
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Wed Feb 28 19:18:23 CET 2001 Jan Hubicka <jh@suse.cz>
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* i386.md (attribute mode): Add "TI".
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@ -6016,6 +6016,92 @@ ix86_expand_fp_movcc (operands)
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rtx tmp;
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rtx compare_op, second_test, bypass_test;
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/* For SF/DFmode conditional moves based on comparisons
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in same mode, we may want to use SSE min/max instructions. */
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if (((TARGET_SSE && GET_MODE (operands[0]) == SFmode)
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|| (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode))
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&& GET_MODE (ix86_compare_op0) == GET_MODE (operands[0])
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/* We may be called from the post-reload splitter. */
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&& (!REG_P (operands[0])
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|| SSE_REG_P (operands[0])
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|| REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
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{
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rtx op0 = ix86_compare_op0, op1 = ix86_compare_op1;
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code = GET_CODE (operands[1]);
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/* See if we have (cross) match between comparison operands and
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conditional move operands. */
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if (rtx_equal_p (operands[2], op1))
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{
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rtx tmp = op0;
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op0 = op1;
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op1 = tmp;
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code = reverse_condition_maybe_unordered (code);
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}
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if (rtx_equal_p (operands[2], op0) && rtx_equal_p (operands[3], op1))
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{
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/* Check for min operation. */
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if (code == LT)
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{
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operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
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if (memory_operand (op0, VOIDmode))
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op0 = force_reg (GET_MODE (operands[0]), op0);
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if (GET_MODE (operands[0]) == SFmode)
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emit_insn (gen_minsf3 (operands[0], op0, op1));
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else
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emit_insn (gen_mindf3 (operands[0], op0, op1));
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return 1;
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}
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/* Check for max operation. */
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if (code == GT)
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{
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operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
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if (memory_operand (op0, VOIDmode))
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op0 = force_reg (GET_MODE (operands[0]), op0);
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if (GET_MODE (operands[0]) == SFmode)
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emit_insn (gen_maxsf3 (operands[0], op0, op1));
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else
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emit_insn (gen_maxdf3 (operands[0], op0, op1));
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return 1;
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}
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}
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/* Manage condition to be sse_comparison_operator. In case we are
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in non-ieee mode, try to canonicalize the destination operand
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to be first in the comparison - this helps reload to avoid extra
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moves. */
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if (!sse_comparison_operator (operands[1], VOIDmode)
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|| (rtx_equal_p (operands[0], ix86_compare_op1) && !TARGET_IEEE_FP))
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{
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rtx tmp = ix86_compare_op0;
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ix86_compare_op0 = ix86_compare_op1;
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ix86_compare_op1 = tmp;
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operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
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VOIDmode, ix86_compare_op0,
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ix86_compare_op1);
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}
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/* Similary try to manage result to be first operand of conditional
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move. */
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if (rtx_equal_p (operands[0], operands[3]))
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{
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rtx tmp = operands[2];
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operands[2] = operands[3];
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operands[2] = tmp;
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operands[1] = gen_rtx_fmt_ee (reverse_condition_maybe_unordered
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(GET_CODE (operands[1])),
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VOIDmode, ix86_compare_op0,
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ix86_compare_op1);
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}
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if (GET_MODE (operands[0]) == SFmode)
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emit_insn (gen_sse_movsfcc (operands[0], operands[1],
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operands[2], operands[3],
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ix86_compare_op0, ix86_compare_op1));
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else
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emit_insn (gen_sse_movdfcc (operands[0], operands[1],
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operands[2], operands[3],
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ix86_compare_op0, ix86_compare_op1));
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return 1;
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}
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/* The floating point conditional move instructions don't directly
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support conditions resulting from a signed integer comparison. */
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@ -12481,6 +12481,210 @@
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(const_string "lea")))
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(set_attr "mode" "SI")])
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;; Placeholder for the conditional moves. This one is split eighter to SSE
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;; based moves emulation or to usual cmove sequence. Little bit unfortunate
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;; fact is that compares supported by the cmp??ss instructions are exactly
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;; swapped of those supported by cmove sequence.
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(define_insn "sse_movsfcc"
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[(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
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(if_then_else:SF (match_operator 1 "sse_comparison_operator"
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[(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
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(match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
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(match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
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(match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
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(clobber (match_scratch:SF 6 "=2,&5,X,X,X,X,X,X,X,X"))
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(clobber (reg:CC 17))]
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"TARGET_SSE
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&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
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"#")
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(define_insn "sse_movdfcc"
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[(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
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(if_then_else:DF (match_operator 1 "sse_comparison_operator"
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[(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
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(match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
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(match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
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(match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
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(clobber (match_scratch:DF 6 "=2,&5,X,X,X,X,X,X,X,X"))
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(clobber (reg:CC 17))]
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"TARGET_SSE2
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&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
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"#")
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;; For non-sse moves just expand the usual cmove sequence.
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(define_split
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[(set (match_operand 0 "register_operand" "")
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(if_then_else (match_operator 1 "comparison_operator"
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[(match_operand 4 "nonimmediate_operand" "")
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(match_operand 5 "register_operand" "")])
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(match_operand 2 "nonimmediate_operand" "")
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(match_operand 3 "nonimmediate_operand" "")))
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(clobber (match_operand 6 "" ""))
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(clobber (reg:CC 17))]
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"!SSE_REG_P (operands[0]) && reload_completed
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&& VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
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[(const_int 0)]
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"
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{
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ix86_compare_op0 = operands[5];
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ix86_compare_op1 = operands[4];
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operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
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VOIDmode, operands[5], operands[4]);
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ix86_expand_fp_movcc (operands);
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DONE;
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}")
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;; Split SSE based conditional move into seqence:
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;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
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;; and op2, op0 - zero op2 if comparison was false
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;; nand op0, op3 - load op3 to op0 if comparison was false
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;; or op2, op0 - get the non-zero one into the result.
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(define_split
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[(set (match_operand 0 "register_operand" "")
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(if_then_else (match_operator 1 "sse_comparison_operator"
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[(match_operand 4 "register_operand" "")
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(match_operand 5 "nonimmediate_operand" "")])
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(match_operand 2 "register_operand" "")
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(match_operand 3 "register_operand" "")))
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(clobber (match_dup 2))
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(clobber (reg:CC 17))]
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"SSE_REG_P (operands[0]) && reload_completed"
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[(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
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(set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
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(subreg:TI (match_dup 0) 0)))
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(set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 0) 0))
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(subreg:TI (match_dup 3) 0)))
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(set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
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(subreg:TI (match_dup 7) 0)))]
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"
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{
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PUT_MODE (operands[1], GET_MODE (operands[0]));
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if (rtx_equal_p (operands[0], operands[4]))
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operands[6] = operands[4], operands[7] = operands[2];
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else
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operands[6] = operands[2], operands[7] = operands[0];
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}")
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;; Special case of conditional move we can handle effectivly.
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;; Do not brother with the integer/floating point case, since these are
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;; bot considerably slower, unlike in the generic case.
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(define_insn "*sse_movsfcc_const0_1"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(if_then_else:SF (match_operator 1 "sse_comparison_operator"
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[(match_operand:SF 4 "register_operand" "0")
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(match_operand:SF 5 "nonimmediate_operand" "xm")])
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(match_operand:SF 2 "register_operand" "x")
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(match_operand:SF 3 "const0_operand" "X")))]
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"TARGET_SSE"
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"#")
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(define_insn "*sse_movsfcc_const0_2"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(if_then_else:SF (match_operator 1 "sse_comparison_operator"
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[(match_operand:SF 4 "register_operand" "0")
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(match_operand:SF 5 "nonimmediate_operand" "xm")])
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(match_operand:SF 2 "const0_operand" "x")
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(match_operand:SF 3 "register_operand" "X")))]
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"TARGET_SSE"
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"#")
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(define_insn "*sse_movsfcc_const0_3"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
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[(match_operand:SF 4 "nonimmediate_operand" "xm")
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(match_operand:SF 5 "register_operand" "0")])
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(match_operand:SF 2 "register_operand" "x")
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(match_operand:SF 3 "const0_operand" "X")))]
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"TARGET_SSE"
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"#")
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(define_insn "*sse_movsfcc_const0_4"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
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[(match_operand:SF 4 "nonimmediate_operand" "xm")
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(match_operand:SF 5 "register_operand" "0")])
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(match_operand:SF 2 "const0_operand" "x")
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(match_operand:SF 3 "register_operand" "X")))]
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"TARGET_SSE"
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"#")
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(define_insn "*sse_movdfcc_const0_1"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(if_then_else:SF (match_operator 1 "sse_comparison_operator"
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[(match_operand:SF 4 "register_operand" "0")
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(match_operand:SF 5 "nonimmediate_operand" "xm")])
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(match_operand:SF 2 "register_operand" "x")
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(match_operand:SF 3 "const0_operand" "X")))]
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"TARGET_SSE2"
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"#")
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(define_insn "*sse_movdfcc_const0_2"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(if_then_else:SF (match_operator 1 "sse_comparison_operator"
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[(match_operand:SF 4 "register_operand" "0")
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(match_operand:SF 5 "nonimmediate_operand" "xm")])
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(match_operand:SF 2 "const0_operand" "x")
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(match_operand:SF 3 "register_operand" "X")))]
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"TARGET_SSE2"
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"#")
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(define_insn "*sse_movdfcc_const0_3"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
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[(match_operand:SF 4 "nonimmediate_operand" "xm")
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(match_operand:SF 5 "register_operand" "0")])
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(match_operand:SF 2 "register_operand" "x")
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(match_operand:SF 3 "const0_operand" "X")))]
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"TARGET_SSE2"
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"#")
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(define_insn "*sse_movdfcc_const0_4"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
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[(match_operand:SF 4 "nonimmediate_operand" "xm")
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(match_operand:SF 5 "register_operand" "0")])
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(match_operand:SF 2 "const0_operand" "x")
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(match_operand:SF 3 "register_operand" "X")))]
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"TARGET_SSE2"
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"#")
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(define_split
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[(set (match_operand 0 "register_operand" "")
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(if_then_else (match_operator 1 "comparison_operator"
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[(match_operand 4 "register_operand" "")
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(match_operand 5 "nonimmediate_operand" "")])
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(match_operand 2 "nonmemory_operand" "")
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(match_operand 3 "nonmemory_operand" "")))]
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"SSE_REG_P (operands[0]) && reload_completed
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&& (const0_operand (operands[2], GET_MODE (operands[0]))
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|| const0_operand (operands[3], GET_MODE (operands[0])))"
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[(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
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(set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
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(subreg:TI (match_dup 7) 0)))]
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"
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{
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PUT_MODE (operands[1], GET_MODE (operands[0]));
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if (!sse_comparison_operator (operands[1], VOIDmode))
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{
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rtx tmp = operands[5];
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operands[5] = operands[4];
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operands[4] = tmp;
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PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
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}
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if (const0_operand (operands[2], GET_MODE (operands[0])))
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{
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operands[7] = operands[3];
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operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
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0));
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}
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else
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{
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operands[7] = operands[2];
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operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
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}
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}")
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(define_insn "allocate_stack_worker"
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[(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
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(set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
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