parent
0d920bbf1a
commit
0081a354a8
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@ -937,6 +937,7 @@
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}
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}
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else
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else
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FAIL;
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FAIL;
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if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
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if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
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{
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{
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operands[2] = force_reg (SImode, operands[2]);
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operands[2] = force_reg (SImode, operands[2]);
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@ -954,6 +955,7 @@
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DONE;
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DONE;
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}")
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}")
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;; AIX architecture-independent common-mode multiply (DImode),
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;; AIX architecture-independent common-mode multiply (DImode),
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;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
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;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
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;; R4; results in R3 and somtimes R4; link register always clobbered by bla
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;; R4; results in R3 and somtimes R4; link register always clobbered by bla
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@ -968,6 +970,7 @@
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(clobber (match_scratch:SI 0 "=l"))]
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(clobber (match_scratch:SI 0 "=l"))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __mulh")
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"bla __mulh")
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(define_insn "mull_call"
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(define_insn "mull_call"
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[(set (reg:DI 3)
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[(set (reg:DI 3)
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(mult:DI (sign_extend:DI (reg:SI 3))
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(mult:DI (sign_extend:DI (reg:SI 3))
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@ -976,6 +979,7 @@
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(clobber (reg:SI 0))]
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(clobber (reg:SI 0))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __mull")
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"bla __mull")
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(define_insn "divss_call"
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(define_insn "divss_call"
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[(set (reg:SI 3)
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[(set (reg:SI 3)
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(div:SI (reg:SI 3) (reg:SI 4)))
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(div:SI (reg:SI 3) (reg:SI 4)))
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@ -985,6 +989,7 @@
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(clobber (reg:SI 0))]
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(clobber (reg:SI 0))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __divss")
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"bla __divss")
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(define_insn "divus_call"
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(define_insn "divus_call"
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[(set (reg:SI 3)
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[(set (reg:SI 3)
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(udiv:SI (reg:SI 3) (reg:SI 4)))
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(udiv:SI (reg:SI 3) (reg:SI 4)))
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@ -994,12 +999,14 @@
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(clobber (reg:SI 0))]
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(clobber (reg:SI 0))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __divus")
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"bla __divus")
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(define_insn "quoss_call"
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(define_insn "quoss_call"
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[(set (reg:SI 3)
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[(set (reg:SI 3)
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(div:SI (reg:SI 3) (reg:SI 4)))
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(div:SI (reg:SI 3) (reg:SI 4)))
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(clobber (match_scratch:SI 0 "=l"))]
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(clobber (match_scratch:SI 0 "=l"))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __quoss")
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"bla __quoss")
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(define_insn "quous_call"
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(define_insn "quous_call"
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[(set (reg:SI 3)
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[(set (reg:SI 3)
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(udiv:SI (reg:SI 3) (reg:SI 4)))
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(udiv:SI (reg:SI 3) (reg:SI 4)))
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