* Fix typos. Remove trailing blanks. Fix coding style.
From-SVN: r195151
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
d0ad394c5e
commit
0089227267
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@ -1,3 +1,27 @@
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2013-01-14 Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr-stdint.h: Remove trailing blanks.
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* config/avr/avr-log.h: Same.
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* config/avr/avr-arch.h: Same.
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* config/avr/avr-devices.c: Same.
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* config/avr/avr-dimode.md: Same.
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* config/avr/predicates.md: Same.
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* config/avr/avr-c.c: Same. And fix typo.
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* config/avr/avr-protos.h: Same. And:
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(function_arg_regno_p): Rename to avr_function_arg_regno_p.
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(init_cumulative_args): Rename to avr_init_cumulative_args.
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(expand_prologue): Rename to avr_expand_prologue.
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(expand_epilogue): Rename to avr_expand_epilogue.
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(adjust_insn_length): Rename to avr_adjust_insn_length.
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(notice_update_cc): Rename to avr_notice_update_cc.
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(final_prescan_insn): Rename to avr_final_prescan_insn.
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* config/avr/avr.c: Same.
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* config/avr/avr.h: Same.
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* config/avr/avr.md: Remove trailing blanks.
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(prologue): Use avr_expand_prologue.
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(epilogue, sibcall_epilogue): Use avr_expand_epilogue.
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2013-01-14 Richard Biener <rguenther@suse.de>
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* tree-cfg.c (verify_expr_location, verify_expr_location_1,
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@ -74,7 +74,7 @@ struct base_arch_s
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/* This core has the RAMPD special function register
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and thus also the RAMPX, RAMPY and RAMPZ registers. */
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int have_rampd;
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/* Default start of data section address for architecture. */
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int default_data_section_start;
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@ -84,9 +84,9 @@ struct base_arch_s
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/* Architecture id to built-in define __AVR_ARCH__ (NULL -> no macro) */
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const char *const macro;
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/* Architecture name. */
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const char *const arch_name;
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const char *const arch_name;
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};
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@ -96,16 +96,16 @@ struct mcu_type_s
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{
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/* Device name. */
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const char *const name;
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/* Index in avr_arch_types[]. */
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enum avr_arch arch;
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enum avr_arch arch;
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/* Must lie outside user's namespace. NULL == no macro. */
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const char *const macro;
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/* Stack pointer have 8 bits width. */
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int short_sp;
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/* Some AVR devices have a core erratum when skipping a 2-word instruction.
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Skip instructions are: SBRC, SBRS, SBIC, SBIS, CPSE.
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Problems will occur with return address is IRQ executes during the
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@ -125,15 +125,15 @@ struct mcu_type_s
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/* Core Erratum: Must not skip 2-word instruction. */
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int errata_skip;
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/* Start of data section. */
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int data_section_start;
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/* Number of 64k segments in the flash. */
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int n_flash;
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/* Name of device library. */
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const char *const library_name;
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const char *const library_name;
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};
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/* Map architecture to its texinfo string. */
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@ -40,7 +40,7 @@ avr_register_target_pragmas (void)
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gcc_assert (ADDR_SPACE_GENERIC == ADDR_SPACE_RAM);
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/* Register address spaces. The order must be the same as in the respective
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enum from avr.h (or designated initialized must be used in avr.c). */
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enum from avr.h (or designated initializers must be used in avr.c). */
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for (i = 0; i < ADDR_SPACE_COUNT; i++)
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{
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@ -52,14 +52,14 @@ avr_register_target_pragmas (void)
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}
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/* Transorm LO into uppercase and write the result to UP.
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/* Transform LO into uppercase and write the result to UP.
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You must provide enough space for UP. Return UP. */
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static char*
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avr_toupper (char *up, const char *lo)
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{
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char *up0 = up;
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for (; *lo; lo++, up++)
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*up = TOUPPER (*lo);
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@ -67,7 +67,7 @@ avr_toupper (char *up, const char *lo)
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return up0;
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}
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/* Worker function for TARGET_CPU_CPP_BUILTINS. */
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static const char *const avr_builtin_name[] =
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@ -82,7 +82,7 @@ void
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avr_cpu_cpp_builtins (struct cpp_reader *pfile)
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{
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int i;
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builtin_define_std ("AVR");
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if (avr_current_arch->macro)
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@ -139,24 +139,24 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile)
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if (avr_current_device->errata_skip)
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{
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cpp_define (pfile, "__AVR_ERRATA_SKIP__");
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if (avr_current_arch->have_jmp_call)
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cpp_define (pfile, "__AVR_ERRATA_SKIP_JMP_CALL__");
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}
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cpp_define_formatted (pfile, "__AVR_SFR_OFFSET__=0x%x",
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avr_current_arch->sfr_offset);
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#ifdef WITH_AVRLIBC
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cpp_define (pfile, "__WITH_AVRLIBC__");
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#endif /* WITH_AVRLIBC */
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/* Define builtin macros so that the user can easily query if or if not
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non-generic address spaces (and which) are supported.
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/* Define builtin macros so that the user can easily query whether
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non-generic address spaces (and which) are supported or not.
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This is only supported for C. For C++, a language extension is needed
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(as mentioned in ISO/IEC DTR 18037; Annex F.2) which is not
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implemented in GCC up to now. */
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if (!strcmp (lang_hooks.name, "GNU C"))
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{
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for (i = 0; i < ADDR_SPACE_COUNT; i++)
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@ -174,8 +174,8 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile)
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}
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}
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/* Define builtin macros so that the user can easily query if or
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if not a specific builtin is available. */
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/* Define builtin macros so that the user can easily query whether or
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not a specific builtin is available. */
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for (i = 0; avr_builtin_name[i]; i++)
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{
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@ -35,7 +35,7 @@ avr_arch_types[] =
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/*
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A M J LM E E E X R d S S O A
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S U M PO L L I M A a t F ff r
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M L P MV P P J E M t a R s c
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M L P MV P P J E M t a R s c
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XW M M M G P a r e h
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X P A D t t ID */
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{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0x0060, 32, "1", "avr1" },
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@ -31,7 +31,7 @@
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;; The DImode insns are all straight forward -- except movdi. The approach
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;; of this implementation is to provide DImode insns without the burden of
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;; introducing movdi.
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;;
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;;
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;; The caveat is that if there are insns for some mode, there must also be a
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;; respective move insn that describes reloads. Therefore, this
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;; implementation uses an accumulator-based model with two hard-coded,
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@ -75,7 +75,7 @@
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{
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emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
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emit_insn (gen_adddi3_const8_insn ());
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}
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}
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else if (const_operand (operands[2], GET_MODE (operands[2])))
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{
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emit_insn (gen_add<mode>3_const_insn (operands[2]));
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@ -344,7 +344,7 @@
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{
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emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
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emit_insn (gen_compare_const8_di2 ());
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}
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}
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else if (const_operand (operands[2], GET_MODE (operands[2])))
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{
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emit_insn (gen_compare_const_<mode>2 (operands[2]));
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@ -41,8 +41,8 @@
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avr_edump (fmt, ...) is a shortcut for avr_fdump (stderr, fmt, ...)
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== known %-codes ==
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b: bool
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b: bool
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r: rtx
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t: tree
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T: tree (brief)
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@ -55,7 +55,7 @@
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H: location_t
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== no arguments ==
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A: call abort()
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f: current_function_name()
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F: caller (via __FUNCTION__)
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@ -65,7 +65,7 @@
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else return.
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== same as printf ==
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%: %
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c: char
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s: string
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@ -95,11 +95,11 @@ static int
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avr_log_fdump_e (const char *fmt, ...)
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{
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va_list ap;
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va_start (ap, fmt);
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avr_log_vadump (stderr, fmt, ap);
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va_end (ap);
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return 1;
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}
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@ -107,12 +107,12 @@ static int
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avr_log_fdump_f (FILE *stream, const char *fmt, ...)
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{
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va_list ap;
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va_start (ap, fmt);
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if (stream)
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avr_log_vadump (stream, fmt, ap);
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va_end (ap);
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return 1;
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}
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@ -124,7 +124,7 @@ avr_log_set_caller_e (const char *caller)
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)(const char*, ...)
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{
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avr_log_caller = caller;
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return avr_log_fdump_e;
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}
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@ -192,19 +192,19 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
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default:
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fputc (*(fmt-1), file);
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break;
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case '\\':
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bs[1] = *fmt++;
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fputs (bs, file);
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break;
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case '%':
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switch (*fmt++)
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{
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case '%':
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fputc ('%', file);
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break;
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case 't':
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{
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tree t = va_arg (ap, tree);
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@ -222,15 +222,15 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
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}
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break;
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}
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case 'T':
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print_node_brief (file, "", va_arg (ap, tree), 3);
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break;
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case 'd':
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fprintf (file, "%d", va_arg (ap, int));
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break;
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case 'D':
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dump_double_int (file, va_arg (ap, double_int), false);
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break;
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@ -238,23 +238,23 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
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case 'X':
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avr_dump_double_int_hex (file, va_arg (ap, double_int));
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break;
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case 'x':
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fprintf (file, "%x", va_arg (ap, int));
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break;
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case 'b':
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fprintf (file, "%s", va_arg (ap, int) ? "true" : "false");
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break;
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case 'c':
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fputc (va_arg (ap, int), file);
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break;
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case 'r':
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print_inline_rtx (file, va_arg (ap, rtx), 0);
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break;
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case 'L':
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{
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rtx insn = va_arg (ap, rtx);
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@ -267,39 +267,40 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
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}
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break;
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}
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case 'f':
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if (cfun && cfun->decl)
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fputs (current_function_name(), file);
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break;
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case 's':
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{
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const char *str = va_arg (ap, char*);
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fputs (str ? str : "(null)", file);
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}
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break;
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case 'm':
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fputs (GET_MODE_NAME ((enum machine_mode) va_arg (ap, int)), file);
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fputs (GET_MODE_NAME ((enum machine_mode) va_arg (ap, int)),
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file);
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break;
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case 'C':
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fputs (rtx_name[va_arg (ap, int)], file);
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break;
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case 'R':
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fputs (reg_class_names[va_arg (ap, int)], file);
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break;
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case 'F':
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fputs (avr_log_caller, file);
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break;
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case 'H':
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{
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location_t loc = va_arg (ap, location_t);
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if (BUILTINS_LOCATION == loc)
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fprintf (file, "<BUILTIN-LOCATION>");
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else if (UNKNOWN_LOCATION == loc)
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@ -307,45 +308,45 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
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else
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fprintf (file, "%s:%d",
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LOCATION_FILE (loc), LOCATION_LINE (loc));
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break;
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}
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case '!':
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if (!current_pass)
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return;
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/* FALLTHRU */
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case '?':
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avr_log_fdump_f (file, "%F[%f:%P]");
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break;
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case 'P':
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if (current_pass)
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fprintf (file, "%s(%d)",
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fprintf (file, "%s(%d)",
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current_pass->name,
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current_pass->static_pass_number);
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else
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fprintf (file, "pass=?");
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break;
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case 'A':
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fflush (file);
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abort();
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default:
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/* Unknown %-code: Stop printing */
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fprintf (file, "??? %%%c ???%s\n", *(fmt-1), fmt);
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fmt = "";
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break;
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}
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break; /* % */
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}
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}
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fflush (file);
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}
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@ -357,14 +358,14 @@ void
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avr_log_set_avr_log (void)
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{
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bool all = TARGET_ALL_DEBUG != 0;
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if (all || avr_log_details)
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{
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/* Adding , at beginning and end of string makes searching easier. */
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char *str = (char*) alloca (3 + strlen (avr_log_details));
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bool info;
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str[0] = ',';
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strcat (stpcpy (str+1, avr_log_details), ",");
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|
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@ -20,11 +20,11 @@
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<http://www.gnu.org/licenses/>. */
|
||||
|
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|
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extern int function_arg_regno_p (int r);
|
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extern int avr_function_arg_regno_p (int r);
|
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extern void avr_cpu_cpp_builtins (struct cpp_reader * pfile);
|
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extern enum reg_class avr_regno_reg_class (int r);
|
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extern void asm_globalize_label (FILE *file, const char *name);
|
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extern void order_regs_for_local_alloc (void);
|
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extern void avr_adjust_reg_alloc_order (void);
|
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extern int avr_initial_elimination_offset (int from, int to);
|
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extern int avr_simple_epilogue (void);
|
||||
extern int avr_hard_regno_rename_ok (unsigned int, unsigned int);
|
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|
|
@ -38,8 +38,7 @@ extern void asm_output_external (FILE *file, tree decl, char *name);
|
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extern int avr_progmem_p (tree decl, tree attributes);
|
||||
|
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#ifdef RTX_CODE /* inside TREE_CODE */
|
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extern void init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
|
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rtx libname, tree fndecl);
|
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extern void avr_init_cumulative_args (CUMULATIVE_ARGS*, tree, rtx, tree);
|
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#endif /* RTX_CODE inside TREE_CODE */
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|
||||
#endif /* TREE_CODE */
|
||||
|
|
@ -78,8 +77,8 @@ extern bool avr_rotate_bytes (rtx operands[]);
|
|||
extern const char* avr_out_fract (rtx, rtx[], bool, int*);
|
||||
extern rtx avr_to_int_mode (rtx);
|
||||
|
||||
extern void expand_prologue (void);
|
||||
extern void expand_epilogue (bool);
|
||||
extern void avr_expand_prologue (void);
|
||||
extern void avr_expand_epilogue (bool);
|
||||
extern bool avr_emit_movmemhi (rtx*);
|
||||
extern int avr_epilogue_uses (int regno);
|
||||
extern int avr_starting_frame_offset (void);
|
||||
|
|
@ -96,12 +95,12 @@ extern bool avr_popcount_each_byte (rtx, int, int);
|
|||
extern bool avr_has_nibble_0xf (rtx);
|
||||
|
||||
extern int extra_constraint_Q (rtx x);
|
||||
extern int adjust_insn_length (rtx insn, int len);
|
||||
extern int avr_adjust_insn_length (rtx insn, int len);
|
||||
extern const char* output_reload_inhi (rtx*, rtx, int*);
|
||||
extern const char* output_reload_insisf (rtx*, rtx, int*);
|
||||
extern const char* avr_out_reload_inpsi (rtx*, rtx, int*);
|
||||
extern const char* avr_out_lpm (rtx, rtx*, int*);
|
||||
extern void notice_update_cc (rtx body, rtx insn);
|
||||
extern void avr_notice_update_cc (rtx body, rtx insn);
|
||||
extern int reg_unused_after (rtx insn, rtx reg);
|
||||
extern int _reg_unused_after (rtx insn, rtx reg);
|
||||
extern int avr_jump_mode (rtx x, rtx insn);
|
||||
|
|
@ -109,7 +108,7 @@ extern int test_hard_reg_class (enum reg_class rclass, rtx x);
|
|||
extern int jump_over_one_insn_p (rtx insn, rtx dest);
|
||||
|
||||
extern int avr_hard_regno_mode_ok (int regno, enum machine_mode mode);
|
||||
extern void final_prescan_insn (rtx insn, rtx *operand, int num_operands);
|
||||
extern void avr_final_prescan_insn (rtx insn, rtx *operand, int num_operands);
|
||||
extern int avr_simplify_comparison_p (enum machine_mode mode,
|
||||
RTX_CODE op, rtx x);
|
||||
extern RTX_CODE avr_normalize_condition (RTX_CODE condition);
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ along with GCC; see the file COPYING3. If not see
|
|||
- For the same reason, [u]int_fast8_t is defined as 8-bit type.
|
||||
|
||||
*/
|
||||
|
||||
|
||||
#define SIG_ATOMIC_TYPE "char"
|
||||
|
||||
#define INT8_TYPE "signed char"
|
||||
|
|
|
|||
1486
gcc/config/avr/avr.c
1486
gcc/config/avr/avr.c
File diff suppressed because it is too large
Load Diff
|
|
@ -201,10 +201,11 @@ enum
|
|||
32,33,34,35 \
|
||||
}
|
||||
|
||||
#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
|
||||
#define ADJUST_REG_ALLOC_ORDER avr_adjust_reg_alloc_order()
|
||||
|
||||
|
||||
#define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
||||
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
||||
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
||||
|
||||
#define HARD_REGNO_MODE_OK(REGNO, MODE) avr_hard_regno_mode_ok(REGNO, MODE)
|
||||
|
||||
|
|
@ -318,15 +319,19 @@ enum reg_class {
|
|||
for POST_DEC targets (PR27386). */
|
||||
/*#define PUSH_ROUNDING(NPUSHED) (NPUSHED)*/
|
||||
|
||||
typedef struct avr_args {
|
||||
int nregs; /* # registers available for passing */
|
||||
int regno; /* next available register number */
|
||||
typedef struct avr_args
|
||||
{
|
||||
/* # Registers available for passing */
|
||||
int nregs;
|
||||
|
||||
/* Next available register number */
|
||||
int regno;
|
||||
} CUMULATIVE_ARGS;
|
||||
|
||||
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
|
||||
init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL)
|
||||
avr_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL)
|
||||
|
||||
#define FUNCTION_ARG_REGNO_P(r) function_arg_regno_p(r)
|
||||
#define FUNCTION_ARG_REGNO_P(r) avr_function_arg_regno_p(r)
|
||||
|
||||
#define DEFAULT_PCC_STRUCT_RETURN 0
|
||||
|
||||
|
|
@ -415,7 +420,8 @@ typedef struct avr_args {
|
|||
"r24","r25","r26","r27","r28","r29","r30","r31", \
|
||||
"__SP_L__","__SP_H__","argL","argH"}
|
||||
|
||||
#define FINAL_PRESCAN_INSN(insn, operand, nop) final_prescan_insn (insn, operand,nop)
|
||||
#define FINAL_PRESCAN_INSN(insn, operand, nop) \
|
||||
avr_final_prescan_insn (insn, operand,nop)
|
||||
|
||||
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
|
||||
{ \
|
||||
|
|
@ -429,8 +435,8 @@ typedef struct avr_args {
|
|||
fprintf (STREAM, "\tpop\tr%d", REGNO); \
|
||||
}
|
||||
|
||||
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
|
||||
avr_output_addr_vec_elt(STREAM, VALUE)
|
||||
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
|
||||
avr_output_addr_vec_elt (STREAM, VALUE)
|
||||
|
||||
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
|
||||
do { \
|
||||
|
|
@ -459,7 +465,7 @@ typedef struct avr_args {
|
|||
after execution of an instruction whose pattern is EXP.
|
||||
Do not alter them if the instruction would not alter the cc's. */
|
||||
|
||||
#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
|
||||
#define NOTICE_UPDATE_CC(EXP, INSN) avr_notice_update_cc (EXP, INSN)
|
||||
|
||||
/* The add insns don't set overflow in a usable way. */
|
||||
#define CC_OVERFLOW_UNUSABLE 01000
|
||||
|
|
@ -477,8 +483,8 @@ typedef struct avr_args {
|
|||
#define FUNCTION_PROFILER(FILE, LABELNO) \
|
||||
fprintf (FILE, "/* profiler %d */", (LABELNO))
|
||||
|
||||
#define ADJUST_INSN_LENGTH(INSN, LENGTH) (LENGTH =\
|
||||
adjust_insn_length (INSN, LENGTH))
|
||||
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
|
||||
(LENGTH = avr_adjust_insn_length (INSN, LENGTH))
|
||||
|
||||
extern const char *avr_device_to_arch (int argc, const char **argv);
|
||||
extern const char *avr_device_to_data_start (int argc, const char **argv);
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@
|
|||
UNSPECV_WDR
|
||||
UNSPECV_DELAY_CYCLES
|
||||
])
|
||||
|
||||
|
||||
|
||||
(include "predicates.md")
|
||||
(include "constraints.md")
|
||||
|
|
@ -166,7 +166,7 @@
|
|||
(define_attr "enabled" ""
|
||||
(cond [(eq_attr "isa" "standard")
|
||||
(const_int 1)
|
||||
|
||||
|
||||
(and (eq_attr "isa" "mov")
|
||||
(match_test "!AVR_HAVE_MOVW"))
|
||||
(const_int 1)
|
||||
|
|
@ -174,7 +174,7 @@
|
|||
(and (eq_attr "isa" "movw")
|
||||
(match_test "AVR_HAVE_MOVW"))
|
||||
(const_int 1)
|
||||
|
||||
|
||||
(and (eq_attr "isa" "rjmp")
|
||||
(match_test "!AVR_HAVE_JMP_CALL"))
|
||||
(const_int 1)
|
||||
|
|
@ -182,7 +182,7 @@
|
|||
(and (eq_attr "isa" "jmp")
|
||||
(match_test "AVR_HAVE_JMP_CALL"))
|
||||
(const_int 1)
|
||||
|
||||
|
||||
(and (eq_attr "isa" "ijmp")
|
||||
(match_test "!AVR_HAVE_EIJMP_EICALL"))
|
||||
(const_int 1)
|
||||
|
|
@ -295,12 +295,12 @@
|
|||
;; The code derived from builtins.c.
|
||||
|
||||
(define_expand "nonlocal_goto_receiver"
|
||||
[(set (reg:HI REG_Y)
|
||||
[(set (reg:HI REG_Y)
|
||||
(unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
|
||||
""
|
||||
{
|
||||
emit_move_insn (virtual_stack_vars_rtx,
|
||||
gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
|
||||
emit_move_insn (virtual_stack_vars_rtx,
|
||||
gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
|
||||
gen_int_mode (STARTING_FRAME_OFFSET,
|
||||
Pmode)));
|
||||
/* ; This might change the hard frame pointer in ways that aren't
|
||||
|
|
@ -308,7 +308,7 @@
|
|||
emit_clobber (hard_frame_pointer_rtx);
|
||||
DONE;
|
||||
})
|
||||
|
||||
|
||||
|
||||
;; Defining nonlocal_goto_receiver means we must also define this.
|
||||
;; even though its function is identical to that in builtins.c
|
||||
|
|
@ -335,7 +335,7 @@
|
|||
emit_use (stack_pointer_rtx);
|
||||
|
||||
emit_indirect_jump (r_label);
|
||||
|
||||
|
||||
DONE;
|
||||
})
|
||||
|
||||
|
|
@ -410,9 +410,9 @@
|
|||
|
||||
;; "loadqi_libgcc"
|
||||
;; "loadhi_libgcc"
|
||||
;; "loadpsi_libgcc"
|
||||
;; "loadsi_libgcc"
|
||||
;; "loadsf_libgcc"
|
||||
;; "loadpsi_libgcc"
|
||||
;; "loadsi_libgcc"
|
||||
;; "loadsf_libgcc"
|
||||
(define_expand "load<mode>_libgcc"
|
||||
[(set (match_dup 3)
|
||||
(match_dup 2))
|
||||
|
|
@ -430,9 +430,9 @@
|
|||
|
||||
;; "load_qi_libgcc"
|
||||
;; "load_hi_libgcc"
|
||||
;; "load_psi_libgcc"
|
||||
;; "load_si_libgcc"
|
||||
;; "load_sf_libgcc"
|
||||
;; "load_psi_libgcc"
|
||||
;; "load_si_libgcc"
|
||||
;; "load_sf_libgcc"
|
||||
(define_insn "load_<mode>_libgcc"
|
||||
[(set (reg:MOVMODE 22)
|
||||
(match_operand:MOVMODE 0 "memory_operand" "m,m"))]
|
||||
|
|
@ -573,11 +573,11 @@
|
|||
""
|
||||
{
|
||||
rtx dest = operands[0];
|
||||
rtx src = operands[1];
|
||||
|
||||
rtx src = operands[1];
|
||||
|
||||
if (avr_mem_flash_p (dest))
|
||||
DONE;
|
||||
|
||||
|
||||
/* One of the operands has to be in a register. */
|
||||
if (!register_operand (dest, <MODE>mode)
|
||||
&& !reg_or_0_operand (src, <MODE>mode))
|
||||
|
|
@ -757,7 +757,7 @@
|
|||
operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
|
||||
})
|
||||
|
||||
;; For LPM loads from AS1 we split
|
||||
;; For LPM loads from AS1 we split
|
||||
;; R = *Z
|
||||
;; to
|
||||
;; R = *Z++
|
||||
|
|
@ -793,7 +793,7 @@
|
|||
|
||||
;;==========================================================================
|
||||
;; xpointer move (24 bit)
|
||||
|
||||
|
||||
(define_peephole2 ; *reload_inpsi
|
||||
[(match_scratch:QI 2 "d")
|
||||
(set (match_operand:PSI 0 "l_register_operand" "")
|
||||
|
|
@ -804,7 +804,7 @@
|
|||
[(parallel [(set (match_dup 0)
|
||||
(match_dup 1))
|
||||
(clobber (match_dup 2))])])
|
||||
|
||||
|
||||
;; '*' because it is not used in rtl generation.
|
||||
(define_insn "*reload_inpsi"
|
||||
[(set (match_operand:PSI 0 "register_operand" "=r")
|
||||
|
|
@ -830,7 +830,7 @@
|
|||
[(set_attr "length" "3,3,8,9,4,10")
|
||||
(set_attr "adjust_len" "mov24")
|
||||
(set_attr "cc" "none,none,clobber,clobber,none,clobber")])
|
||||
|
||||
|
||||
;;==========================================================================
|
||||
;; move double word (32 bit)
|
||||
|
||||
|
|
@ -897,7 +897,7 @@
|
|||
(match_operand:SF 1 "const_double_operand" ""))
|
||||
(match_dup 2)]
|
||||
"operands[1] != CONST0_RTX (SFmode)"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(parallel [(set (match_dup 0)
|
||||
(match_dup 1))
|
||||
(clobber (match_dup 2))])])
|
||||
|
||||
|
|
@ -926,7 +926,7 @@
|
|||
{
|
||||
if (avr_emit_movmemhi (operands))
|
||||
DONE;
|
||||
|
||||
|
||||
FAIL;
|
||||
})
|
||||
|
||||
|
|
@ -1062,7 +1062,7 @@
|
|||
if (operands[2] != const0_rtx)
|
||||
FAIL;
|
||||
addr = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
|
||||
operands[1] = gen_rtx_MEM (BLKmode, addr);
|
||||
operands[1] = gen_rtx_MEM (BLKmode, addr);
|
||||
operands[5] = addr;
|
||||
operands[4] = gen_reg_rtx (HImode);
|
||||
})
|
||||
|
|
@ -1495,7 +1495,7 @@
|
|||
clr __zero_reg__"
|
||||
[(set_attr "length" "3")
|
||||
(set_attr "cc" "clobber")])
|
||||
|
||||
|
||||
|
||||
;; Used when expanding div or mod inline for some special values
|
||||
(define_insn "*subqi3.ashiftrt7"
|
||||
|
|
@ -1563,7 +1563,7 @@
|
|||
"%~call __umulqihi3"
|
||||
[(set_attr "type" "xcall")
|
||||
(set_attr "cc" "clobber")])
|
||||
|
||||
|
||||
;; "umulqihi3"
|
||||
;; "mulqihi3"
|
||||
(define_insn "<extend_u>mulqihi3"
|
||||
|
|
@ -1637,7 +1637,7 @@
|
|||
(plus:QI (mult:QI (match_operand:QI 1 "register_operand" "r")
|
||||
(match_operand:QI 2 "register_operand" "r"))
|
||||
(match_operand:QI 3 "register_operand" "0")))]
|
||||
|
||||
|
||||
"AVR_HAVE_MUL"
|
||||
"mul %1,%2
|
||||
add %A0,r0
|
||||
|
|
@ -1718,7 +1718,7 @@
|
|||
(plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
|
||||
(any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
|
||||
(match_operand:HI 3 "register_operand" "0")))]
|
||||
|
||||
|
||||
"AVR_HAVE_MUL"
|
||||
"mul<extend_s> %1,%2
|
||||
add %A0,r0
|
||||
|
|
@ -2163,7 +2163,7 @@
|
|||
if (u8_operand (operands[2], HImode))
|
||||
{
|
||||
emit_insn (gen_muluqihi3 (operands[0], reg, operands[1]));
|
||||
}
|
||||
}
|
||||
else if (s8_operand (operands[2], HImode))
|
||||
{
|
||||
emit_insn (gen_mulsqihi3 (operands[0], reg, operands[1]));
|
||||
|
|
@ -2250,7 +2250,7 @@
|
|||
"&& 1"
|
||||
[(set (reg:SI 18)
|
||||
(match_dup 1))
|
||||
(set (reg:SI 22)
|
||||
(set (reg:SI 22)
|
||||
(match_dup 2))
|
||||
(parallel [(set (reg:SI 22)
|
||||
(mult:SI (reg:SI 22)
|
||||
|
|
@ -2297,7 +2297,7 @@
|
|||
{
|
||||
/* Do the QI -> HI extension explicitely before the multiplication. */
|
||||
/* Do the HI -> SI extension implicitely and after the multiplication. */
|
||||
|
||||
|
||||
if (QImode == <MODE>mode)
|
||||
operands[1] = gen_rtx_ZERO_EXTEND (HImode, operands[1]);
|
||||
|
||||
|
|
@ -2333,7 +2333,7 @@
|
|||
{
|
||||
/* Do the QI -> HI extension explicitely before the multiplication. */
|
||||
/* Do the HI -> SI extension implicitely and after the multiplication. */
|
||||
|
||||
|
||||
if (QImode == <MODE>mode)
|
||||
operands[1] = gen_rtx_SIGN_EXTEND (HImode, operands[1]);
|
||||
|
||||
|
|
@ -2357,7 +2357,7 @@
|
|||
|
||||
(define_insn_and_split "mulohisi3"
|
||||
[(set (match_operand:SI 0 "pseudo_register_operand" "=r")
|
||||
(mult:SI (not:SI (zero_extend:SI
|
||||
(mult:SI (not:SI (zero_extend:SI
|
||||
(not:HI (match_operand:HI 1 "pseudo_register_operand" "r"))))
|
||||
(match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
|
||||
(clobber (reg:HI 26))
|
||||
|
|
@ -2422,7 +2422,7 @@
|
|||
|
||||
/* Do the QI -> HI extension explicitely before the multiplication. */
|
||||
/* Do the HI -> SI extension implicitely and after the multiplication. */
|
||||
|
||||
|
||||
if (QImode == <QIHI:MODE>mode)
|
||||
xop1 = gen_rtx_fmt_e (<any_extend:CODE>, HImode, xop1);
|
||||
|
||||
|
|
@ -2536,16 +2536,16 @@
|
|||
;; - we get both the quotient and the remainder at no extra cost
|
||||
;; - we split the patterns only after the first CSE passes because
|
||||
;; CSE has problems to operate on hard regs.
|
||||
;;
|
||||
;;
|
||||
(define_insn_and_split "divmodqi4"
|
||||
[(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
|
||||
(div:QI (match_operand:QI 1 "pseudo_register_operand" "")
|
||||
[(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
|
||||
(div:QI (match_operand:QI 1 "pseudo_register_operand" "")
|
||||
(match_operand:QI 2 "pseudo_register_operand" "")))
|
||||
(set (match_operand:QI 3 "pseudo_register_operand" "")
|
||||
(set (match_operand:QI 3 "pseudo_register_operand" "")
|
||||
(mod:QI (match_dup 1) (match_dup 2)))
|
||||
(clobber (reg:QI 22))
|
||||
(clobber (reg:QI 23))
|
||||
(clobber (reg:QI 24))
|
||||
(clobber (reg:QI 22))
|
||||
(clobber (reg:QI 23))
|
||||
(clobber (reg:QI 24))
|
||||
(clobber (reg:QI 25))])]
|
||||
""
|
||||
"this divmodqi4 pattern should have been splitted;"
|
||||
|
|
@ -2570,10 +2570,10 @@
|
|||
(set_attr "cc" "clobber")])
|
||||
|
||||
(define_insn_and_split "udivmodqi4"
|
||||
[(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
|
||||
(udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
|
||||
[(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
|
||||
(udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
|
||||
(match_operand:QI 2 "pseudo_register_operand" "")))
|
||||
(set (match_operand:QI 3 "pseudo_register_operand" "")
|
||||
(set (match_operand:QI 3 "pseudo_register_operand" "")
|
||||
(umod:QI (match_dup 1) (match_dup 2)))
|
||||
(clobber (reg:QI 22))
|
||||
(clobber (reg:QI 23))
|
||||
|
|
@ -2581,7 +2581,7 @@
|
|||
(clobber (reg:QI 25))])]
|
||||
""
|
||||
"this udivmodqi4 pattern should have been splitted;"
|
||||
""
|
||||
""
|
||||
[(set (reg:QI 24) (match_dup 1))
|
||||
(set (reg:QI 22) (match_dup 2))
|
||||
(parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
|
||||
|
|
@ -2600,10 +2600,10 @@
|
|||
(set_attr "cc" "clobber")])
|
||||
|
||||
(define_insn_and_split "divmodhi4"
|
||||
[(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
|
||||
(div:HI (match_operand:HI 1 "pseudo_register_operand" "")
|
||||
[(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
|
||||
(div:HI (match_operand:HI 1 "pseudo_register_operand" "")
|
||||
(match_operand:HI 2 "pseudo_register_operand" "")))
|
||||
(set (match_operand:HI 3 "pseudo_register_operand" "")
|
||||
(set (match_operand:HI 3 "pseudo_register_operand" "")
|
||||
(mod:HI (match_dup 1) (match_dup 2)))
|
||||
(clobber (reg:QI 21))
|
||||
(clobber (reg:HI 22))
|
||||
|
|
@ -2632,10 +2632,10 @@
|
|||
(set_attr "cc" "clobber")])
|
||||
|
||||
(define_insn_and_split "udivmodhi4"
|
||||
[(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
|
||||
[(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
|
||||
(udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
|
||||
(match_operand:HI 2 "pseudo_register_operand" "")))
|
||||
(set (match_operand:HI 3 "pseudo_register_operand" "")
|
||||
(set (match_operand:HI 3 "pseudo_register_operand" "")
|
||||
(umod:HI (match_dup 1) (match_dup 2)))
|
||||
(clobber (reg:QI 21))
|
||||
(clobber (reg:HI 22))
|
||||
|
|
@ -2748,7 +2748,7 @@
|
|||
"&& 1"
|
||||
[(set (reg:PSI 18)
|
||||
(match_dup 1))
|
||||
(set (reg:PSI 22)
|
||||
(set (reg:PSI 22)
|
||||
(match_dup 2))
|
||||
(parallel [(set (reg:PSI 22)
|
||||
(mult:PSI (reg:PSI 22)
|
||||
|
|
@ -2864,17 +2864,17 @@
|
|||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
(define_insn_and_split "divmodsi4"
|
||||
[(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
|
||||
(div:SI (match_operand:SI 1 "pseudo_register_operand" "")
|
||||
[(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
|
||||
(div:SI (match_operand:SI 1 "pseudo_register_operand" "")
|
||||
(match_operand:SI 2 "pseudo_register_operand" "")))
|
||||
(set (match_operand:SI 3 "pseudo_register_operand" "")
|
||||
(set (match_operand:SI 3 "pseudo_register_operand" "")
|
||||
(mod:SI (match_dup 1) (match_dup 2)))
|
||||
(clobber (reg:SI 18))
|
||||
(clobber (reg:SI 22))
|
||||
(clobber (reg:HI 26))
|
||||
(clobber (reg:HI 30))])]
|
||||
""
|
||||
"this divmodsi4 pattern should have been splitted;"
|
||||
"this divmodsi4 pattern should have been splitted;"
|
||||
""
|
||||
[(set (reg:SI 22) (match_dup 1))
|
||||
(set (reg:SI 18) (match_dup 2))
|
||||
|
|
@ -2896,10 +2896,10 @@
|
|||
(set_attr "cc" "clobber")])
|
||||
|
||||
(define_insn_and_split "udivmodsi4"
|
||||
[(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
|
||||
(udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
|
||||
[(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
|
||||
(udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
|
||||
(match_operand:SI 2 "pseudo_register_operand" "")))
|
||||
(set (match_operand:SI 3 "pseudo_register_operand" "")
|
||||
(set (match_operand:SI 3 "pseudo_register_operand" "")
|
||||
(umod:SI (match_dup 1) (match_dup 2)))
|
||||
(clobber (reg:SI 18))
|
||||
(clobber (reg:SI 22))
|
||||
|
|
@ -3206,7 +3206,7 @@
|
|||
FAIL;
|
||||
|
||||
offset = INTVAL (operands[2]);
|
||||
|
||||
|
||||
if (0 == offset % 8)
|
||||
{
|
||||
if (AVR_HAVE_MOVW && 0 == offset % 16)
|
||||
|
|
@ -3614,7 +3614,7 @@
|
|||
if (IN_RANGE (INTVAL (operands[2]), 3, 6))
|
||||
{
|
||||
rtx xoffset = force_reg (QImode, gen_int_mode (1 << INTVAL (operands[2]), QImode));
|
||||
emit_insn (gen_mulsqipsi3 (operands[0], xoffset, operands[1]));
|
||||
emit_insn (gen_mulsqipsi3 (operands[0], xoffset, operands[1]));
|
||||
DONE;
|
||||
}
|
||||
else if (optimize_insn_for_speed_p ()
|
||||
|
|
@ -3622,7 +3622,7 @@
|
|||
&& IN_RANGE (INTVAL (operands[2]), 9, 22))
|
||||
{
|
||||
rtx xoffset = force_reg (PSImode, gen_int_mode (1 << INTVAL (operands[2]), PSImode));
|
||||
emit_insn (gen_mulpsi3 (operands[0], operands[1], xoffset));
|
||||
emit_insn (gen_mulpsi3 (operands[0], operands[1], xoffset));
|
||||
DONE;
|
||||
}
|
||||
}
|
||||
|
|
@ -4447,7 +4447,7 @@
|
|||
case 0:
|
||||
case 1:
|
||||
return avr_out_tsthi (insn, operands, NULL);
|
||||
|
||||
|
||||
case 2:
|
||||
return "cp %A0,%A1\;cpc %B0,%B1";
|
||||
|
||||
|
|
@ -4457,15 +4457,15 @@
|
|||
return reg_unused_after (insn, operands[0])
|
||||
? "subi %A0,lo8(%1)\;sbci %B0,hi8(%1)"
|
||||
: "ldi %2,hi8(%1)\;cpi %A0,lo8(%1)\;cpc %B0,%2";
|
||||
|
||||
|
||||
case 4:
|
||||
if (<MODE>mode != HImode)
|
||||
break;
|
||||
return "ldi %2,lo8(%1)\;cp %A0,%2\;ldi %2,hi8(%1)\;cpc %B0,%2";
|
||||
}
|
||||
|
||||
|
||||
return avr_out_compare (insn, operands, NULL);
|
||||
}
|
||||
}
|
||||
[(set_attr "cc" "compare")
|
||||
(set_attr "length" "1,2,2,3,4,2,4")
|
||||
(set_attr "adjust_len" "tsthi,tsthi,*,*,*,compare,compare")])
|
||||
|
|
@ -4489,11 +4489,11 @@
|
|||
return reg_unused_after (insn, operands[0])
|
||||
? "subi %A0,lo8(%1)\;sbci %B0,hi8(%1)\;sbci %C0,hh8(%1)"
|
||||
: "cpi %A0,lo8(%1)\;ldi %2,hi8(%1)\;cpc %B0,%2\;ldi %2,hh8(%1)\;cpc %C0,%2";
|
||||
|
||||
|
||||
case 3:
|
||||
return "ldi %2,lo8(%1)\;cp %A0,%2\;ldi %2,hi8(%1)\;cpc %B0,%2\;ldi %2,hh8(%1)\;cpc %C0,%2";
|
||||
}
|
||||
|
||||
|
||||
return avr_out_compare (insn, operands, NULL);
|
||||
}
|
||||
[(set_attr "cc" "compare")
|
||||
|
|
@ -4514,7 +4514,7 @@
|
|||
return avr_out_tstsi (insn, operands, NULL);
|
||||
else if (1 == which_alternative)
|
||||
return "cp %A0,%A1\;cpc %B0,%B1\;cpc %C0,%C1\;cpc %D0,%D1";
|
||||
|
||||
|
||||
return avr_out_compare (insn, operands, NULL);
|
||||
}
|
||||
[(set_attr "cc" "compare")
|
||||
|
|
@ -4758,7 +4758,7 @@
|
|||
|
||||
(define_insn "rvbranch"
|
||||
[(set (pc)
|
||||
(if_then_else (match_operator 1 "simple_comparison_operator"
|
||||
(if_then_else (match_operator 1 "simple_comparison_operator"
|
||||
[(cc0)
|
||||
(const_int 0)])
|
||||
(pc)
|
||||
|
|
@ -4772,7 +4772,7 @@
|
|||
|
||||
(define_insn "difficult_rvbranch"
|
||||
[(set (pc)
|
||||
(if_then_else (match_operator 1 "difficult_comparison_operator"
|
||||
(if_then_else (match_operator 1 "difficult_comparison_operator"
|
||||
[(cc0)
|
||||
(const_int 0)])
|
||||
(pc)
|
||||
|
|
@ -4940,7 +4940,7 @@
|
|||
(compare (match_dup 6)
|
||||
(match_operand:HI 2 "register_operand" "")))
|
||||
(clobber (match_scratch:QI 9 ""))])
|
||||
|
||||
|
||||
(set (pc)
|
||||
(if_then_else (gtu (cc0)
|
||||
(const_int 0))
|
||||
|
|
@ -5317,13 +5317,13 @@
|
|||
;;
|
||||
;; Notice that the peephole is always shorter than cmpqi + branch.
|
||||
;; The reason to write it as peephole is that sequences like
|
||||
;;
|
||||
;;
|
||||
;; AND Rm, Rn
|
||||
;; BRNE .La
|
||||
;;
|
||||
;; shall not be superseeded. With a respective combine pattern
|
||||
;; the latter sequence would be
|
||||
;;
|
||||
;; the latter sequence would be
|
||||
;;
|
||||
;; AND Rm, Rn
|
||||
;; CPSE Rm, __zero_reg__
|
||||
;; RJMP .La
|
||||
|
|
@ -5412,7 +5412,7 @@
|
|||
[(set_attr "length" "5,6")
|
||||
(set_attr "cc" "clobber")
|
||||
(set_attr "isa" "rjmp,jmp")])
|
||||
|
||||
|
||||
; epilogue restores using library
|
||||
(define_insn "epilogue_restores"
|
||||
[(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
|
||||
|
|
@ -5429,7 +5429,7 @@
|
|||
[(set_attr "length" "2,3")
|
||||
(set_attr "cc" "clobber")
|
||||
(set_attr "isa" "rjmp,jmp")])
|
||||
|
||||
|
||||
; return
|
||||
(define_insn "return"
|
||||
[(return)]
|
||||
|
|
@ -5440,8 +5440,8 @@
|
|||
|
||||
(define_insn "return_from_epilogue"
|
||||
[(return)]
|
||||
"reload_completed
|
||||
&& cfun->machine
|
||||
"reload_completed
|
||||
&& cfun->machine
|
||||
&& !(cfun->machine->is_interrupt || cfun->machine->is_signal)
|
||||
&& !cfun->machine->is_naked"
|
||||
"ret"
|
||||
|
|
@ -5450,8 +5450,8 @@
|
|||
|
||||
(define_insn "return_from_interrupt_epilogue"
|
||||
[(return)]
|
||||
"reload_completed
|
||||
&& cfun->machine
|
||||
"reload_completed
|
||||
&& cfun->machine
|
||||
&& (cfun->machine->is_interrupt || cfun->machine->is_signal)
|
||||
&& !cfun->machine->is_naked"
|
||||
"reti"
|
||||
|
|
@ -5460,8 +5460,8 @@
|
|||
|
||||
(define_insn "return_from_naked_epilogue"
|
||||
[(return)]
|
||||
"reload_completed
|
||||
&& cfun->machine
|
||||
"reload_completed
|
||||
&& cfun->machine
|
||||
&& cfun->machine->is_naked"
|
||||
""
|
||||
[(set_attr "cc" "none")
|
||||
|
|
@ -5471,7 +5471,7 @@
|
|||
[(const_int 0)]
|
||||
""
|
||||
{
|
||||
expand_prologue ();
|
||||
avr_expand_prologue ();
|
||||
DONE;
|
||||
})
|
||||
|
||||
|
|
@ -5479,7 +5479,7 @@
|
|||
[(const_int 0)]
|
||||
""
|
||||
{
|
||||
expand_epilogue (false /* sibcall_p */);
|
||||
avr_expand_epilogue (false /* sibcall_p */);
|
||||
DONE;
|
||||
})
|
||||
|
||||
|
|
@ -5487,7 +5487,7 @@
|
|||
[(const_int 0)]
|
||||
""
|
||||
{
|
||||
expand_epilogue (true /* sibcall_p */);
|
||||
avr_expand_epilogue (true /* sibcall_p */);
|
||||
DONE;
|
||||
})
|
||||
|
||||
|
|
@ -5915,7 +5915,7 @@
|
|||
"bst %D2,7\;bld %D0,7"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "none")])
|
||||
|
||||
|
||||
;; Swap Bytes (change byte-endianess)
|
||||
|
||||
(define_expand "bswapsi2"
|
||||
|
|
@ -5937,9 +5937,9 @@
|
|||
|
||||
;; CPU instructions
|
||||
|
||||
;; NOP taking 1 or 2 Ticks
|
||||
;; NOP taking 1 or 2 Ticks
|
||||
(define_expand "nopv"
|
||||
[(parallel [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")]
|
||||
[(parallel [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")]
|
||||
UNSPECV_NOP)
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:BLK [(match_dup 1)]
|
||||
|
|
@ -5951,7 +5951,7 @@
|
|||
})
|
||||
|
||||
(define_insn "*nopv"
|
||||
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "P,K")]
|
||||
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "P,K")]
|
||||
UNSPECV_NOP)
|
||||
(set (match_operand:BLK 1 "" "")
|
||||
(unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))]
|
||||
|
|
@ -5982,7 +5982,7 @@
|
|||
"sleep"
|
||||
[(set_attr "length" "1")
|
||||
(set_attr "cc" "none")])
|
||||
|
||||
|
||||
;; WDR
|
||||
(define_expand "wdr"
|
||||
[(parallel [(unspec_volatile [(const_int 0)] UNSPECV_WDR)
|
||||
|
|
@ -6003,7 +6003,7 @@
|
|||
"wdr"
|
||||
[(set_attr "length" "1")
|
||||
(set_attr "cc" "none")])
|
||||
|
||||
|
||||
;; FMUL
|
||||
(define_expand "fmul"
|
||||
[(set (reg:QI 24)
|
||||
|
|
@ -6330,7 +6330,7 @@
|
|||
|
||||
(define_insn_and_split "*extzv.qihi2"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
(zero_extend:HI
|
||||
(zero_extend:HI
|
||||
(zero_extract:QI (match_operand:QI 1 "register_operand" "r")
|
||||
(const_int 1)
|
||||
(match_operand:QI 2 "const_0_to_7_operand" "n"))))]
|
||||
|
|
|
|||
|
|
@ -162,11 +162,11 @@
|
|||
;; True for EQ & NE
|
||||
(define_predicate "eqne_operator"
|
||||
(match_code "eq,ne"))
|
||||
|
||||
|
||||
;; True for GE & LT
|
||||
(define_predicate "gelt_operator"
|
||||
(match_code "ge,lt"))
|
||||
|
||||
|
||||
;; True for GT, GTU, LE & LEU
|
||||
(define_predicate "difficult_comparison_operator"
|
||||
(match_code "gt,gtu,le,leu"))
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
|
||||
|
||||
* config/avr/lib1funcs.S: Remove trailing blanks.
|
||||
* config/avr/lib1funcs-fixed.S: Ditto.
|
||||
|
||||
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
|
||||
|
||||
* config/avr/avr-lib.h: Add GPL copyright notice.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* -*- Mode: Asm -*- */
|
||||
;; Copyright (C) 2012
|
||||
;; Copyright (C) 2012-2013
|
||||
;; Free Software Foundation, Inc.
|
||||
;; Contributed by Sean D'Epagnier (sean@depagnier.com)
|
||||
;; Georg-Johann Lay (avr@gjlay.de)
|
||||
|
|
@ -163,7 +163,7 @@ ENDF __fractusasf
|
|||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; Conversions from float
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
|
||||
#if defined (L_fractsfqq)
|
||||
DEFUN __fractsfqq
|
||||
;; Multiply with 2^{24+7} to get a QQ result in r25
|
||||
|
|
@ -408,14 +408,14 @@ DEFUN __mulusa3_round
|
|||
|
||||
mul A1, B0 $ add C3, r0 $ adc C0, r1
|
||||
mul A0, B1 $ add C3, r0 $ adc C0, r1 $ rol C1
|
||||
|
||||
|
||||
;; Round if T = 1. Store guarding bits outside the result for rounding
|
||||
;; and left-shift by the signed version (function below).
|
||||
brtc 0f
|
||||
sbrc C3, 7
|
||||
adiw C0, 1
|
||||
0: push C3
|
||||
|
||||
|
||||
;; The following MULs don't have LSBs outside the result.
|
||||
;; C2/C3 is the high part.
|
||||
|
||||
|
|
@ -429,11 +429,11 @@ DEFUN __mulusa3_round
|
|||
mul A2, B1 $ add C1, r0 $ adc C2, r1 $ sbci C3, 0
|
||||
mul A3, B0 $ add C1, r0 $ adc C2, r1 $ sbci C3, 0
|
||||
neg C3
|
||||
|
||||
|
||||
mul A1, B3 $ add C2, r0 $ adc C3, r1
|
||||
mul A2, B2 $ add C2, r0 $ adc C3, r1
|
||||
mul A3, B1 $ add C2, r0 $ adc C3, r1
|
||||
|
||||
|
||||
mul A2, B3 $ add C3, r0
|
||||
mul A3, B2 $ add C3, r0
|
||||
|
||||
|
|
@ -636,7 +636,7 @@ DEFUN __mulusa3_round
|
|||
adc C1, __zero_reg__
|
||||
adc C2, __zero_reg__
|
||||
adc C3, __zero_reg__
|
||||
6:
|
||||
6:
|
||||
pop GUARD
|
||||
;; Epilogue
|
||||
pop CC3
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* -*- Mode: Asm -*- */
|
||||
/* Copyright (C) 1998, 1999, 2000, 2007, 2008, 2009
|
||||
/* Copyright (C) 1998-2013
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Denis Chertykov <chertykov@gmail.com>
|
||||
|
||||
|
|
@ -151,16 +151,16 @@ __mulqi3_loop:
|
|||
add r_res,r_arg2
|
||||
add r_arg2,r_arg2 ; shift multiplicand
|
||||
breq __mulqi3_exit ; while multiplicand != 0
|
||||
lsr r_arg1 ;
|
||||
lsr r_arg1 ;
|
||||
brne __mulqi3_loop ; exit if multiplier = 0
|
||||
__mulqi3_exit:
|
||||
mov r_arg1,r_res ; result to return register
|
||||
ret
|
||||
ENDF __mulqi3
|
||||
|
||||
#undef r_arg2
|
||||
#undef r_arg1
|
||||
#undef r_res
|
||||
#undef r_arg2
|
||||
#undef r_arg1
|
||||
#undef r_res
|
||||
|
||||
#endif /* defined (L_mulqi3) */
|
||||
|
||||
|
|
@ -370,7 +370,7 @@ DEFUN __mulsi3_helper
|
|||
|
||||
2: ;; B <<= 1
|
||||
lsl B0 $ rol B1 $ rol B2 $ rol B3
|
||||
|
||||
|
||||
3: ;; A >>= 1: Carry = n-th bit of A
|
||||
lsr A3 $ ror A2 $ ror A1 $ ror A0
|
||||
|
||||
|
|
@ -409,7 +409,7 @@ ENDF __mulsi3_helper
|
|||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
#if defined (__AVR_HAVE_MUL__)
|
||||
#if defined (__AVR_HAVE_MUL__)
|
||||
#define A0 26
|
||||
#define B0 18
|
||||
#define C0 22
|
||||
|
|
@ -427,7 +427,7 @@ ENDF __mulsi3_helper
|
|||
/*******************************************************
|
||||
Widening Multiplication 32 = 16 x 16 with MUL
|
||||
*******************************************************/
|
||||
|
||||
|
||||
#if defined (L_mulhisi3)
|
||||
;;; R25:R22 = (signed long) R27:R26 * (signed long) R19:R18
|
||||
;;; C3:C0 = (signed long) A1:A0 * (signed long) B1:B0
|
||||
|
|
@ -512,7 +512,7 @@ DEFUN __mulshisi3
|
|||
XJMP __muluhisi3
|
||||
;; FALLTHRU
|
||||
ENDF __mulshisi3
|
||||
|
||||
|
||||
;;; R25:R22 = (one-extended long) R27:R26 * R21:R18
|
||||
;;; (C3:C0) = (one-extended long) A1:A0 * B3:B0
|
||||
;;; Clobbers: __tmp_reg__
|
||||
|
|
@ -647,23 +647,23 @@ DEFUN __mulpsi3
|
|||
;; C[] = 0
|
||||
clr __tmp_reg__
|
||||
clr C2
|
||||
|
||||
|
||||
0: ;; Shift N-th Bit of B[] into Carry. N = 24 - Loop
|
||||
LSR B2 $ ror B1 $ ror B0
|
||||
|
||||
|
||||
;; If the N-th Bit of B[] was set...
|
||||
brcc 1f
|
||||
|
||||
|
||||
;; ...then add A[] * 2^N to the Result C[]
|
||||
ADD C0,A0 $ adc C1,A1 $ adc C2,A2
|
||||
|
||||
|
||||
1: ;; Multiply A[] by 2
|
||||
LSL A0 $ rol A1 $ rol A2
|
||||
|
||||
|
||||
;; Loop until B[] is 0
|
||||
subi B0,0 $ sbci B1,0 $ sbci B2,0
|
||||
brne 0b
|
||||
|
||||
|
||||
;; Copy C[] to the return Register A[]
|
||||
wmov A0, C0
|
||||
mov A2, C2
|
||||
|
|
@ -1002,7 +1002,7 @@ __udivmodqi4_ep:
|
|||
rol r_arg1 ; shift dividend (with CARRY)
|
||||
dec r_cnt ; decrement loop counter
|
||||
brne __udivmodqi4_loop
|
||||
com r_arg1 ; complement result
|
||||
com r_arg1 ; complement result
|
||||
; because C flag was complemented in loop
|
||||
ret
|
||||
ENDF __udivmodqi4
|
||||
|
|
@ -1112,14 +1112,14 @@ __divmodhi4_exit:
|
|||
ENDF __divmodhi4
|
||||
#endif /* defined (L_divmodhi4) */
|
||||
|
||||
#undef r_remH
|
||||
#undef r_remL
|
||||
|
||||
#undef r_arg1H
|
||||
#undef r_arg1L
|
||||
|
||||
#undef r_arg2H
|
||||
#undef r_arg2L
|
||||
#undef r_remH
|
||||
#undef r_remL
|
||||
|
||||
#undef r_arg1H
|
||||
#undef r_arg1L
|
||||
|
||||
#undef r_arg2H
|
||||
#undef r_arg2L
|
||||
|
||||
#undef r_cnt
|
||||
|
||||
|
|
@ -1501,8 +1501,8 @@ DEFUN __udivmod64
|
|||
|
||||
1: ;; Compare shifted Devidend against Divisor
|
||||
;; If -- even after Shifting -- it is smaller...
|
||||
CP A7,B0 $ cpc C0,B1 $ cpc C1,B2 $ cpc C2,B3
|
||||
cpc C3,B4 $ cpc C4,B5 $ cpc C5,B6 $ cpc C6,B7
|
||||
CP A7,B0 $ cpc C0,B1 $ cpc C1,B2 $ cpc C2,B3
|
||||
cpc C3,B4 $ cpc C4,B5 $ cpc C5,B6 $ cpc C6,B7
|
||||
brcc 2f
|
||||
|
||||
;; ...then we can subtract it. Thus, it is legal to shift left
|
||||
|
|
@ -1596,7 +1596,7 @@ DEFUN __udivmod64
|
|||
|
||||
ENDF __udivmod64
|
||||
#endif /* L_udivmod64 */
|
||||
|
||||
|
||||
|
||||
#if defined (L_divdi3)
|
||||
|
||||
|
|
@ -1622,7 +1622,7 @@ DEFUN __divdi3_moddi3
|
|||
brmi 0f
|
||||
;; Both Signs are 0: the following Complexitiy is not needed
|
||||
XJMP __udivdi3_umoddi3
|
||||
#endif /* SPEED_DIV */
|
||||
#endif /* SPEED_DIV */
|
||||
|
||||
0: ;; The Prologue
|
||||
;; Save 12 Registers: Y, 17...8
|
||||
|
|
@ -1645,7 +1645,7 @@ DEFUN __divdi3_moddi3
|
|||
#else
|
||||
brpl 21f
|
||||
#endif /* SPEED_DIV */
|
||||
|
||||
|
||||
XCALL __negdi2
|
||||
|
||||
;; Adjust Divisor's Sign and SS.7 as needed
|
||||
|
|
@ -1809,7 +1809,7 @@ ENDF __negdi2
|
|||
|
||||
|
||||
.section .text.libgcc.prologue, "ax", @progbits
|
||||
|
||||
|
||||
/**********************************
|
||||
* This is a prologue subroutine
|
||||
**********************************/
|
||||
|
|
@ -1944,7 +1944,7 @@ _cleanup:
|
|||
|
||||
|
||||
.section .text.libgcc, "ax", @progbits
|
||||
|
||||
|
||||
#ifdef L_tablejump
|
||||
DEFUN __tablejump2__
|
||||
lsl r30
|
||||
|
|
@ -2146,7 +2146,7 @@ ENDF __do_global_dtors
|
|||
#endif /* L_dtors */
|
||||
|
||||
.section .text.libgcc, "ax", @progbits
|
||||
|
||||
|
||||
#ifdef L_tablejump_elpm
|
||||
DEFUN __tablejump_elpm__
|
||||
#if defined (__AVR_HAVE_ELPMX__)
|
||||
|
|
@ -2484,7 +2484,7 @@ DEFUN __loop_ffsqi2
|
|||
brcc __loop_ffsqi2
|
||||
mov r24, r26
|
||||
clr r25
|
||||
ret
|
||||
ret
|
||||
ENDF __loop_ffsqi2
|
||||
#endif /* defined (L_loop_ffsqi2) */
|
||||
|
||||
|
|
@ -2586,7 +2586,7 @@ ENDF __clzhi2
|
|||
|
||||
|
||||
/**********************************
|
||||
* Parity
|
||||
* Parity
|
||||
**********************************/
|
||||
|
||||
#if defined (L_paritydi2)
|
||||
|
|
@ -2702,20 +2702,20 @@ ENDF __popcountdi2
|
|||
DEFUN __popcountqi2
|
||||
mov __tmp_reg__, r24
|
||||
andi r24, 1
|
||||
lsr __tmp_reg__
|
||||
lsr __tmp_reg__
|
||||
lsr __tmp_reg__
|
||||
lsr __tmp_reg__
|
||||
adc r24, __zero_reg__
|
||||
lsr __tmp_reg__
|
||||
lsr __tmp_reg__
|
||||
adc r24, __zero_reg__
|
||||
lsr __tmp_reg__
|
||||
lsr __tmp_reg__
|
||||
adc r24, __zero_reg__
|
||||
lsr __tmp_reg__
|
||||
lsr __tmp_reg__
|
||||
adc r24, __zero_reg__
|
||||
lsr __tmp_reg__
|
||||
lsr __tmp_reg__
|
||||
adc r24, __zero_reg__
|
||||
lsr __tmp_reg__
|
||||
adc r24, __tmp_reg__
|
||||
ret
|
||||
lsr __tmp_reg__
|
||||
adc r24, __tmp_reg__
|
||||
ret
|
||||
ENDF __popcountqi2
|
||||
#endif /* defined (L_popcountqi2) */
|
||||
|
||||
|
|
@ -2850,10 +2850,10 @@ ENDF __rotldi3
|
|||
|
||||
.section .text.libgcc.fmul, "ax", @progbits
|
||||
|
||||
/***********************************************************/
|
||||
/***********************************************************/
|
||||
;;; Softmul versions of FMUL, FMULS and FMULSU to implement
|
||||
;;; __builtin_avr_fmul* if !AVR_HAVE_MUL
|
||||
/***********************************************************/
|
||||
/***********************************************************/
|
||||
|
||||
#define A1 24
|
||||
#define B1 25
|
||||
|
|
|
|||
Loading…
Reference in New Issue