(all floating point): If -msoft-float, don't allow any
floating point builtin operations. From-SVN: r6689
This commit is contained in:
parent
97f57b11d4
commit
009cf8e010
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@ -277,61 +277,61 @@
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(define_insn "fix_truncsfsi2"
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(define_insn "fix_truncsfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(fix:SI (match_operand:SF 1 "register_operand" "r")))]
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(fix:SI (match_operand:SF 1 "register_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,0,3,0,1")
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"convert %0,%1,0,3,0,1")
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(define_insn "fix_truncdfsi2"
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(define_insn "fix_truncdfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(fix:SI (match_operand:DF 1 "register_operand" "r")))]
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(fix:SI (match_operand:DF 1 "register_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,0,3,0,2")
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"convert %0,%1,0,3,0,2")
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(define_insn "fixuns_truncsfsi2"
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(define_insn "fixuns_truncsfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
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(unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,1,3,0,1")
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"convert %0,%1,1,3,0,1")
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(define_insn "fixuns_truncdfsi2"
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(define_insn "fixuns_truncdfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
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(unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,1,3,0,2")
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"convert %0,%1,1,3,0,2")
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(define_insn "truncdfsf2"
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(define_insn "truncdfsf2"
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[(set (match_operand:SF 0 "register_operand" "=r")
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[(set (match_operand:SF 0 "register_operand" "=r")
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(float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
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(float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,0,4,1,2")
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"convert %0,%1,0,4,1,2")
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(define_insn "extendsfdf2"
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(define_insn "extendsfdf2"
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[(set (match_operand:DF 0 "register_operand" "=r")
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[(set (match_operand:DF 0 "register_operand" "=r")
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(float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
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(float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,0,4,2,1")
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"convert %0,%1,0,4,2,1")
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(define_insn "floatsisf2"
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(define_insn "floatsisf2"
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[(set (match_operand:SF 0 "register_operand" "=r")
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[(set (match_operand:SF 0 "register_operand" "=r")
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(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,0,4,1,0")
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"convert %0,%1,0,4,1,0")
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(define_insn "floatsidf2"
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(define_insn "floatsidf2"
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[(set (match_operand:DF 0 "register_operand" "=r")
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[(set (match_operand:DF 0 "register_operand" "=r")
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(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,0,4,2,0")
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"convert %0,%1,0,4,2,0")
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(define_insn "floatunssisf2"
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(define_insn "floatunssisf2"
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[(set (match_operand:SF 0 "register_operand" "=r")
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[(set (match_operand:SF 0 "register_operand" "=r")
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(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,1,4,1,0")
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"convert %0,%1,1,4,1,0")
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(define_insn "floatunssidf2"
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(define_insn "floatunssidf2"
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[(set (match_operand:DF 0 "register_operand" "=r")
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[(set (match_operand:DF 0 "register_operand" "=r")
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(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"convert %0,%1,1,4,2,0")
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"convert %0,%1,1,4,2,0")
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;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE
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;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE
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@ -348,7 +348,7 @@
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(match_operator 3 "fp_comparison_operator"
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(match_operator 3 "fp_comparison_operator"
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[(match_operand:SF 1 "register_operand" "r")
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[(match_operand:SF 1 "register_operand" "r")
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(match_operand:SF 2 "register_operand" "r")]))]
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(match_operand:SF 2 "register_operand" "r")]))]
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""
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"! TARGET_SOFT_FLOAT"
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"f%J3 %0,%1,%2"
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"f%J3 %0,%1,%2"
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[(set_attr "type" "fadd")])
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[(set_attr "type" "fadd")])
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@ -357,7 +357,7 @@
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(match_operator 3 "fp_comparison_operator"
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(match_operator 3 "fp_comparison_operator"
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[(match_operand:DF 1 "register_operand" "r")
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[(match_operand:DF 1 "register_operand" "r")
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(match_operand:DF 2 "register_operand" "r")]))]
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(match_operand:DF 2 "register_operand" "r")]))]
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""
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"! TARGET_SOFT_FLOAT"
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"d%J3 %0,%1,%2"
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"d%J3 %0,%1,%2"
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[(set_attr "type" "fadd")])
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[(set_attr "type" "fadd")])
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@ -366,7 +366,7 @@
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[(set (match_operand:DF 0 "register_operand" "")
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[(set (match_operand:DF 0 "register_operand" "")
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(plus:DF (match_operand:DF 1 "register_operand" "")
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(plus:DF (match_operand:DF 1 "register_operand" "")
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(match_operand:DF 2 "register_operand" "")))]
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(match_operand:DF 2 "register_operand" "")))]
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""
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"! TARGET_SOFT_FLOAT"
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"")
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"")
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(define_insn ""
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(define_insn ""
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@ -392,7 +392,7 @@
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[(set (match_operand:DF 0 "register_operand" "=r")
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[(set (match_operand:DF 0 "register_operand" "=r")
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(div:DF (match_operand:DF 1 "register_operand" "=r")
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(div:DF (match_operand:DF 1 "register_operand" "=r")
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(match_operand:DF 2 "register_operand" "r")))]
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(match_operand:DF 2 "register_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"ddiv %0,%1,%2"
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"ddiv %0,%1,%2"
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[(set_attr "type" "ddiv")])
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[(set_attr "type" "ddiv")])
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@ -535,7 +535,7 @@
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[(set (match_operand:DF 0 "register_operand" "")
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[(set (match_operand:DF 0 "register_operand" "")
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(mult:DF (match_operand:DF 1 "register_operand" "")
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(mult:DF (match_operand:DF 1 "register_operand" "")
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(match_operand:DF 2 "register_operand" "")))]
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(match_operand:DF 2 "register_operand" "")))]
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""
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"! TARGET_SOFT_FLOAT"
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"")
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"")
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(define_insn ""
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(define_insn ""
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@ -561,7 +561,7 @@
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[(set (match_operand:DF 0 "register_operand" "=r")
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[(set (match_operand:DF 0 "register_operand" "=r")
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(minus:DF (match_operand:DF 1 "register_operand" "r")
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(minus:DF (match_operand:DF 1 "register_operand" "r")
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(match_operand:DF 2 "register_operand" "r")))]
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(match_operand:DF 2 "register_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"")
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"")
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(define_insn ""
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(define_insn ""
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@ -731,7 +731,7 @@
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[(set (match_operand:SF 0 "register_operand" "")
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[(set (match_operand:SF 0 "register_operand" "")
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(plus:SF (match_operand:SF 1 "register_operand" "")
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(plus:SF (match_operand:SF 1 "register_operand" "")
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(match_operand:SF 2 "register_operand" "")))]
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(match_operand:SF 2 "register_operand" "")))]
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""
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"! TARGET_SOFT_FLOAT"
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"")
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"")
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(define_insn ""
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(define_insn ""
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@ -757,7 +757,7 @@
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[(set (match_operand:SF 0 "register_operand" "=r")
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[(set (match_operand:SF 0 "register_operand" "=r")
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(div:SF (match_operand:SF 1 "register_operand" "=r")
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(div:SF (match_operand:SF 1 "register_operand" "=r")
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(match_operand:SF 2 "register_operand" "r")))]
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(match_operand:SF 2 "register_operand" "r")))]
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""
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"! TARGET_SOFT_FLOAT"
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"fdiv %0,%1,%2"
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"fdiv %0,%1,%2"
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[(set_attr "type" "fdiv")])
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[(set_attr "type" "fdiv")])
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@ -766,7 +766,7 @@
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[(set (match_operand:DF 0 "register_operand" "=r")
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[(set (match_operand:DF 0 "register_operand" "=r")
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(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r"))
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(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r"))
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(float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
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(float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
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""
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"! TARGET_SOFT_FLOAT"
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"fdmul %0,%1,%2")
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"fdmul %0,%1,%2")
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;; FMAC/FMSM
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;; FMAC/FMSM
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@ -847,7 +847,7 @@
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[(set (match_operand:SF 0 "register_operand" "")
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[(set (match_operand:SF 0 "register_operand" "")
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(mult:SF (match_operand:SF 1 "register_operand" "")
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(mult:SF (match_operand:SF 1 "register_operand" "")
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(match_operand:SF 2 "register_operand" "")))]
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(match_operand:SF 2 "register_operand" "")))]
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""
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"! TARGET_SOFT_FLOAT"
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"")
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"")
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(define_insn ""
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(define_insn ""
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@ -873,7 +873,7 @@
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[(set (match_operand:SF 0 "register_operand" "")
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[(set (match_operand:SF 0 "register_operand" "")
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(minus:SF (match_operand:SF 1 "register_operand" "")
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(minus:SF (match_operand:SF 1 "register_operand" "")
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(match_operand:SF 2 "register_operand" "")))]
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(match_operand:SF 2 "register_operand" "")))]
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""
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"! TARGET_SOFT_FLOAT"
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"")
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"")
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(define_insn ""
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(define_insn ""
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@ -1531,7 +1531,7 @@
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[(parallel [(set (match_operand:SF 0 "register_operand" "")
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[(parallel [(set (match_operand:SF 0 "register_operand" "")
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(neg:SF (match_operand:SF 1 "register_operand" "")))
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(neg:SF (match_operand:SF 1 "register_operand" "")))
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(clobber (match_scratch:SI 2 ""))])]
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(clobber (match_scratch:SI 2 ""))])]
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""
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"! TARGET_SOFT_FLOAT"
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"
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"
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{
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{
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rtx result;
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rtx result;
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@ -1559,7 +1559,7 @@
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[(parallel [(set (match_operand:DF 0 "register_operand" "")
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[(parallel [(set (match_operand:DF 0 "register_operand" "")
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(neg:DF (match_operand:DF 1 "register_operand" "")))
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(neg:DF (match_operand:DF 1 "register_operand" "")))
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(clobber (match_scratch:SI 2 ""))])]
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(clobber (match_scratch:SI 2 ""))])]
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""
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"! TARGET_SOFT_FLOAT"
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"
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"
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{
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{
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rtx result;
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rtx result;
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@ -2430,7 +2430,7 @@
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[(set (cc0)
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[(set (cc0)
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(compare (match_operand:SF 0 "gpc_reg_operand" "")
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(compare (match_operand:SF 0 "gpc_reg_operand" "")
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(match_operand:SF 1 "gpc_reg_operand" "")))]
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(match_operand:SF 1 "gpc_reg_operand" "")))]
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""
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"! TARGET_SOFT_FLOAT"
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"
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"
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{
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{
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a29k_compare_op0 = operands[0];
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a29k_compare_op0 = operands[0];
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@ -2443,7 +2443,7 @@
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[(set (cc0)
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[(set (cc0)
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(compare (match_operand:DF 0 "gpc_reg_operand" "")
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(compare (match_operand:DF 0 "gpc_reg_operand" "")
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(match_operand:DF 1 "gpc_reg_operand" "")))]
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(match_operand:DF 1 "gpc_reg_operand" "")))]
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""
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"! TARGET_SOFT_FLOAT"
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"
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"
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{
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{
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a29k_compare_op0 = operands[0];
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a29k_compare_op0 = operands[0];
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@ -2663,7 +2663,7 @@
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(match_operand 2 "gpc_reg_operand" "")))
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(match_operand 2 "gpc_reg_operand" "")))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(ge:SI (match_dup 3) (const_int 0)))]
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(ge:SI (match_dup 3) (const_int 0)))]
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""
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"! TARGET_SOFT_FLOAT"
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"
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"
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{ operands[3] = gen_reg_rtx (SImode);
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{ operands[3] = gen_reg_rtx (SImode);
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}");
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}");
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